]> git.sur5r.net Git - u-boot/commitdiff
arm: mvebu: add DB-88F6820-AMC board
authorChris Packham <judge.packham@gmail.com>
Thu, 22 Sep 2016 00:56:14 +0000 (12:56 +1200)
committerStefan Roese <sr@denx.de>
Sat, 24 Sep 2016 08:07:48 +0000 (10:07 +0200)
This board is a plug in card for Marvell's switch system development
kits. Form-factor aside it is similar to the DB-88F6820-GP with the
following differences.
- TCLK is 200MHz
- SPI1 is used
- No SATA
- No MMC
- NAND flash

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
arch/arm/dts/Makefile
arch/arm/dts/armada-385-amc.dts [new file with mode: 0644]
arch/arm/mach-mvebu/Kconfig
board/Marvell/db-88f6820-amc/MAINTAINERS [new file with mode: 0644]
board/Marvell/db-88f6820-amc/Makefile [new file with mode: 0644]
board/Marvell/db-88f6820-amc/db-88f6820-amc.c [new file with mode: 0644]
board/Marvell/db-88f6820-amc/kwbimage.cfg [new file with mode: 0644]
configs/db-88f6820-amc_defconfig [new file with mode: 0644]
include/configs/db-88f6820-amc.h [new file with mode: 0644]

index 1d41d485558d4b3f4df131d51d5b4eaf6f3a06c4..df572880767fd10872720dfbc777bad508c08a32 100644 (file)
@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=                   \
        armada-375-db.dtb                       \
        armada-388-clearfog.dtb                 \
        armada-388-gp.dtb                       \
+       armada-385-amc.dtb                      \
        armada-xp-gp.dtb                        \
        armada-xp-maxbcm.dtb                    \
        armada-xp-synology-ds414.dtb            \
diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts
new file mode 100644 (file)
index 0000000..858138a
--- /dev/null
@@ -0,0 +1,155 @@
+/*
+ * Device Tree file for Marvell Armada 385 development board
+ * (DB-88F6820-AMC)
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       model = "Marvell Armada 385 AMC";
+       compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       aliases {
+               ethernet0 = &eth0;
+               ethernet1 = &eth1;
+               spi1 = &spi1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x00000000 0x80000000>; /* 2 GB */
+       };
+
+       soc {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                         MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+               internal-regs {
+                       i2c@11000 {
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&i2c0_pins>;
+                               status = "okay";
+                       };
+
+                       serial@12000 {
+                               /*
+                                * Exported on the micro USB connector CON16
+                                * through an FTDI
+                                */
+
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&uart0_pins>;
+                               status = "okay";
+                               u-boot,dm-pre-reloc;
+                       };
+
+                       ethernet@34000 {
+                               status = "okay";
+                               phy = <&phy1>;
+                               phy-mode = "sgmii";
+                       };
+
+                       usb@58000 {
+                               status = "okay";
+                       };
+
+                       ethernet@70000 {
+                               pinctrl-names = "default";
+                               /*
+                                * The Reference Clock 0 is used to provide a
+                                * clock to the PHY
+                                */
+                               pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+                               status = "okay";
+                               phy = <&phy0>;
+                               phy-mode = "rgmii-id";
+                       };
+
+
+                       mdio@72004 {
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&mdio_pins>;
+
+                               phy0: ethernet-phy@1 {
+                                       reg = <1>;
+                               };
+
+                               phy1: ethernet-phy@0 {
+                                       reg = <0>;
+                               };
+                       };
+               };
+
+               pcie-controller {
+                       status = "okay";
+                       pcie@1,0 {
+                               /* Port 0, Lane 0 */
+                               status = "okay";
+                       };
+
+               };
+       };
+};
+
+&spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi1_pins>;
+       status = "okay";
+       u-boot,dm-pre-reloc;
+
+       spi-flash@0 {
+               u-boot,dm-pre-reloc;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "st,m25p128", "jedec,spi-nor";
+               reg = <0>; /* Chip select 0 */
+               spi-max-frequency = <50000000>;
+               m25p,fast-read;
+       };
+};
+
+&refclk {
+       clock-frequency = <20000000>;
+};
index 8ce0c9ee45a93ac5ad3ffcb26138f3d74238867b..0fd71a717a28a3732e254bc1747fc699691575bd 100644 (file)
@@ -41,6 +41,10 @@ config TARGET_DB_88F6820_GP
        bool "Support DB-88F6820-GP"
        select 88F6820
 
+config TARGET_DB_88F6820_AMC
+       bool "Support DB-88F6820-AMC"
+       select 88F6820
+
 config TARGET_DB_MV784MP_GP
        bool "Support db-mv784mp-gp"
        select MV78460
@@ -63,6 +67,7 @@ config SYS_BOARD
        default "clearfog" if TARGET_CLEARFOG
        default "db-88f6720" if TARGET_DB_88F6720
        default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+       default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
        default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
        default "ds414" if TARGET_DS414
        default "maxbcm" if TARGET_MAXBCM
@@ -72,6 +77,7 @@ config SYS_CONFIG_NAME
        default "clearfog" if TARGET_CLEARFOG
        default "db-88f6720" if TARGET_DB_88F6720
        default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+       default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
        default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
        default "ds414" if TARGET_DS414
        default "maxbcm" if TARGET_MAXBCM
@@ -81,6 +87,7 @@ config SYS_VENDOR
        default "Marvell" if TARGET_DB_MV784MP_GP
        default "Marvell" if TARGET_DB_88F6720
        default "Marvell" if TARGET_DB_88F6820_GP
+       default "Marvell" if TARGET_DB_88F6820_AMC
        default "solidrun" if TARGET_CLEARFOG
        default "Synology" if TARGET_DS414
 
diff --git a/board/Marvell/db-88f6820-amc/MAINTAINERS b/board/Marvell/db-88f6820-amc/MAINTAINERS
new file mode 100644 (file)
index 0000000..abf5b7e
--- /dev/null
@@ -0,0 +1,6 @@
+DB_88F6820_AMC BOARD
+M:     Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:     Maintained
+F:     board/Marvell/db-88f6820-amc/
+F:     include/configs/db-88f6820-amc.h
+F:     configs/db-88f6820-amc_defconfig
diff --git a/board/Marvell/db-88f6820-amc/Makefile b/board/Marvell/db-88f6820-amc/Makefile
new file mode 100644 (file)
index 0000000..79e1a75
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := db-88f6820-amc.o
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
new file mode 100644 (file)
index 0000000..cade99c
--- /dev/null
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ETH_PHY_CTRL_REG               0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT    11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK   (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v10"
+ */
+#define DB_AMC_88F68XX_GPP_OUT_ENA_LOW                                 \
+       (~(BIT(29)))
+#define DB_AMC_88F68XX_GPP_OUT_ENA_MID                                 \
+       (~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
+#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT(29))
+#define DB_AMC_88F68XX_GPP_OUT_VAL_MID 0x0
+#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH        0x0
+#define DB_AMC_88F68XX_GPP_POL_LOW     0x0
+#define DB_AMC_88F68XX_GPP_POL_MID     0x0
+
+static struct serdes_map board_serdes_map[] = {
+       {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+       {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+       {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+       {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+       {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+       {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+       *serdes_map_array = board_serdes_map;
+       *count = ARRAY_SIZE(board_serdes_map);
+       return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map = {
+       0x1, /* active interfaces */
+       /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+       { { { {0x1, 0, 0, 0},
+             {0x1, 0, 0, 0},
+             {0x1, 0, 0, 0},
+             {0x1, 0, 0, 0},
+             {0x1, 0, 0, 0} },
+           SPEED_BIN_DDR_1866L,        /* speed_bin */
+           BUS_WIDTH_8,                /* memory_width */
+           MEM_4G,                     /* mem_size */
+           DDR_FREQ_800,               /* frequency */
+           0, 0,                       /* cas_l cas_wl */
+           HWS_TEMP_LOW} },            /* temperature */
+       5,                              /* Num Of Bus Per Interface*/
+       BUS_MASK_32BIT                  /* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+       /* Return the board topology as defined in the board code */
+       return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+       /* Configure MPP */
+       writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+       writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+       writel(0x55066011, MVEBU_MPP_BASE + 0x08);
+       writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
+       writel(0x05055555, MVEBU_MPP_BASE + 0x10);
+       writel(0x01106565, MVEBU_MPP_BASE + 0x14);
+       writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+       writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+       /* Set GPP Out value */
+       writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+       writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+       /* Set GPP Polarity */
+       writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+       writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+       /* Set GPP Out Enable */
+       writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+       writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       puts("Board: Marvell DB-88F6820-AMC\n");
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       cpu_eth_init(bis); /* Built in controller(s) come first */
+       return pci_eth_init(bis);
+}
diff --git a/board/Marvell/db-88f6820-amc/kwbimage.cfg b/board/Marvell/db-88f6820-amc/kwbimage.cfg
new file mode 100644 (file)
index 0000000..1f748db
--- /dev/null
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION                1
+
+# Boot Media configurations
+BOOT_FROM      spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
new file mode 100644 (file)
index 0000000..5784c45
--- /dev/null
@@ -0,0 +1,43 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_DB_88F6820_AMC=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
+CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
new file mode 100644 (file)
index 0000000..042ded8
--- /dev/null
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _CONFIG_DB_88F6820_AMC_H
+#define _CONFIG_DB_88F6820_AMC_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define        CONFIG_SYS_TEXT_BASE    0x00800000
+#define CONFIG_SYS_TCLK                200000000       /* 200MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH            /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_PCI
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0                MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE           0x0
+#define CONFIG_SYS_I2C_SPEED           100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_BUS          1
+#define CONFIG_SF_DEFAULT_SPEED                1000000
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_3
+
+/* Partition support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS             1
+#define CONFIG_ENV_OFFSET              (1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE                        (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE           (256 << 10) /* 256KiB sectors */
+
+#define CONFIG_PHY_MARVELL             /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT       8000    /* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET  /* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS      \
+       "fdt_high=0x10000000\0"         \
+       "initrd_high=0x10000000\0"
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH      - Booting via SPI NOR flash
+ *
+ * MMC is not populated on this board.
+ * NAND support may be added in the future.
+ */
+#define SPL_BOOT_SPI_NOR_FLASH         1
+#define CONFIG_SPL_BOOT_DEVICE         SPL_BOOT_SPI_NOR_FLASH
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE                        (140 << 10)
+#define CONFIG_SPL_TEXT_BASE           0x40000030
+#define CONFIG_SPL_MAX_SIZE            (CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR      (0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE                (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK               (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE                (CONFIG_SPL_STACK + 4)
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x24000
+#define CONFIG_SYS_U_BOOT_OFFS         CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 96
+
+#endif /* _CONFIG_DB_88F6820_AMC_H */