sc520: Define MMCR address in include file

diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index b99408cc999ce9eb0e072770122abf4e0d3a9fad..7caa4c8a6cfd7b6246592e8de5988fb905a95575 100644 (file)
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * unsigned long init_sc520_dram(void)
  */
 
-volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
+sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
 
 int cpu_init_f(void)
 {

diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S
index 63c14b7eb0ecec1b6843eb6bdc96c85a9541be2a..9f6cce3188a9afe9005f225e71b77a1c4109e790 100644 (file)
--- a/arch/i386/cpu/sc520/sc520_asm.S
+++ b/arch/i386/cpu/sc520/sc520_asm.S
@@ -142,16 +142,9 @@
  */
 
 #include <config.h>
+#include <asm/ic/sc520.h>
 
 .section .text
-.equ            DRCCTL,     0x0fffef010   /* DRAM control register */
-.equ            DRCTMCTL,   0x0fffef012   /* DRAM timing control register */
-.equ            DRCCFG,     0x0fffef014   /* DRAM bank configuration register */
-.equ            DRCBENDADR, 0x0fffef018   /* DRAM bank ending address register */
-.equ            ECCCTL,     0x0fffef020   /* DRAM ECC control register */
-.equ            ECCINT,     0x0fffefd18   /* DRAM ECC nmi-INT mapping */
-.equ            DBCTL,      0x0fffef040   /* DRAM buffer control register */
-
 .equ            CACHELINESZ, 0x00000010   /* size of our cache line (read buffer) */
 .equ            COL11_ADR,  0x0e001e00    /* 11 col addrs */
 .equ            COL10_ADR,  0x0e000e00    /* 10 col addrs */
@@ -179,27 +172,27 @@ mem_init:
 
        /* initialize dram controller registers */
        xorw    %ax, %ax
-       movl    $DBCTL, %edi
+       movl    $SC520_DBCTL, %edi
        movb    %al, (%edi)             /* disable write buffer */
 
-       movl    $ECCCTL, %edi
+       movl    $SC520_ECCCTL, %edi
        movb    %al, (%edi)             /* disable ECC */
 
-       movl    $DRCTMCTL, %edi
+       movl    $SC520_DRCTMCTL, %edi
        movb    $0x1e, %al              /* Set SDRAM timing for slowest */
        movb    %al, (%edi)
 
        /* setup loop to do 4 external banks starting with bank 3 */
        movl    $0xff000000, %eax       /* enable last bank and setup */
-       movl    $DRCBENDADR, %edi       /* ending address register */
+       movl    $SC520_DRCBENDADR, %edi /* ending address register */
        movl    %eax, (%edi)
 
-       movl    $DRCCFG, %edi           /* setup */
+       movl    $SC520_DRCCFG, %edi             /* setup */
        movw    $0xbbbb, %ax            /* dram config register for  */
        movw    %ax, (%edi)
 
        /* issue a NOP to all DRAMs */
-       movl    $DRCCTL, %edi           /* setup DRAM control register with */
+       movl    $SC520_DRCCTL, %edi     /* setup DRAM control register with */
        movb    $0x01, %al              /* Disable refresh,disable write buffer */
        movb    %al, (%edi)
        movl    $CACHELINESZ, %esi      /* just a dummy address to write for */
@@ -409,7 +402,7 @@ bad_reint:
        /*
         * issue all banks precharge
         */
-       movl    $DRCCTL, %esi           /* setup DRAM control register with */
+       movl    $SC520_DRCCTL, %esi     /* setup DRAM control register with */
        movb    $0x02, %al              /* All banks precharge */
        movb    %al, (%esi)
        movl    $CACHELINESZ, %esi      /* address to init read buffer */
@@ -418,7 +411,7 @@ bad_reint:
        /*
         * update ENDING ADDRESS REGISTER
         */
-       movl    $DRCBENDADR, %edi       /* DRAM ending address register */
+       movl    $SC520_DRCBENDADR, %edi /* DRAM ending address register */
        movl    %ecx, %ebx
        addl    %ebx, %edi
        movb    %dh, (%edi)
@@ -435,7 +428,7 @@ bad_reint:
        shlw    %cl, %bx
        notw    %bx
        xchgw   %cx, %ax
-       movl    $DRCCFG, %edi
+       movl    $SC520_DRCCFG, %edi
        movw    (%edi), %ax
        andw    %bx, %ax
        orw     %dx, %ax
@@ -444,7 +437,7 @@ bad_reint:
 
        decw    %cx
        movl    %ecx, %ebx
-       movl    $DRCBENDADR, %edi       /* DRAM ending address register */
+       movl    $SC520_DRCBENDADR, %edi /* DRAM ending address register */
        movb    $0xff, %al
        addl    %ebx, %edi
        movb    %al, (%edi)
@@ -452,7 +445,7 @@ bad_reint:
        /*
         * set control register to NORMAL mode
         */
-       movl    $DRCCTL, %esi           /* setup DRAM control register with */
+       movl    $SC520_DRCCTL, %esi     /* setup DRAM control register with */
        movb    $0x00, %al              /* Normal mode value */
        movb    %al, (%esi)
        movl    $CACHELINESZ, %esi      /* address to init read buffer */
@@ -460,7 +453,7 @@ bad_reint:
        jmp     nextbank
 
 cleanup:
-       movl    $DRCBENDADR, %edi       /* DRAM ending address register  */
+       movl    $SC520_DRCBENDADR, %edi /* DRAM ending address register  */
        movw    $0x04, %cx
        xorw    %ax, %ax
 cleanuplp:
@@ -482,7 +475,7 @@ emptybank:
 
 #if defined CONFIG_SYS_SDRAM_DRCTMCTL
        /* just have your hardware desinger _GIVE_ you what you need here! */
-       movl    $DRCTMCTL, %edi
+       movl    $SC520_DRCTMCTL, %edi
        movb    $CONFIG_SYS_SDRAM_DRCTMCTL, %al
        movb    %al, (%edi)
 #else
@@ -491,7 +484,7 @@ emptybank:
         * Set the CAS latency now since it is hard to do
         * when we run from the RAM
         */
-       movl    $DRCTMCTL, %edi /* DRAM timing register */
+       movl    $SC520_DRCTMCTL, %edi   /* DRAM timing register */
        movb    (%edi), %al
 #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
        andb    $0xef, %al
@@ -502,13 +495,13 @@ emptybank:
        movb    %al, (%edi)
 #endif
 #endif
-       movl    $DRCCTL, %edi   /* DRAM Control register */
+       movl    $SC520_DRCCTL, %edi     /* DRAM Control register */
        movb    $0x03, %al      /* Load mode register cmd */
        movb    %al, (%edi)
        movw    %ax, (%esi)
 
 
-       movl    $DRCCTL, %edi   /* DRAM Control register */
+       movl    $SC520_DRCCTL, %edi     /* DRAM Control register */
        movb    $0x18, %al      /*  Enable refresh and NORMAL mode */
        movb    %al, (%edi)
 
@@ -553,16 +546,16 @@ set_ecc:
 
        /* enable read, write buffers */
        movb    $0x11, %al
-       movl    $DBCTL, %edi
+       movl    $SC520_DBCTL, %edi
        movb    %al, (%edi)
 
        /* enable NMI mapping for ECC */
-       movl    $ECCINT, %edi
+       movl    $SC520_ECCINT, %edi
        movb    $0x10, %al
        movb    %al, (%edi)
 
        /* Turn on ECC */
-       movl    $ECCCTL, %edi
+       movl    $SC520_ECCCTL, %edi
        movb    $0x05, %al
        movb    %al,(%edi)
 
@@ -576,7 +569,7 @@ out:
  */
 .globl get_mem_size
 get_mem_size:
-       movl    $DRCBENDADR, %edi       /* DRAM ending address register */
+       movl    $SC520_DRCBENDADR, %edi /* DRAM ending address register */
 
 bank0: movl    (%edi), %eax
        movl    %eax, %ecx

diff --git a/arch/i386/include/asm/ic/sc520.h b/arch/i386/include/asm/ic/sc520.h
index 053d9c6773a755ecf12c2e6ebca24016552f276d..5e7fb476671cd58fe9c0858b257aec8ca2461007 100644 (file)
--- a/arch/i386/include/asm/ic/sc520.h
+++ b/arch/i386/include/asm/ic/sc520.h
@@ -252,16 +252,38 @@ typedef struct sc520_mmcr {
        u8  pad_0xdc0[0x0240];
 } sc520_mmcr_t;
 
-extern volatile sc520_mmcr_t *sc520_mmcr;
+extern sc520_mmcr_t *sc520_mmcr;
 
 #endif
 
-/* MMCR Offsets (required for assembler code */
-#define SC520_DBCTL            0x0040  /* SDRAM Buffer Control Register */
-#define SC520_PAR14            0x00c0  /* Programmable Address Region 14 Register */
-#define SC520_PAR15            0x00c4  /* Programmable Address Region 15 Register */
-#define SC520_SWTMRMILLI       0x0c60  /* Software Timer Millisecond Count */
-#define SC520_SWTMRMICRO       0x0c62  /* Software Timer Microsecond Count */
+/* Memory Mapped Control Registers (MMCR) Base Address */
+#define SC520_MMCR_BASE                0xfffef000
+
+/* MMCR Addresses (required for assembler code) */
+#define SC520_DRCCTL           (SC520_MMCR_BASE + 0x010)
+#define SC520_DRCTMCTL         (SC520_MMCR_BASE + 0x012)
+#define SC520_DRCCFG           (SC520_MMCR_BASE + 0x014)
+#define SC520_DRCBENDADR       (SC520_MMCR_BASE + 0x018)
+#define SC520_ECCCTL           (SC520_MMCR_BASE + 0x020)
+#define SC520_DBCTL            (SC520_MMCR_BASE + 0x040)
+#define SC520_ECCINT           (SC520_MMCR_BASE + 0xd18)
+
+#define SC520_PAR0             (SC520_MMCR_BASE + 0x088)
+#define SC520_PAR1             (SC520_PAR0 + (0x04 * 1))
+#define SC520_PAR2             (SC520_PAR0 + (0x04 * 2))
+#define SC520_PAR3             (SC520_PAR0 + (0x04 * 3))
+#define SC520_PAR4             (SC520_PAR0 + (0x04 * 4))
+#define SC520_PAR5             (SC520_PAR0 + (0x04 * 5))
+#define SC520_PAR6             (SC520_PAR0 + (0x04 * 6))
+#define SC520_PAR7             (SC520_PAR0 + (0x04 * 7))
+#define SC520_PAR8             (SC520_PAR0 + (0x04 * 8))
+#define SC520_PAR9             (SC520_PAR0 + (0x04 * 9))
+#define SC520_PAR10            (SC520_PAR0 + (0x04 * 10))
+#define SC520_PAR11            (SC520_PAR0 + (0x04 * 11))
+#define SC520_PAR12            (SC520_PAR0 + (0x04 * 12))
+#define SC520_PAR13            (SC520_PAR0 + (0x04 * 13))
+#define SC520_PAR14            (SC520_PAR0 + (0x04 * 14))
+#define SC520_PAR15            (SC520_PAR0 + (0x04 * 15))
 
 /* MMCR Register bits (not all of them :) ) */
 

diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
index 06cfd558d1306b3020f5dcee0092cc106c6e94b4..183309cb7f10343c3e5e1abaa97bc24fee4654d4 100644 (file)
--- a/board/eNET/eNET_start16.S
+++ b/board/eNET/eNET_start16.S
@@ -30,6 +30,7 @@
 /* #include <asm/ic/sc520_defs.h> */
 
 #include "hardware.h"
+#include <asm/ic/sc520.h>
 
 .text
 .section .start16, "ax"
@@ -46,17 +47,17 @@ board_init16:
        movw    %ax, %ds
 
        /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
-       movl    $0x00c0, %edi           /* SC520_PAR14 */
+       movl    $(SC520_PAR14 - SC520_MMCR_BASE), %edi
        movl    $0x8bfff800, %eax       /* TODO: Check this */
        movl    %eax, (%di)
 
        /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
-       movl    $0x00c4, %edi           /* SC520_PAR15 */
+       movl    $(SC520_PAR15 - SC520_MMCR_BASE), %edi
        movl    $0x38201000, %eax
        movl    %eax, (%di)
 
        /* Disable SDRAM write buffer */
-       movw    $0x0040, %di            /* SC520_DBCTL */
+       movw    $(SC520_DBCTL - SC520_MMCR_BASE), %di
        xorw    %ax, %ax
        movb    %al, (%di)