int i;
for (i = 0; i < 100; i++) {
sdelay(450);
- if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
+ if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))
break;
}
}
-void init_pll(const struct pll_init_data *data)
+static inline void bypass_main_pll(const struct pll_init_data *data)
{
- u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |
+ PLLCTL_PLLEN_MASK);
+
+ /* 4 cycles of reference clock CLKIN*/
+ sdelay(340);
+}
+
+static void configure_mult_div(const struct pll_init_data *data)
+{
+ u32 pllm, plld, bwadj;
pllm = data->pll_m - 1;
- plld = (data->pll_d - 1) & PLL_DIV_MASK;
- pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
+ plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;
- if (data->pll == MAIN_PLL) {
- /* The requered delay before main PLL configuration */
- sdelay(210000);
+ /* Program Multiplier */
+ if (data->pll == MAIN_PLL)
+ pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
- tmp = pllctl_reg_read(data->pll, secctl);
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_PLLM_MASK,
+ pllm << CFG_PLLCTL0_PLLM_SHIFT);
+
+ /* Program BWADJ */
+ bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_BWADJ_MASK,
+ (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) &
+ CFG_PLLCTL0_BWADJ_MASK);
+ bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS;
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
+ CFG_PLLCTL1_BWADJ_MASK, bwadj);
+
+ /* Program Divider */
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_PLLD_MASK, plld);
+}
- if (tmp & (PLLCTL_BYPASS)) {
- setbits_le32(keystone_pll_regs[data->pll].reg1,
- BIT(MAIN_ENSAT_OFFSET));
+void configure_main_pll(const struct pll_init_data *data)
+{
+ u32 tmp, pllod, i, alnctl_val = 0;
+ u32 *offset;
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
- PLLCTL_PLLENSRC);
- sdelay(340);
+ pllod = data->pll_od - 1;
- pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- sdelay(21000);
+ /* 100 micro sec for stabilization */
+ sdelay(210000);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- } else {
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
- PLLCTL_PLLENSRC);
- sdelay(340);
- }
+ tmp = pllctl_reg_read(data->pll, secctl);
- pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
+ /* Check for Bypass */
+ if (tmp & SECCTL_BYPASS_MASK) {
+ setbits_le32(keystone_pll_regs[data->pll].reg1,
+ CFG_PLLCTL1_ENSAT_MASK);
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLLM_MULT_HI_SMASK, (pllm << 6));
+ bypass_main_pll(data);
- /* Set the BWADJ (12 bit field) */
- tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLL_BWADJ_LO_SMASK,
- (tmp_ctl << PLL_BWADJ_LO_SHIFT));
- clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
- PLL_BWADJ_HI_MASK,
- (tmp_ctl >> 8));
+ /* Powerdown and powerup Main Pll */
+ pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
+ /* 5 micro sec */
+ sdelay(21000);
- /*
- * Set the pll divider (6 bit field) *
- * PLLD[5:0] is located in MAINPLLCTL0
- */
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLL_DIV_MASK, plld);
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
+ } else {
+ bypass_main_pll(data);
+ }
- /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
- pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
- (pllod << PLL_CLKOD_SHIFT));
- wait_for_completion(data);
+ configure_mult_div(data);
- pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
- pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
- pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
- pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
- pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
+ /* Program Output Divider */
+ pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,
+ ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK));
- pllctl_reg_setbits(data->pll, alnctl, 0x1f);
+ /* Program PLLDIVn */
+ wait_for_completion(data);
+ for (i = 0; i < PLLDIV_MAX; i++) {
+ if (i < 3)
+ offset = pllctl_reg(data->pll, div1) + i;
+ else
+ offset = pllctl_reg(data->pll, div4) + (i - 3);
+ if (divn_val[i] != -1) {
+ __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset);
+ alnctl_val |= BIT(i);
+ }
+ }
+
+ if (alnctl_val) {
+ pllctl_reg_setbits(data->pll, alnctl, alnctl_val);
/*
* Set GOSET bit in PLLCMD to initiate the GO operation
* to change the divide
*/
- pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
- sdelay(1500); /* wait for the phase adj */
+ pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);
wait_for_completion(data);
+ }
- /* Reset PLL */
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
- sdelay(21000); /* Wait for a minimum of 7 us*/
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
- sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
-
- pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
-
- tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+ /* Reset PLL */
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
+ sdelay(21000); /* Wait for a minimum of 7 us*/
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
+ sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
-#ifndef CONFIG_SOC_K2E
- } else if (data->pll == TETRIS_PLL) {
- bwadj = pllm >> 1;
- /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
- setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
- * only applicable for Kepler
- */
- clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
- /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
- setbits_le32(keystone_pll_regs[data->pll].reg1 ,
- PLL_PLLRST | PLLCTL_ENSAT);
-
- /*
- * 3 Program PLLM and PLLD in PLLCTL0 register
- * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
- * PLLCTL1 register. BWADJ value must be set
- * to ((PLLM + 1) >> 1) – 1)
- */
- tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
- (pllm << 6) |
- (plld & PLL_DIV_MASK) |
- (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
- /* Set BWADJ[11:8] bits */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
- tmp &= ~(PLL_BWADJ_HI_MASK);
- tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
- /*
- * 5 Wait for at least 5 us based on the reference
- * clock (PLL reset time)
- */
- sdelay(21000); /* Wait for a minimum of 7 us*/
-
- /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
- clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
- /*
- * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
- * (PLL lock time)
- */
- sdelay(105000);
- /* 8 disable bypass */
- clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
- * only applicable for Kepler
- */
- setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
-#endif
- } else {
- setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
- /*
- * process keeps state of Bypass bit while programming
- * all other DDR PLL settings
- */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
- tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
+ /* Enable PLL */
+ pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);
+}
- /*
- * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
- * bypass disabled
- */
- bwadj = pllm >> 1;
- tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
- (pllm << PLL_MULT_SHIFT) |
- (plld & PLL_DIV_MASK) |
- (pllod << PLL_CLKOD_SHIFT);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
- /* Set BWADJ[11:8] bits */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
- tmp &= ~(PLL_BWADJ_HI_MASK);
- tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
-
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
-
- /* Reset bit: bit 14 for both DDR3 & PASS PLL */
- tmp = PLL_PLLRST;
- /* Set RESET bit = 1 */
- setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
- /* Wait for a minimum of 7 us*/
- sdelay(21000);
- /* Clear RESET bit */
- clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
- sdelay(105000);
+void configure_secondary_pll(const struct pll_init_data *data)
+{
+ int pllod = data->pll_od - 1;
+
+ /* Enable Bypass mode */
+ setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
+ setbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_BYPASS_MASK);
+
+ /* Enable Glitch free bypass for ARM PLL */
+ if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
+ clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
+
+ configure_mult_div(data);
+
+ /* Program Output Divider */
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_CLKOD_MASK,
+ (pllod << CFG_PLLCTL0_CLKOD_SHIFT) &
+ CFG_PLLCTL0_CLKOD_MASK);
+
+ /* Reset PLL */
+ setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
+ /* Wait for 5 micro seconds */
+ sdelay(21000);
+
+ /* Select the Output of PASS PLL as input to PASS */
+ if (data->pll == PASS_PLL)
+ setbits_le32(keystone_pll_regs[data->pll].reg1,
+ CFG_PLLCTL1_PAPLL_MASK);
+
+ /* Select the Output of ARM PLL as input to ARM */
+ if (data->pll == TETRIS_PLL)
+ setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
+
+ clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
+ /* Wait for 500 * REFCLK cucles * (PLLD + 1) */
+ sdelay(105000);
+
+ /* Switch to PLL mode */
+ clrbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_BYPASS_MASK);
+}
- /* clear BYPASS (Enable PLL Mode) */
- clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- sdelay(21000); /* Wait for a minimum of 7 us*/
- }
+void init_pll(const struct pll_init_data *data)
+{
+ if (data->pll == MAIN_PLL)
+ configure_main_pll(data);
+ else
+ configure_secondary_pll(data);
/*
* This is required to provide a delay between multiple
{
return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);
}
-
-void pass_pll_pa_clk_enable(void)
-{
- u32 reg;
-
- reg = readl(keystone_pll_regs[PASS_PLL].reg1);
-
- reg |= PLLCTL_PAPLL;
- writel(reg, keystone_pll_regs[PASS_PLL].reg1);
-
- /* wait till clock is enabled */
- sdelay(15000);
-}
#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
-/* PLLCTL Bits */
#define PLLCTL_BYPASS BIT(23)
#define PLL_PLLRST BIT(14)
#define PLLCTL_PAPLL BIT(13)
#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
#define PLL_BWADJ_HI_MASK 0xf
-#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1)
-#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4)
-#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17)
+/* PLLCTL Bits */
+#define PLLCTL_PLLENSRC_SHIF 5
+#define PLLCTL_PLLENSRC_MASK BIT(5)
+#define PLLCTL_PLLRST_SHIFT 3
+#define PLLCTL_PLLRST_MASK BIT(3)
+#define PLLCTL_PLLPWRDN_SHIFT 1
+#define PLLCTL_PLLPWRDN_MASK BIT(1)
+#define PLLCTL_PLLEN_SHIFT 0
+#define PLLCTL_PLLEN_MASK BIT(0)
+
+/* SECCTL Bits */
+#define SECCTL_BYPASS_SHIFT 23
+#define SECCTL_BYPASS_MASK BIT(23)
+#define SECCTL_OP_DIV_SHIFT 19
+#define SECCTL_OP_DIV_MASK (0xf << 19)
+
+/* PLLM Bits */
+#define PLLM_MULT_LO_SHIFT 0
+#define PLLM_MULT_LO_MASK 0x3f
+#define PLLM_MULT_LO_BITS 6
+
+/* PLLDIVn Bits */
+#define PLLDIV_ENABLE_SHIFT 15
+#define PLLDIV_ENABLE_MASK BIT(15)
+#define PLLDIV_RATIO_SHIFT 0x0
+#define PLLDIV_RATIO_MASK 0xff
+#define PLLDIV_MAX 16
+
+/* PLLCMD Bits */
+#define PLLCMD_GOSET_SHIFT 0
+#define PLLCMD_GOSET_MASK BIT(0)
+
+/* PLLSTAT Bits */
+#define PLLSTAT_GOSTAT_SHIFT 0
+#define PLLSTAT_GOSTAT_MASK BIT(0)
+
+/* Device Config PLLCTL0 */
+#define CFG_PLLCTL0_BWADJ_SHIFT 24
+#define CFG_PLLCTL0_BWADJ_MASK (0xff << 24)
+#define CFG_PLLCTL0_BWADJ_BITS 8
+#define CFG_PLLCTL0_BYPASS_SHIFT 23
+#define CFG_PLLCTL0_BYPASS_MASK BIT(23)
+#define CFG_PLLCTL0_CLKOD_SHIFT 19
+#define CFG_PLLCTL0_CLKOD_MASK (0xf << 19)
+#define CFG_PLLCTL0_PLLM_HI_SHIFT 12
+#define CFG_PLLCTL0_PLLM_HI_MASK (0x7f << 12)
+#define CFG_PLLCTL0_PLLM_SHIFT 6
+#define CFG_PLLCTL0_PLLM_MASK (0x1fff << 6)
+#define CFG_PLLCTL0_PLLD_SHIFT 0
+#define CFG_PLLCTL0_PLLD_MASK 0x3f
+
+/* Device Config PLLCTL1 */
+#define CFG_PLLCTL1_RST_SHIFT 14
+#define CFG_PLLCTL1_RST_MASK BIT(14)
+#define CFG_PLLCTL1_PAPLL_SHIFT 13
+#define CFG_PLLCTL1_PAPLL_MASK BIT(13)
+#define CFG_PLLCTL1_ENSAT_SHIFT 6
+#define CFG_PLLCTL1_ENSAT_MASK BIT(6)
+#define CFG_PLLCTL1_BWADJ_SHIFT 0
+#define CFG_PLLCTL1_BWADJ_MASK 0xf
+
+#define MISC_CTL1_ARM_PLL_EN BIT(13)
#endif /* _CLOCK_DEFS_H_ */
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