u32 value;
        struct mii_dev bus;
        bus.priv = priv->mac->phyregs;
+       bool sgmii_2500 = (priv->enet_if ==
+                       PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+
+       /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
+       value = PHY_SGMII_IF_MODE_SGMII;
+       if (!sgmii_2500)
+               value |= PHY_SGMII_IF_MODE_AN;
 
-       /* SGMII IF mode + AN enable */
-       value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII;
        memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
 
        /* Dev ability according to SGMII specification */
        memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
 
        /* Restart AN */
-       value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
+       value = PHY_SGMII_CR_DEF_VAL;
+       if (!sgmii_2500)
+               value |= PHY_SGMII_CR_RESET_AN;
        memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
 #else
        struct dtsec *regs = priv->mac->base;
        out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
 #endif
 
-       if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
+       if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+           fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
                dtsec_configure_serdes(fm_eth);
 }
 
 
        PHY_INTERFACE_MODE_MII,
        PHY_INTERFACE_MODE_GMII,
        PHY_INTERFACE_MODE_SGMII,
+       PHY_INTERFACE_MODE_SGMII_2500,
        PHY_INTERFACE_MODE_QSGMII,
        PHY_INTERFACE_MODE_TBI,
        PHY_INTERFACE_MODE_RMII,
        [PHY_INTERFACE_MODE_MII]                = "mii",
        [PHY_INTERFACE_MODE_GMII]               = "gmii",
        [PHY_INTERFACE_MODE_SGMII]              = "sgmii",
+       [PHY_INTERFACE_MODE_SGMII_2500]         = "sgmii-2500",
        [PHY_INTERFACE_MODE_QSGMII]             = "qsgmii",
        [PHY_INTERFACE_MODE_TBI]                = "tbi",
        [PHY_INTERFACE_MODE_RMII]               = "rmii",