]> git.sur5r.net Git - u-boot/commitdiff
stm32mp1: add FUSE command support
authorPatrick Delaunay <patrick.delaunay@st.com>
Thu, 17 May 2018 13:24:06 +0000 (15:24 +0200)
committerTom Rini <trini@konsulko.com>
Sat, 26 May 2018 22:19:18 +0000 (18:19 -0400)
Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
MAINTAINERS
arch/arm/Kconfig
configs/stm32mp15_basic_defconfig
drivers/misc/Kconfig
drivers/misc/Makefile
drivers/misc/stm32mp_fuse.c [new file with mode: 0644]

index 5670917b41b9299a77d3c2ac7c800a1b46e5be55..3209dcd3184444eba23e88ec50376f312cf8a55e 100644 (file)
@@ -204,6 +204,7 @@ M:  Patrick Delaunay <patrick.delaunay@st.com>
 S:     Maintained
 F:     arch/arm/mach-stm32mp
 F:     drivers/clk/clk_stm32mp1.c
+F:     drivers/misc/stm32mp_fuse.c
 F:     drivers/ram/stm32mp1/
 
 ARM STM STV0991
index 0d1802b9f9595d41a3743afe87db55de9273a7e7..582e84cf4014555bd593459da994a17b65d7df7b 100644 (file)
@@ -1225,6 +1225,7 @@ config ARCH_STM32MP
        select DM_SERIAL
        select OF_CONTROL
        select OF_LIBFDT
+       select MISC
        select PINCTRL
        select REGMAP
        select SUPPORT_SPL
index b1c3690c009437770c92b3bf335e9a6069a14ee2..9e43cc969850579b0b8d044281ad51ae024bb84d 100644 (file)
@@ -18,6 +18,7 @@ CONFIG_SYS_PROMPT="STM32MP> "
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
index be900cf4d6ecf89fff7ec078aef6dabae05a70d2..17b3a805a2d581c2762c995d557fd4e45217e846 100644 (file)
@@ -158,6 +158,15 @@ config PCA9551_I2C_ADDR
        help
          The I2C address of the PCA9551 LED controller.
 
+config STM32MP_FUSE
+       bool "Enable STM32MP fuse wrapper providing the fuse API"
+       depends on ARCH_STM32MP && MISC
+       default y if CMD_FUSE
+       help
+         If you say Y here, you will get support for the fuse API (OTP)
+         for STM32MP architecture.
+         This API is needed for CMD_FUSE.
+
 config STM32_RCC
        bool "Enable RCC driver for the STM32 SoC's family"
        depends on STM32 && MISC
index e362609d62a4ea0250bf99157b7457a08eb33fb7..4ce9d213f06f964f5840c7baa9c8061b814a3d39 100644 (file)
@@ -51,5 +51,6 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_QFW) += qfw.o
 obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
 obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
+obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
 obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
 obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
diff --git a/drivers/misc/stm32mp_fuse.c b/drivers/misc/stm32mp_fuse.c
new file mode 100644 (file)
index 0000000..2d66135
--- /dev/null
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <command.h>
+#include <misc.h>
+#include <errno.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+#define STM32MP_OTP_BANK       0
+
+/*
+ * The 'fuse' command API
+ */
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+       int ret = 0;
+       struct udevice *dev;
+
+       switch (bank) {
+       case STM32MP_OTP_BANK:
+               ret = uclass_get_device_by_driver(UCLASS_MISC,
+                                                 DM_GET_DRIVER(stm32mp_bsec),
+                                                 &dev);
+               if (ret)
+                       return ret;
+               ret = misc_read(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET,
+                               val, 4);
+               break;
+
+       default:
+               printf("stm32mp %s: wrong value for bank %i\n", __func__, bank);
+               ret = -EINVAL;
+               break;
+       }
+
+       return ret;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+       struct udevice *dev;
+       int ret;
+
+       switch (bank) {
+       case STM32MP_OTP_BANK:
+               ret = uclass_get_device_by_driver(UCLASS_MISC,
+                                                 DM_GET_DRIVER(stm32mp_bsec),
+                                                 &dev);
+               if (ret)
+                       return ret;
+               ret = misc_write(dev, word * 4 + STM32_BSEC_OTP_OFFSET,
+                                &val, 4);
+               break;
+
+       default:
+               printf("stm32mp %s: wrong value for bank %i\n", __func__, bank);
+               ret = -EINVAL;
+               break;
+       }
+
+       return ret;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+       struct udevice *dev;
+       int ret;
+
+       switch (bank) {
+       case STM32MP_OTP_BANK:
+               ret = uclass_get_device_by_driver(UCLASS_MISC,
+                                                 DM_GET_DRIVER(stm32mp_bsec),
+                                                 &dev);
+               if (ret)
+                       return ret;
+               ret = misc_read(dev, word * 4 + STM32_BSEC_OTP_OFFSET, val, 4);
+               break;
+
+       default:
+               printf("stm32mp %s: wrong value for bank %i\n", __func__, bank);
+               ret = -EINVAL;
+               break;
+       }
+
+       return ret;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+       struct udevice *dev;
+       int ret;
+
+       switch (bank) {
+       case STM32MP_OTP_BANK:
+               ret = uclass_get_device_by_driver(UCLASS_MISC,
+                                                 DM_GET_DRIVER(stm32mp_bsec),
+                                                 &dev);
+               if (ret)
+                       return ret;
+               ret = misc_write(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET,
+                                &val, 4);
+               break;
+
+       default:
+               printf("stm32mp %s: wrong value for bank %i\n",
+                      __func__, bank);
+               ret = -EINVAL;
+               break;
+       }
+
+       return ret;
+}