]> git.sur5r.net Git - u-boot/commitdiff
rockchip: enable SYS_NS16550 for all SoCs by default
authorKever Yang <kever.yang@rock-chips.com>
Thu, 19 Apr 2018 03:37:09 +0000 (11:37 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Wed, 25 Apr 2018 20:20:07 +0000 (22:20 +0200)
All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.

Version-changes: 2
- use imply instead of select

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
arch/arm/Kconfig
arch/arm/mach-rockchip/Kconfig
include/configs/rk3036_common.h
include/configs/rk3128_common.h
include/configs/rk322x_common.h
include/configs/rk3288_common.h
include/configs/rv1108_common.h

index 7212fc5afa72c2bfeee8e5918af13b79d7c33edf..c930fa284600aabbe5931afcb7fd73a0aeae454a 100644 (file)
@@ -1185,6 +1185,7 @@ config ARCH_ROCKCHIP
        imply TPL_SYSRESET
        imply ADC
        imply SARADC_ROCKCHIP
+       imply SYS_NS16550
 
 config TARGET_THUNDERX_88XX
        bool "Support ThunderX 88xx"
index 0adaed43677ac686a70d9a6335b1e2631c3d36f8..007cb22a349e15d4b5fb5e5bf5ef4cd78320e678 100644 (file)
@@ -103,7 +103,6 @@ config ROCKCHIP_RK3368
        imply SPL_SERIAL_SUPPORT
        imply TPL_SERIAL_SUPPORT
        select DEBUG_UART_BOARD_INIT
-       select SYS_NS16550
        help
          The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
          into a big and little cluster with 4 cores each) Cortex-A53 including
index f39a272e6d211c783183520a66c4f7f7acdb730a..c5ec864b1ed0e935cf6660583930f0adb08d1702 100644 (file)
@@ -18,9 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE          0x200440a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR                0x60100000
 #define CONFIG_SYS_LOAD_ADDR           0x60800800
 #define CONFIG_SPL_STACK               0x10081fff
index bd8019c6a56a7ba715627286d83934c00ff496aa..c593f18fdbeb950a317b7497f44859767a93affc 100644 (file)
@@ -19,8 +19,6 @@
 #define CONFIG_SYS_TIMER_BASE          0x200440a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR                0x60100000
 #define CONFIG_SYS_LOAD_ADDR           0x60800800
 
index b437b858c3607505128369b20196f78c86537874..0fb72214f4a8bd2880103b2aa702bb1bc6b7e278 100644 (file)
@@ -18,7 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE          0x110c00a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
 #define CONFIG_SYS_INIT_SP_ADDR                0x60100000
 #define CONFIG_SYS_LOAD_ADDR           0x60800800
 #define CONFIG_SPL_STACK               0x10088000
index 9b7b24ff967b2ba346b875123e7b6fa3aa13cf3a..23dbfecf018cd0fc04d28089652e0fdd0b6e340a 100644 (file)
@@ -19,8 +19,6 @@
 #define        CONFIG_SYS_TIMER_BASE           0xff810020 /* TIMER7 */
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
 #endif
index 349c53c2898d53c365e6b6267d78b2533da7a542..cd204e97184fd006fba0ca86206a675d34625bfa 100644 (file)
@@ -18,9 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE          0x10350020
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_SDRAM_BASE          0x60000000
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE + 0x100000)