]> git.sur5r.net Git - u-boot/commitdiff
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
authorTom Rini <trini@konsulko.com>
Sat, 4 Jun 2016 12:49:08 +0000 (08:49 -0400)
committerTom Rini <trini@konsulko.com>
Sat, 4 Jun 2016 12:49:08 +0000 (08:49 -0400)
79 files changed:
arch/arm/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/Makefile
arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 [deleted file]
arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 [deleted file]
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-layerscape/soc.c
arch/arm/dts/Makefile
arch/arm/dts/fsl-ls1012a-frdm.dts [new file with mode: 0644]
arch/arm/dts/fsl-ls1012a-frdm.dtsi [new file with mode: 0644]
arch/arm/dts/fsl-ls1012a-qds.dts [new file with mode: 0644]
arch/arm/dts/fsl-ls1012a-qds.dtsi [new file with mode: 0644]
arch/arm/dts/fsl-ls1012a-rdb.dts [new file with mode: 0644]
arch/arm/dts/fsl-ls1012a-rdb.dtsi [new file with mode: 0644]
arch/arm/dts/fsl-ls1012a.dtsi [new file with mode: 0644]
arch/arm/include/asm/arch-fsl-layerscape/config.h
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
arch/arm/include/asm/arch-fsl-layerscape/soc.h
board/freescale/common/ls102xa_stream_id.c
board/freescale/common/qixis.c
board/freescale/ls1012afrdm/Kconfig [new file with mode: 0644]
board/freescale/ls1012afrdm/MAINTAINERS [new file with mode: 0644]
board/freescale/ls1012afrdm/Makefile [new file with mode: 0644]
board/freescale/ls1012afrdm/README [new file with mode: 0644]
board/freescale/ls1012afrdm/ls1012afrdm.c [new file with mode: 0644]
board/freescale/ls1012aqds/Kconfig [new file with mode: 0644]
board/freescale/ls1012aqds/MAINTAINERS [new file with mode: 0644]
board/freescale/ls1012aqds/Makefile [new file with mode: 0644]
board/freescale/ls1012aqds/README [new file with mode: 0644]
board/freescale/ls1012aqds/ls1012aqds.c [new file with mode: 0644]
board/freescale/ls1012aqds/ls1012aqds_qixis.h [new file with mode: 0644]
board/freescale/ls1012ardb/Kconfig [new file with mode: 0644]
board/freescale/ls1012ardb/MAINTAINERS [new file with mode: 0644]
board/freescale/ls1012ardb/Makefile [new file with mode: 0644]
board/freescale/ls1012ardb/README [new file with mode: 0644]
board/freescale/ls1012ardb/ls1012ardb.c [new file with mode: 0644]
board/freescale/ls1021aqds/ddr.h
board/freescale/ls1043aqds/README
board/freescale/ls1043aqds/ddr.h
board/freescale/ls1043aqds/ls1043aqds.c
board/freescale/ls1043ardb/README
board/freescale/ls1043ardb/ddr.h
board/freescale/ls2080aqds/README
board/freescale/ls2080aqds/ddr.h
board/freescale/ls2080aqds/ls2080aqds.c
board/freescale/ls2080ardb/README
board/freescale/ls2080ardb/ddr.h
board/freescale/ls2080ardb/ls2080ardb.c
board/freescale/t102xqds/ddr.c
board/freescale/t102xrdb/ddr.c
board/freescale/t1040qds/ddr.h
board/freescale/t104xrdb/ddr.h
board/freescale/t208xqds/ddr.h
board/freescale/t208xrdb/ddr.h
board/freescale/t4qds/ddr.h
board/freescale/t4rdb/ddr.h
configs/ls1012afrdm_qspi_defconfig [new file with mode: 0644]
configs/ls1012aqds_qspi_defconfig [new file with mode: 0644]
configs/ls1012ardb_qspi_defconfig [new file with mode: 0644]
drivers/ddr/fsl/ctrl_regs.c
drivers/ddr/fsl/fsl_ddr_gen4.c
drivers/ddr/fsl/options.c
drivers/mmc/fsl_esdhc.c
drivers/mtd/spi/sf_params.c
drivers/mtd/spi/spi_flash.c
drivers/pci/pcie_layerscape.c
include/configs/ls1012a_common.h [new file with mode: 0644]
include/configs/ls1012afrdm.h [new file with mode: 0644]
include/configs/ls1012aqds.h [new file with mode: 0644]
include/configs/ls1012ardb.h [new file with mode: 0644]
include/fsl_mmdc.h [new file with mode: 0644]
include/linux/usb/xhci-fsl.h

index 77eab66fb4235e5557d4ae354be82cc0d3c9fcd8..72b0aa78a56a7b779e38dd5328c62b0c9841dd91 100644 (file)
@@ -710,6 +710,33 @@ config TARGET_HIKEY
          Support for HiKey 96boards platform. It features a HI6220
          SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
 
+config TARGET_LS1012AQDS
+       bool "Support ls1012aqds"
+       select ARM64
+       help
+         Support for Freescale LS1012AQDS platform.
+         The LS1012A Development System (QDS) is a high-performance
+         development platform that supports the QorIQ LS1012A
+         Layerscape Architecture processor.
+
+config TARGET_LS1012ARDB
+       bool "Support ls1012ardb"
+       select ARM64
+       help
+         Support for Freescale LS1012ARDB platform.
+         The LS1012A Reference design board (RDB) is a high-performance
+         development platform that supports the QorIQ LS1012A
+         Layerscape Architecture processor.
+
+config TARGET_LS1012AFRDM
+       bool "Support ls1012afrdm"
+       select ARM64
+       help
+         Support for Freescale LS1012AFRDM platform.
+         The LS1012A Freedom  board (FRDM) is a high-performance
+         development platform that supports the QorIQ LS1012A
+         Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
        bool "Support ls1021aqds"
        select CPU_V7
@@ -867,6 +894,9 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
+source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
index 5f86ef90d24e5e6941d70c1cead742dbe78d596a..eb2cbc3f7e2b87587a24d4002ce280807ad8d052 100644 (file)
@@ -28,3 +28,7 @@ endif
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1012A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
deleted file mode 100644 (file)
index a6ef830..0000000
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright 2015 Freescale Semiconductor
-#
-# SPDX-License-Identifier:      GPL-2.0+
-#
-
-Freescale LayerScape with Chassis Generation 2
-
-This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
-for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
deleted file mode 100644 (file)
index f9323c1..0000000
+++ /dev/null
@@ -1,325 +0,0 @@
-#
-# Copyright 2014-2015 Freescale Semiconductor
-#
-# SPDX-License-Identifier:      GPL-2.0+
-#
-
-Freescale LayerScape with Chassis Generation 3
-
-This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
-for example LS2080A.
-
-DDR Layout
-============
-Entire DDR region splits into two regions.
- - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
- - Region 2 is at 0x80_8000_0000 to the top of total memory,
-   for example 16GB, 0x83_ffff_ffff.
-
-All DDR memory is marked as cache-enabled.
-
-When MC and Debug server is enabled, they carve 512MB away from the high
-end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
-with MC and Debug server enabled. Linux only sees 15.5GB.
-
-The reserved 512MB layout looks like
-
-   +---------------+ <-- top/end of memory
-   |    256MB      |  debug server
-   +---------------+
-   |    256MB      |  MC
-   +---------------+
-   |     ...       |
-
-MC requires the memory to be aligned with 512MB, so even debug server is
-not enabled, 512MB is reserved, not 256MB.
-
-Flash Layout
-============
-
-(1) A typical layout of various images (including Linux and other firmware images)
-   is shown below considering a 32MB NOR flash device present on most
-   pre-silicon platforms (simulator and emulator):
-
-       -------------------------
-       |       FIT Image       |
-       | (linux + DTB + RFS)   |
-       ------------------------- ----> 0x0120_0000
-       |       Debug Server FW |
-       ------------------------- ----> 0x00C0_0000
-       |       AIOP FW         |
-       ------------------------- ----> 0x0070_0000
-       |       MC FW           |
-       ------------------------- ----> 0x006C_0000
-       |       MC DPL Blob     |
-       ------------------------- ----> 0x0020_0000
-       |       BootLoader + Env|
-       ------------------------- ----> 0x0000_1000
-       |       PBI             |
-       ------------------------- ----> 0x0000_0080
-       |       RCW             |
-       ------------------------- ----> 0x0000_0000
-
-       32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
-
-(2) A typical layout of various images (including Linux and other firmware images)
-    is shown below considering a 128MB NOR flash device present on QDS and RDB
-    boards:
-       ----------------------------------------- ----> 0x5_8800_0000 ---
-       |       .. Unused .. (7M)               |                       |
-       ----------------------------------------- ----> 0x5_8790_0000   |
-       | FIT Image (linux + DTB + RFS) (40M)   |                       |
-       ----------------------------------------- ----> 0x5_8510_0000   |
-       |       PHY firmware (2M)               |                       |
-       ----------------------------------------- ----> 0x5_84F0_0000   | 64K
-       |       Debug Server FW (2M)            |                       | Alt
-       ----------------------------------------- ----> 0x5_84D0_0000   | Bank
-       |       AIOP FW (4M)                    |                       |
-       ----------------------------------------- ----> 0x5_8490_0000 (vbank4)
-       |       MC DPC Blob (1M)                |                       |
-       ----------------------------------------- ----> 0x5_8480_0000   |
-       |       MC DPL Blob (1M)                |                       |
-       ----------------------------------------- ----> 0x5_8470_0000   |
-       |       MC FW (4M)                      |                       |
-       ----------------------------------------- ----> 0x5_8430_0000   |
-       |       BootLoader Environment (1M)     |                       |
-       ----------------------------------------- ----> 0x5_8420_0000   |
-       |       BootLoader (1M)                 |                       |
-       ----------------------------------------- ----> 0x5_8410_0000   |
-       |       RCW and PBI (1M)                |                       |
-       ----------------------------------------- ----> 0x5_8400_0000 ---
-       |       .. Unused .. (7M)               |                       |
-       ----------------------------------------- ----> 0x5_8390_0000   |
-       | FIT Image (linux + DTB + RFS) (40M)   |                       |
-       ----------------------------------------- ----> 0x5_8110_0000   |
-       |       PHY firmware (2M)               |                       |
-       ----------------------------------------- ----> 0x5_80F0_0000   | 64K
-       |       Debug Server FW (2M)            |                       | Bank
-       ----------------------------------------- ----> 0x5_80D0_0000   |
-       |       AIOP FW (4M)                    |                       |
-       ----------------------------------------- ----> 0x5_8090_0000 (vbank0)
-       |       MC DPC Blob (1M)                |                       |
-       ----------------------------------------- ----> 0x5_8080_0000   |
-       |       MC DPL Blob (1M)                |                       |
-       ----------------------------------------- ----> 0x5_8070_0000   |
-       |       MC FW (4M)                      |                       |
-       ----------------------------------------- ----> 0x5_8030_0000   |
-       |       BootLoader Environment (1M)     |                       |
-       ----------------------------------------- ----> 0x5_8020_0000   |
-       |       BootLoader (1M)                 |                       |
-       ----------------------------------------- ----> 0x5_8010_0000   |
-       |       RCW and PBI (1M)                |                       |
-       ----------------------------------------- ----> 0x5_8000_0000 ---
-
-       128-MB NOR flash layout for QDS and RDB boards
-
-Environment Variables
-=====================
-mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
-               the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
-
-mcmemsize:     MC DRAM block size. If this variable is not defined, the value
-               CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
-
-Booting from NAND
--------------------
-Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
-The difference between NAND boot RCW image and NOR boot image is the PBI
-command sequence. Below is one example for PBI commands for QDS which uses
-NAND device with 2KB/page, block size 128KB.
-
-1) CCSR 4-byte write to 0x00e00404, data=0x00000000
-2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
-The above two commands set bootloc register to 0x00000000_1800a000 where
-the u-boot code will be running in OCRAM.
-
-3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
-BLOCK_SIZE=0x00014000
-This command copies u-boot image from NAND device into OCRAM. The values need
-to adjust accordingly.
-
-SRC            should match the cfg_rcw_src, the reset config pins. It depends
-               on the NAND device. See reference manual for cfg_rcw_src.
-SRC_ADDR       is the offset of u-boot-with-spl.bin image in NAND device. In
-               the example above, 128KB. For easy maintenance, we put it at
-               the beginning of next block from RCW.
-DEST_ADDR      is fixed at 0x1800a000, matching bootloc set above.
-BLOCK_SIZE     is the size to be copied by PBI.
-
-RCW image should be written to the beginning of NAND device. Example of using
-u-boot command
-
-nand write <rcw image in memory> 0 <size of rcw image>
-
-To form the NAND image, build u-boot with NAND config, for example,
-ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
-The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
-
-nand write <u-boot image in memory> 200000 <size of u-boot image>
-
-With these two images in NAND device, the board can boot from NAND.
-
-Another example for RDB boards,
-
-1) CCSR 4-byte write to 0x00e00404, data=0x00000000
-2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
-3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
-BLOCK_SIZE=0x00014000
-
-nand write <rcw image in memory> 0 <size of rcw image>
-nand write <u-boot image in memory> 80000 <size of u-boot image>
-
-Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
-to match board NAND device with 4KB/page, block size 512KB.
-
-MMU Translation Tables
-======================
-
-(1) Early MMU Tables:
-
-     Level 0                   Level 1                   Level 2
-------------------        ------------------        ------------------
-| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
-------------------        ------------------        ------------------
-| 0x80_0000_0000 | --|    | 0x00_4000_0000 |        | 0x00_0020_0000 |
-------------------   |    ------------------        ------------------
-|    invalid     |   |    | 0x00_8000_0000 |        | 0x00_0040_0000 |
-------------------   |    ------------------        ------------------
-                     |    | 0x00_c000_0000 |        | 0x00_0060_0000 |
-                     |    ------------------        ------------------
-                     |    | 0x01_0000_0000 |        | 0x00_0080_0000 |
-                     |    ------------------        ------------------
-                     |            ...                      ...
-                     |    ------------------
-                     |    | 0x05_8000_0000 |  --|
-                     |    ------------------    |
-                     |    | 0x05_c000_0000 |    |
-                     |    ------------------    |
-                     |            ...           |
-                     |    ------------------    |   ------------------
-                     |--> | 0x80_0000_0000 |    |-> | 0x00_3000_0000 |
-                          ------------------        ------------------
-                          | 0x80_4000_0000 |        | 0x00_3020_0000 |
-                          ------------------        ------------------
-                          | 0x80_8000_0000 |        | 0x00_3040_0000 |
-                          ------------------        ------------------
-                          | 0x80_c000_0000 |        | 0x00_3060_0000 |
-                          ------------------        ------------------
-                          | 0x81_0000_0000 |        | 0x00_3080_0000 |
-                          ------------------        ------------------
-                                ...                       ...
-
-(2) Final MMU Tables:
-
-     Level 0                   Level 1                   Level 2
-------------------        ------------------        ------------------
-| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
-------------------        ------------------        ------------------
-| 0x80_0000_0000 | --|    | 0x00_4000_0000 |        | 0x00_0020_0000 |
-------------------   |    ------------------        ------------------
-|    invalid     |   |    | 0x00_8000_0000 |        | 0x00_0040_0000 |
-------------------   |    ------------------        ------------------
-                     |    | 0x00_c000_0000 |        | 0x00_0060_0000 |
-                     |    ------------------        ------------------
-                     |    | 0x01_0000_0000 |        | 0x00_0080_0000 |
-                     |    ------------------        ------------------
-                     |            ...                      ...
-                     |    ------------------
-                     |    | 0x08_0000_0000 | --|
-                     |    ------------------   |
-                     |    | 0x08_4000_0000 |   |
-                     |    ------------------   |
-                     |            ...          |
-                     |    ------------------   |    ------------------
-                     |--> | 0x80_0000_0000 |   |--> | 0x08_0000_0000 |
-                          ------------------        ------------------
-                          | 0x80_4000_0000 |        | 0x08_0020_0000 |
-                          ------------------        ------------------
-                          | 0x80_8000_0000 |        | 0x08_0040_0000 |
-                          ------------------        ------------------
-                          | 0x80_c000_0000 |        | 0x08_0060_0000 |
-                          ------------------        ------------------
-                          | 0x81_0000_0000 |        | 0x08_0080_0000 |
-                          ------------------        ------------------
-                                ...                       ...
-
-
-DPAA2 commands to manage Management Complex (MC)
-------------------------------------------------
-DPAA2 commands has been introduced to manage Management Complex
-(MC). These commands are used to start mc, aiop and apply DPL
-from u-boot command prompt.
-
-Please note Management complex Firmware(MC), DPL and DPC are no
-more deployed during u-boot boot-sequence.
-
-Commands:
-a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
-b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
-c) fsl_mc start aiop <FW_addr> - Start AIOP
-
-How to use commands :-
-1. Command sequence for u-boot ethernet:
-   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
-   b) DPMAC net-devices are now available for use
-
-   Example-
-       Assumption: MC firmware, DPL and DPC dtb is already programmed
-       on NOR flash.
-
-       => fsl_mc start mc 580300000 580800000
-       => setenv ethact DPMAC1@xgmii
-       => ping $serverip
-
-2. Command sequence for Linux boot:
-   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
-   b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
-   c) No DPMAC net-devices are available for use in u-boot
-   d) boot Linux
-
-   Example-
-       Assumption: MC firmware, DPL and DPC dtb is already programmed
-       on NOR flash.
-
-       => fsl_mc start mc 580300000 580800000
-       => setenv ethact DPMAC1@xgmii
-       => tftp a0000000 kernel.itb
-       => fsl_mc apply dpl 580700000
-       => bootm a0000000
-
-3. Command sequence for AIOP boot:
-   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
-   b) fsl_mc start aiop <FW_addr> - Start AIOP
-   c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
-   d) No DPMAC net-devices are availabe for use in u-boot
-  Please note actual AIOP start will happen during DPL parsing of
-  Management complex
-
-  Example-
-       Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
-       programmed on NOR flash.
-
-       => fsl_mc start mc 580300000 580800000
-       => fsl_mc start aiop 0x580900000
-       => setenv ethact DPMAC1@xgmii
-       => fsl_mc apply dpl 580700000
-
-Errata A009635
----------------
-If the core runs at higher than x3 speed of the platform, there is
-possiblity about sev instruction to getting missed by other cores.
-This is because of SoC Run Control block may not able to sample
-the EVENTI(Sev) signals.
-
-Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
-wake up A57 cores
-
-Errata workaround uses Env variable "a009635_interval_val". It uses decimal
-value.
-- Default value of env variable is platform clock (MHz)
-
-- User can modify default value by updating the env variable
-  setenv a009635_interval_val 600; saveenv;
-  It configure platform clock as 600 MHz
-
-- Env variable as 0 signifies no workaround
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
new file mode 100644 (file)
index 0000000..a6ef830
--- /dev/null
@@ -0,0 +1,10 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 2
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
+for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
new file mode 100644 (file)
index 0000000..f9323c1
--- /dev/null
@@ -0,0 +1,325 @@
+#
+# Copyright 2014-2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 3
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
+for example LS2080A.
+
+DDR Layout
+============
+Entire DDR region splits into two regions.
+ - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
+ - Region 2 is at 0x80_8000_0000 to the top of total memory,
+   for example 16GB, 0x83_ffff_ffff.
+
+All DDR memory is marked as cache-enabled.
+
+When MC and Debug server is enabled, they carve 512MB away from the high
+end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
+with MC and Debug server enabled. Linux only sees 15.5GB.
+
+The reserved 512MB layout looks like
+
+   +---------------+ <-- top/end of memory
+   |    256MB      |  debug server
+   +---------------+
+   |    256MB      |  MC
+   +---------------+
+   |     ...       |
+
+MC requires the memory to be aligned with 512MB, so even debug server is
+not enabled, 512MB is reserved, not 256MB.
+
+Flash Layout
+============
+
+(1) A typical layout of various images (including Linux and other firmware images)
+   is shown below considering a 32MB NOR flash device present on most
+   pre-silicon platforms (simulator and emulator):
+
+       -------------------------
+       |       FIT Image       |
+       | (linux + DTB + RFS)   |
+       ------------------------- ----> 0x0120_0000
+       |       Debug Server FW |
+       ------------------------- ----> 0x00C0_0000
+       |       AIOP FW         |
+       ------------------------- ----> 0x0070_0000
+       |       MC FW           |
+       ------------------------- ----> 0x006C_0000
+       |       MC DPL Blob     |
+       ------------------------- ----> 0x0020_0000
+       |       BootLoader + Env|
+       ------------------------- ----> 0x0000_1000
+       |       PBI             |
+       ------------------------- ----> 0x0000_0080
+       |       RCW             |
+       ------------------------- ----> 0x0000_0000
+
+       32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
+
+(2) A typical layout of various images (including Linux and other firmware images)
+    is shown below considering a 128MB NOR flash device present on QDS and RDB
+    boards:
+       ----------------------------------------- ----> 0x5_8800_0000 ---
+       |       .. Unused .. (7M)               |                       |
+       ----------------------------------------- ----> 0x5_8790_0000   |
+       | FIT Image (linux + DTB + RFS) (40M)   |                       |
+       ----------------------------------------- ----> 0x5_8510_0000   |
+       |       PHY firmware (2M)               |                       |
+       ----------------------------------------- ----> 0x5_84F0_0000   | 64K
+       |       Debug Server FW (2M)            |                       | Alt
+       ----------------------------------------- ----> 0x5_84D0_0000   | Bank
+       |       AIOP FW (4M)                    |                       |
+       ----------------------------------------- ----> 0x5_8490_0000 (vbank4)
+       |       MC DPC Blob (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8480_0000   |
+       |       MC DPL Blob (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8470_0000   |
+       |       MC FW (4M)                      |                       |
+       ----------------------------------------- ----> 0x5_8430_0000   |
+       |       BootLoader Environment (1M)     |                       |
+       ----------------------------------------- ----> 0x5_8420_0000   |
+       |       BootLoader (1M)                 |                       |
+       ----------------------------------------- ----> 0x5_8410_0000   |
+       |       RCW and PBI (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8400_0000 ---
+       |       .. Unused .. (7M)               |                       |
+       ----------------------------------------- ----> 0x5_8390_0000   |
+       | FIT Image (linux + DTB + RFS) (40M)   |                       |
+       ----------------------------------------- ----> 0x5_8110_0000   |
+       |       PHY firmware (2M)               |                       |
+       ----------------------------------------- ----> 0x5_80F0_0000   | 64K
+       |       Debug Server FW (2M)            |                       | Bank
+       ----------------------------------------- ----> 0x5_80D0_0000   |
+       |       AIOP FW (4M)                    |                       |
+       ----------------------------------------- ----> 0x5_8090_0000 (vbank0)
+       |       MC DPC Blob (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8080_0000   |
+       |       MC DPL Blob (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8070_0000   |
+       |       MC FW (4M)                      |                       |
+       ----------------------------------------- ----> 0x5_8030_0000   |
+       |       BootLoader Environment (1M)     |                       |
+       ----------------------------------------- ----> 0x5_8020_0000   |
+       |       BootLoader (1M)                 |                       |
+       ----------------------------------------- ----> 0x5_8010_0000   |
+       |       RCW and PBI (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8000_0000 ---
+
+       128-MB NOR flash layout for QDS and RDB boards
+
+Environment Variables
+=====================
+mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
+               the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+mcmemsize:     MC DRAM block size. If this variable is not defined, the value
+               CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting from NAND
+-------------------
+Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
+The difference between NAND boot RCW image and NOR boot image is the PBI
+command sequence. Below is one example for PBI commands for QDS which uses
+NAND device with 2KB/page, block size 128KB.
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+The above two commands set bootloc register to 0x00000000_1800a000 where
+the u-boot code will be running in OCRAM.
+
+3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+This command copies u-boot image from NAND device into OCRAM. The values need
+to adjust accordingly.
+
+SRC            should match the cfg_rcw_src, the reset config pins. It depends
+               on the NAND device. See reference manual for cfg_rcw_src.
+SRC_ADDR       is the offset of u-boot-with-spl.bin image in NAND device. In
+               the example above, 128KB. For easy maintenance, we put it at
+               the beginning of next block from RCW.
+DEST_ADDR      is fixed at 0x1800a000, matching bootloc set above.
+BLOCK_SIZE     is the size to be copied by PBI.
+
+RCW image should be written to the beginning of NAND device. Example of using
+u-boot command
+
+nand write <rcw image in memory> 0 <size of rcw image>
+
+To form the NAND image, build u-boot with NAND config, for example,
+ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
+
+nand write <u-boot image in memory> 200000 <size of u-boot image>
+
+With these two images in NAND device, the board can boot from NAND.
+
+Another example for RDB boards,
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+
+nand write <rcw image in memory> 0 <size of rcw image>
+nand write <u-boot image in memory> 80000 <size of u-boot image>
+
+Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
+to match board NAND device with 4KB/page, block size 512KB.
+
+MMU Translation Tables
+======================
+
+(1) Early MMU Tables:
+
+     Level 0                   Level 1                   Level 2
+------------------        ------------------        ------------------
+| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
+------------------        ------------------        ------------------
+| 0x80_0000_0000 | --|    | 0x00_4000_0000 |        | 0x00_0020_0000 |
+------------------   |    ------------------        ------------------
+|    invalid     |   |    | 0x00_8000_0000 |        | 0x00_0040_0000 |
+------------------   |    ------------------        ------------------
+                     |    | 0x00_c000_0000 |        | 0x00_0060_0000 |
+                     |    ------------------        ------------------
+                     |    | 0x01_0000_0000 |        | 0x00_0080_0000 |
+                     |    ------------------        ------------------
+                     |            ...                      ...
+                     |    ------------------
+                     |    | 0x05_8000_0000 |  --|
+                     |    ------------------    |
+                     |    | 0x05_c000_0000 |    |
+                     |    ------------------    |
+                     |            ...           |
+                     |    ------------------    |   ------------------
+                     |--> | 0x80_0000_0000 |    |-> | 0x00_3000_0000 |
+                          ------------------        ------------------
+                          | 0x80_4000_0000 |        | 0x00_3020_0000 |
+                          ------------------        ------------------
+                          | 0x80_8000_0000 |        | 0x00_3040_0000 |
+                          ------------------        ------------------
+                          | 0x80_c000_0000 |        | 0x00_3060_0000 |
+                          ------------------        ------------------
+                          | 0x81_0000_0000 |        | 0x00_3080_0000 |
+                          ------------------        ------------------
+                                ...                       ...
+
+(2) Final MMU Tables:
+
+     Level 0                   Level 1                   Level 2
+------------------        ------------------        ------------------
+| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
+------------------        ------------------        ------------------
+| 0x80_0000_0000 | --|    | 0x00_4000_0000 |        | 0x00_0020_0000 |
+------------------   |    ------------------        ------------------
+|    invalid     |   |    | 0x00_8000_0000 |        | 0x00_0040_0000 |
+------------------   |    ------------------        ------------------
+                     |    | 0x00_c000_0000 |        | 0x00_0060_0000 |
+                     |    ------------------        ------------------
+                     |    | 0x01_0000_0000 |        | 0x00_0080_0000 |
+                     |    ------------------        ------------------
+                     |            ...                      ...
+                     |    ------------------
+                     |    | 0x08_0000_0000 | --|
+                     |    ------------------   |
+                     |    | 0x08_4000_0000 |   |
+                     |    ------------------   |
+                     |            ...          |
+                     |    ------------------   |    ------------------
+                     |--> | 0x80_0000_0000 |   |--> | 0x08_0000_0000 |
+                          ------------------        ------------------
+                          | 0x80_4000_0000 |        | 0x08_0020_0000 |
+                          ------------------        ------------------
+                          | 0x80_8000_0000 |        | 0x08_0040_0000 |
+                          ------------------        ------------------
+                          | 0x80_c000_0000 |        | 0x08_0060_0000 |
+                          ------------------        ------------------
+                          | 0x81_0000_0000 |        | 0x08_0080_0000 |
+                          ------------------        ------------------
+                                ...                       ...
+
+
+DPAA2 commands to manage Management Complex (MC)
+------------------------------------------------
+DPAA2 commands has been introduced to manage Management Complex
+(MC). These commands are used to start mc, aiop and apply DPL
+from u-boot command prompt.
+
+Please note Management complex Firmware(MC), DPL and DPC are no
+more deployed during u-boot boot-sequence.
+
+Commands:
+a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+c) fsl_mc start aiop <FW_addr> - Start AIOP
+
+How to use commands :-
+1. Command sequence for u-boot ethernet:
+   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+   b) DPMAC net-devices are now available for use
+
+   Example-
+       Assumption: MC firmware, DPL and DPC dtb is already programmed
+       on NOR flash.
+
+       => fsl_mc start mc 580300000 580800000
+       => setenv ethact DPMAC1@xgmii
+       => ping $serverip
+
+2. Command sequence for Linux boot:
+   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+   b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+   c) No DPMAC net-devices are available for use in u-boot
+   d) boot Linux
+
+   Example-
+       Assumption: MC firmware, DPL and DPC dtb is already programmed
+       on NOR flash.
+
+       => fsl_mc start mc 580300000 580800000
+       => setenv ethact DPMAC1@xgmii
+       => tftp a0000000 kernel.itb
+       => fsl_mc apply dpl 580700000
+       => bootm a0000000
+
+3. Command sequence for AIOP boot:
+   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+   b) fsl_mc start aiop <FW_addr> - Start AIOP
+   c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+   d) No DPMAC net-devices are availabe for use in u-boot
+  Please note actual AIOP start will happen during DPL parsing of
+  Management complex
+
+  Example-
+       Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
+       programmed on NOR flash.
+
+       => fsl_mc start mc 580300000 580800000
+       => fsl_mc start aiop 0x580900000
+       => setenv ethact DPMAC1@xgmii
+       => fsl_mc apply dpl 580700000
+
+Errata A009635
+---------------
+If the core runs at higher than x3 speed of the platform, there is
+possiblity about sev instruction to getting missed by other cores.
+This is because of SoC Run Control block may not able to sample
+the EVENTI(Sev) signals.
+
+Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
+wake up A57 cores
+
+Errata workaround uses Env variable "a009635_interval_val". It uses decimal
+value.
+- Default value of env variable is platform clock (MHz)
+
+- User can modify default value by updating the env variable
+  setenv a009635_interval_val 600; saveenv;
+  It configure platform clock as 600 MHz
+
+- Env variable as 0 signifies no workaround
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
new file mode 100644 (file)
index 0000000..8eee016
--- /dev/null
@@ -0,0 +1,129 @@
+SoC overview
+
+       1. LS1043A
+       2. LS2080A
+       3. LS1012A
+
+LS1043A
+---------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+     management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+   - Up to 1 x XFI supporting 10G interface
+   - Up to 1 x QSGMII
+   - Up to 4 x SGMII supporting 1000Mbps
+   - Up to 2 x SGMII supporting 2500Mbps
+   - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+   - Three PCIe 2.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+LS2080A
+--------
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2080A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+  the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+   - Packet parsing, classification, and distribution (WRIOP)
+   - Queue and Hardware buffer management for scheduling, packet sequencing, and
+     congestion management, buffer allocation and de-allocation (QBMan)
+   - Cryptography acceleration (SEC) at up to 10 Gbps
+   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+   - Decompression/compression acceleration (DCE) at up to 20 Gbps
+   - Accelerated I/O processing (AIOP) at up to 20 Gbps
+   - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+   - Up to eight 10 Gbps Ethernet MACs
+   - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 3.0) controllers
+   - Two high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Serial peripheral interface (SPI) controller
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+  capabilities
+
+LS1012A
+--------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+    16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+    Two Serdes PLLs supported for usage by any SerDes data lane
+    Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+     - One PCI Express Gen2 controller, supporting x1 operation
+     - One serial ATA (SATA Gen 3.0) controller
+     - One USB 3.0/2.0 controller with integrated PHY
+     - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+    - One quad serial peripheral interface (QuadSPI) controller
+    - One serial peripheral interface (SPI) controller
+    - Two enhanced secure digital host controllers
+    - Two I2C controllers
+    - One 16550 compliant DUART (two UART interfaces)
+    - Two general purpose IOs (GPIO)
+    - Two FlexTimers
+    - Five synchronous audio interfaces (SAI)
+    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+    - Single-source clocking solution enabling generation of core, platform,
+    DDR, SerDes, and USB clocks from a single external crystal and internal
+    crystaloscillator
+    - Thermal monitor unit (TMU) with +/- 3C accuracy
+    - Two WatchDog timers
+    - ARM generic timer
+ - QorIQ platform's trust architecture 2.1
index 453a93d94c43b4a319a8bddd72020c75a3530e7b..3a77b21d0ab89d98ed7faed1e0cd354107d46e86 100644 (file)
@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
        struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
        u32 ccr;
 #endif
-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+#if (defined(CONFIG_FSL_ESDHC) &&\
+       defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
+       defined(CONFIG_SYS_DPAA_FMAN)
+
        u32 rcw_tmp;
 #endif
        struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -56,12 +59,18 @@ void get_sys_info(struct sys_info *sys_info)
        sys_info->freq_ddrbus = sysclk;
 #endif
 
+#ifdef CONFIG_LS1012A
+       sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+                       FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+                       FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+#else
        sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
                        FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
                        FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
        sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
                        FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
                        FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+#endif
 
        for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
                ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
@@ -80,6 +89,11 @@ void get_sys_info(struct sys_info *sys_info)
                        freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
        }
 
+#ifdef CONFIG_LS1012A
+       sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+       sys_info->freq_ddrbus *= 2;
+#endif
+
 #define HWA_CGA_M1_CLK_SEL     0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT   29
 #ifdef CONFIG_SYS_DPAA_FMAN
index 04831ca5bbc7611601d153f5a2d242398752fcf5..5af6b73bc9e8dab0bb32edff6b9653ac49b8e1c0 100644 (file)
@@ -94,11 +94,13 @@ ENTRY(lowlevel_init)
        bl      ccn504_set_qos
 #endif
 
+#ifdef SMMU_BASE
        /* Set the SMMU page size in the sACR register */
        ldr     x1, =SMMU_BASE
        ldr     w0, [x1, #0x10]
        orr     w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
        str     w0, [x1, #0x10]
+#endif
 
        /* Initialize GIC Secure Bank Status */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
@@ -181,6 +183,7 @@ ENTRY(lowlevel_init)
        ret
 ENDPROC(lowlevel_init)
 
+#ifdef CONFIG_FSL_LSCH3
 hnf_pstate_poll:
        /* x0 has the desired status, return 0 for success, 1 for timeout
         * clobber x1, x2, x3, x4, x6, x7
@@ -258,6 +261,7 @@ ENTRY(__asm_flush_l3_cache)
        mov     lr, x29
        ret
 ENDPROC(__asm_flush_l3_cache)
+#endif
 
 #ifdef CONFIG_MP
        /* Keep literals not used by the secondary boot code outside it */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
new file mode 100644 (file)
index 0000000..ff0903c
--- /dev/null
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+       u32 protocol;
+       u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+       {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
+       {0x0008, {NONE, NONE, NONE, SATA1} },
+       {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
+       {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+       {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
+       {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+       {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
+       {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
+       {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+       {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+       serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+       struct serdes_config *ptr;
+
+       if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+               return 0;
+
+       ptr = serdes_cfg_tbl[serdes];
+       while (ptr->protocol) {
+               if (ptr->protocol == cfg)
+                       return ptr->lanes[lane];
+               ptr++;
+       }
+
+       return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+       int i;
+       struct serdes_config *ptr;
+
+       if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+               return 0;
+
+       ptr = serdes_cfg_tbl[serdes];
+       while (ptr->protocol) {
+               if (ptr->protocol == prtcl)
+                       break;
+               ptr++;
+       }
+
+       if (!ptr->protocol)
+               return 0;
+
+       for (i = 0; i < SRDS_MAX_LANES; i++) {
+               if (ptr->lanes[i] != NONE)
+                       return 1;
+       }
+
+       return 0;
+}
index 0fb5c7f0cc1770d7bddfdd8613a6847be4bead20..dd633f36905c77d318ffab53d83eb2dca65c3c5b 100644 (file)
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_SYS_FSL_DDR
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
+#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
@@ -224,7 +226,7 @@ int sata_init(void)
 }
 #endif
 
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 int sata_init(void)
 {
index e159475580bc963da27b0c25236f50771761201e..95676806fa4802fecd4eb394fea526a86114098e 100644 (file)
@@ -122,7 +122,10 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
        fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
        fsl-ls1043a-qds-lpuart.dtb \
-       fsl-ls1043a-rdb.dtb
+       fsl-ls1043a-rdb.dtb \
+       fsl-ls1012a-qds.dtb \
+       fsl-ls1012a-rdb.dtb \
+       fsl-ls1012a-frdm.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
new file mode 100644 (file)
index 0000000..983e599
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
new file mode 100644 (file)
index 0000000..25dcdd2
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+       model = "LS1012A FREEDOM Board";
+       aliases {
+               spi0 = &qspi;
+       };
+};
+
+&qspi {
+       bus-num = <0>;
+       status = "okay";
+
+       qflash0: s25fl128s@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+};
+
+&duart0 {
+       status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
new file mode 100644 (file)
index 0000000..76db36c
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-qds.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
new file mode 100644 (file)
index 0000000..dde7134
--- /dev/null
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+       model = "LS1012A QDS Board";
+       aliases {
+               spi0 = &qspi;
+               spi1 = &dspi0;
+       };
+};
+
+&dspi0 {
+       bus-num = <0>;
+       status = "okay";
+
+       dflash0: n25q128a {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               reg = <0>;
+               spi-max-frequency = <1000000>; /* input clock */
+       };
+
+       dflash1: sst25wf040b {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <3500000>;
+               reg = <1>;
+       };
+
+       dflash2: en25s64 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <3500000>;
+               reg = <2>;
+       };
+};
+
+&qspi {
+       bus-num = <0>;
+       status = "okay";
+
+       qflash0: s25fl128s@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+       pca9547@77 {
+               compatible = "philips,pca9547";
+               reg = <0x77>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               i2c@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0>;
+
+                       rtc@68 {
+                               compatible = "dallas,ds3232";
+                               reg = <0x68>;
+                               /* IRQ10_B */
+                               interrupts = <0 150 0x4>;
+                       };
+               };
+
+               i2c@2 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x2>;
+
+                       ina220@40 {
+                               compatible = "ti,ina220";
+                               reg = <0x40>;
+                               shunt-resistor = <1000>;
+                       };
+
+                       ina220@41 {
+                               compatible = "ti,ina220";
+                               reg = <0x41>;
+                               shunt-resistor = <1000>;
+                       };
+               };
+
+               i2c@3 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x3>;
+
+                       eeprom@56 {
+                               compatible = "at24,24c512";
+                               reg = <0x56>;
+                       };
+
+                       eeprom@57 {
+                               compatible = "at24,24c512";
+                               reg = <0x57>;
+                       };
+
+                       adt7461a@4c {
+                               compatible = "adt7461a";
+                               reg = <0x4c>;
+                       };
+               };
+       };
+};
+
+&duart0 {
+       status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
new file mode 100644 (file)
index 0000000..f683812
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-rdb.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
new file mode 100644 (file)
index 0000000..bf407ae
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+       model = "LS1012A RDB Board";
+       aliases {
+               spi0 = &qspi;
+       };
+};
+
+&qspi {
+       bus-num = <0>;
+       status = "okay";
+
+       qflash0: s25fl128s@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+};
+
+&duart0 {
+       status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
new file mode 100644 (file)
index 0000000..546a87a
--- /dev/null
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+       compatible = "fsl,ls1012a";
+       interrupt-parent = <&gic>;
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x0>;
+                       clocks = <&clockgen 1 0>;
+               };
+
+       };
+
+       sysclk: sysclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+               clock-output-names = "sysclk";
+       };
+
+       gic: interrupt-controller@1400000 {
+               compatible = "arm,gic-400";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+                     <0x0 0x1402000 0 0x2000>, /* GICC */
+                     <0x0 0x1404000 0 0x2000>, /* GICH */
+                     <0x0 0x1406000 0 0x2000>; /* GICV */
+               interrupts = <1 9 0xf08>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               clockgen: clocking@1ee1000 {
+                       compatible = "fsl,ls1012a-clockgen";
+                       reg = <0x0 0x1ee1000 0x0 0x1000>;
+                       #clock-cells = <2>;
+                       clocks = <&sysclk>;
+               };
+
+               dspi0: dspi@2100000 {
+                       compatible = "fsl,vf610-dspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2100000 0x0 0x10000>;
+                       interrupts = <0 64 0x4>;
+                       clock-names = "dspi";
+                       clocks = <&clockgen 4 0>;
+                       num-cs = <6>;
+                       big-endian;
+                       status = "disabled";
+               };
+
+
+               i2c0: i2c@2180000 {
+                       compatible = "fsl,vf610-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2180000 0x0 0x10000>;
+                       interrupts = <0 56 0x4>;
+                       clock-names = "i2c";
+                       clocks = <&clockgen 4 0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@2190000 {
+                       compatible = "fsl,vf610-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2190000 0x0 0x10000>;
+                       interrupts = <0 57 0x4>;
+                       clock-names = "i2c";
+                       clocks = <&clockgen 4 0>;
+                       status = "disabled";
+               };
+
+               duart0: serial@21c0500 {
+                       compatible = "fsl,ns16550", "ns16550a";
+                       reg = <0x00 0x21c0500 0x0 0x100>;
+                       interrupts = <0 54 0x4>;
+                       clocks = <&clockgen 4 0>;
+               };
+
+               duart1: serial@21c0600 {
+                       compatible = "fsl,ns16550", "ns16550a";
+                       reg = <0x00 0x21c0600 0x0 0x100>;
+                       interrupts = <0 54 0x4>;
+                       clocks = <&clockgen 4 0>;
+               };
+
+               qspi: quadspi@1550000 {
+                       compatible = "fsl,vf610-qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x1550000 0x0 0x10000>,
+                               <0x0 0x40000000 0x0 0x4000000>;
+                       reg-names = "QuadSPI", "QuadSPI-memory";
+                       num-cs = <2>;
+                       big-endian;
+                       status = "disabled";
+               };
+
+       };
+};
index fbdaa52c32943144139f68c7061cd80a7491ff6d..44fe0c00953964b8f59ebac78fb8495cc5a85666 100644 (file)
 #else
 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3   /* Enable Freescale ARM DDR3 driver */
 #endif
+
+#ifndef CONFIG_LS1012A
 #define CONFIG_SYS_FSL_DDR             /* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
+#endif
 
 /*
  * Reserve secure memory
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_MAX_CPUS                         1
+#define CONFIG_SYS_CACHELINE_SIZE              64
+#define CONFIG_NUM_DDR_CONTROLLERS             1
+#define CONFIG_SYS_CCSRBAR_DEFAULT             0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT              5
+#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
+
+#define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE              0x200000 /* 2 MiB */
+
+#define GICD_BASE              0x01401000
+#define GICC_BASE              0x01402000
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
+
+#define SRDS_MAX_LANES         4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT             "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SEC_BE
 #else
 #error SoC not defined
 #endif
index 702b9faabd9f23e11918008c929f80e821e3a884..1cebe2fbb010736ae0e35a944773a025e3638701 100644 (file)
@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(LS1043, LS1043, 4),
        CPU_TYPE_ENTRY(LS1023, LS1023, 2),
        CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+       CPU_TYPE_ENTRY(LS1012, LS1012, 1),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF
index f71c2c1773603da66181a74f09c1ea3dd8fa0f8b..487cba80803f64c9f520e7c15e08d65542c06abe 100644 (file)
@@ -55,7 +55,7 @@ enum srds {
        FSL_SRDS_1  = 0,
        FSL_SRDS_2  = 1,
 };
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 enum srds_prtcl {
        NONE = 0,
        PCIE1,
@@ -134,6 +134,7 @@ enum srds_prtcl {
        SGMII_2500_FM2_DTSEC6,
        SGMII_2500_FM2_DTSEC9,
        SGMII_2500_FM2_DTSEC10,
+       TX_CLK,
        SERDES_PRCTL_COUNT
 };
 
index 57b99d4084ef0c666540f1c6e59d5d2ca46c2c12..e98e055d9f1150e29ddd20b88718f8afa8150d3c 100644 (file)
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x5000000000ULL
 /* LUT registers */
+#ifdef CONFIG_LS1012A
+#define PCIE_LUT_BASE                          0xC0000
+#else
 #define PCIE_LUT_BASE                          0x10000
+#endif
 #define PCIE_LUT_LCTRL0                                0x7F8
 #define PCIE_LUT_DBG                           0x7FC
 
index a3ccdb03c7f67969f86c4366175fd724f0447db4..db76066c8078f1aef342b46399a5a8e97129bfca 100644 (file)
@@ -69,7 +69,12 @@ enum csu_cslx_ind {
        CSU_CSLX_IIC4 = 77,
        CSU_CSLX_WDT4,
        CSU_CSLX_WDT3,
+       CSU_CSLX_ESDHC2 = 80,
        CSU_CSLX_WDT5 = 81,
+       CSU_CSLX_SAI2,
+       CSU_CSLX_SAI1,
+       CSU_CSLX_SAI4,
+       CSU_CSLX_SAI3,
        CSU_CSLX_FTM2 = 86,
        CSU_CSLX_FTM1,
        CSU_CSLX_FTM4,
@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
         {CSU_CSLX_IIC4, CSU_ALL_RW},
         {CSU_CSLX_WDT4, CSU_ALL_RW},
         {CSU_CSLX_WDT3, CSU_ALL_RW},
+        {CSU_CSLX_ESDHC2, CSU_ALL_RW},
         {CSU_CSLX_WDT5, CSU_ALL_RW},
+        {CSU_CSLX_SAI2, CSU_ALL_RW},
+        {CSU_CSLX_SAI1, CSU_ALL_RW},
+        {CSU_CSLX_SAI4, CSU_ALL_RW},
+        {CSU_CSLX_SAI3, CSU_ALL_RW},
         {CSU_CSLX_FTM2, CSU_ALL_RW},
         {CSU_CSLX_FTM1, CSU_ALL_RW},
         {CSU_CSLX_FTM4, CSU_ALL_RW},
index 831d81764ec5d34e7c2b860fce999b901e4df7a6..02ecc6257e16993385821cc6be545a565c096861 100644 (file)
@@ -41,6 +41,7 @@ struct cpu_type {
        { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #define SVR_WO_E               0xFFFFFE
+#define SVR_LS1012             0x870400
 #define SVR_LS1043             0x879200
 #define SVR_LS1023             0x879208
 #define SVR_LS2045             0x870120
index 3d5404ee100a1b9d8c8748fecacbc3f22a3b7862..0abaffb3349378ac3a93d8fe43e06008fb5e5a53 100644 (file)
@@ -12,9 +12,12 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
 {
        void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
        int i;
+       u32 icid;
 
-       for (i = 0; i < num; i++)
-               out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id);
+       for (i = 0; i < num; i++) {
+               icid = (id[i].stream_id & 0xff) << 24;
+               out_be32((u32 *)(scfg + id[i].offset), icid);
+       }
 }
 
 void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
index 113295f64a04b2a0d45daa80dfa061ab470b77af..0db0ed667002f33d6f532faf1840ad3ab4a6abac 100644 (file)
 #include <i2c.h>
 #include "qixis.h"
 
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
@@ -27,6 +34,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
 }
 #endif
 
+#ifdef QIXIS_BASE
 u8 qixis_read(unsigned int reg)
 {
        void *p = (void *)QIXIS_BASE;
@@ -40,6 +48,7 @@ void qixis_write(unsigned int reg, u8 value)
 
        out_8(p + reg, value);
 }
+#endif
 
 u16 qixis_read_minor(void)
 {
@@ -142,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
 {
        u8 reg;
 
-       reg = QIXIS_READ(brdcfg[0]);
+       reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
        reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
-       QIXIS_WRITE(brdcfg[0], reg);
+       QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
 }
 
 static void __maybe_unused set_rcw_src(int rcw_src)
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
new file mode 100644 (file)
index 0000000..a34521c
--- /dev/null
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+       default "ls1012afrdm"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_SOC
+       default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+       default "ls1012afrdm"
+
+endif
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
new file mode 100644 (file)
index 0000000..842f86f
--- /dev/null
@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M:     Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:     Maintained
+F:     board/freescale/ls1012afrdm/
+F:     include/configs/ls1012afrdm.h
+F:     configs/ls1012afrdm_qspi_defconfig
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
new file mode 100644 (file)
index 0000000..dbfa2ce
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
new file mode 100644 (file)
index 0000000..181c461
--- /dev/null
@@ -0,0 +1,58 @@
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+     - 2 SGMII 1G PHYs
+ - DDR Controller
+     - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+       operating at 1.35 V
+ - QSPI
+     - Onboard 512 Mbit QSPI flash memory running at speed up
+      to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+     - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+       Micro-AB connector.
+     - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+       as a Micro-AB device.
+ - I2C controller
+     - One I2C bus with connectivity to Arduino headers
+ - UART
+     - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+     - ARM Cortex® 10-pin JTAG connector for LS1012A
+     - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+     - One SAI port, SAI 2 with full duplex support
+ - Clocks
+     - 25 MHz crystal for LS1012A
+     - 8 MHz Crystal for K20
+     - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+     - 5 V input supply from USB
+     - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+       other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images         | Size  |QSPI Flash Address
+------------------------------------------
+RCW + PBI      | 1MB   | 0x4000_0000
+U-boot                 | 1MB   | 0x4010_0000
+U-boot Env     | 1MB   | 0x4020_0000
+PPA FIT image  | 2MB   | 0x4050_0000
+Linux ITB      | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
new file mode 100644 (file)
index 0000000..a94a458
--- /dev/null
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_csu.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+       int timeout = 1000;
+
+       out_be32(ptr, value);
+
+       while (in_be32(ptr) & bits) {
+               udelay(100);
+               timeout--;
+       }
+       if (timeout <= 0)
+               puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+       puts("Board: LS1012AFRDM ");
+
+       return 0;
+}
+
+void mmdc_init(void)
+{
+       struct mmdc_p_regs *mmdc =
+               (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+       out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+       /* configure timing parms */
+       out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+       out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+       out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+       out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+       /* other parms  */
+       out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+       out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+       out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+       out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+       /* out of reset delays */
+       out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+       /* physical parms */
+       out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+       out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+       out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+       /* dram init sequence: update MRs */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+                               CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+       set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+                               CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+                               FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+                               CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+       set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+       mdelay(1);
+
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+       mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+       out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+       set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+                               AUTO_RD_DQS_GATING_CALIBRATION_EN,
+                               AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+       set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+                               AUTO_RD_CALIBRATION_EN,
+                               AUTO_RD_CALIBRATION_EN);
+
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+       out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+       out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+       set_wait_for_bits_clear(&mmdc->mdref,
+                               CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+                               START_REFRESH);
+
+       /* disable CON_REQ */
+       out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+       mmdc_init();
+
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+       fsl_lsch2_early_init_f();
+
+       return 0;
+}
+
+int board_init(void)
+{
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       /*
+        * Set CCI-400 control override register to enable barrier
+        * transaction
+        */
+       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+       gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+       enable_layerscape_ns_access();
+#endif
+
+       return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+       arch_fixup_fdt(blob);
+
+       ft_cpu_setup(blob, bd);
+
+       return 0;
+}
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
new file mode 100644 (file)
index 0000000..1257ec8
--- /dev/null
@@ -0,0 +1,15 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+       default "ls1012aqds"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_SOC
+       default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+       default "ls1012aqds"
+
+endif
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
new file mode 100644 (file)
index 0000000..27c4aff
--- /dev/null
@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M:     Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:     Maintained
+F:     board/freescale/ls1012aqds/
+F:     include/configs/ls1012aqds.h
+F:     configs/ls1012aqds_qspi_defconfig
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
new file mode 100644 (file)
index 0000000..0b813f9
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012aqds.o
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
new file mode 100644 (file)
index 0000000..dee4b30
--- /dev/null
@@ -0,0 +1,59 @@
+Overview
+--------
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
+SoC overview.
+
+LS1012AQDS board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ - QSPI Controller
+     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+       emulator
+ - USB 3.0
+    - One USB 3.0 controller with integrated PHY
+    - One high-speed USB 3.0 port
+ - USB 2.0
+    - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+    - One SAI port with audio codec SGTL5000:
+       â€¢ Provides MIC bias
+       â€¢ Provides headphone and line output
+    - One SAI port terminated at 2x6 header
+    - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images         | Size  |QSPI Flash Address
+------------------------------------------
+RCW + PBI      | 1MB   | 0x4000_0000
+U-boot                 | 1MB   | 0x4010_0000
+U-boot Env     | 1MB   | 0x4020_0000
+PPA FIT image  | 2MB   | 0x4050_0000
+Linux ITB      | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
new file mode 100644 (file)
index 0000000..71eea82
--- /dev/null
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+       int timeout = 1000;
+
+       out_be32(ptr, value);
+
+       while (in_be32(ptr) & bits) {
+               udelay(100);
+               timeout--;
+       }
+       if (timeout <= 0)
+               puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+       char buf[64];
+       u8 sw;
+
+       sw = QIXIS_READ(arch);
+       printf("Board Arch: V%d, ", sw >> 4);
+       printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+       sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+       if (sw & QIXIS_LBMAP_ALTBANK)
+               printf("flash: 2\n");
+       else
+               printf("flash: 1\n");
+
+       printf("FPGA: v%d (%s), build %d",
+              (int)QIXIS_READ(scver), qixis_read_tag(buf),
+              (int)qixis_read_minor());
+
+       /* the timestamp string contains "\n" at the end */
+       printf(" on %s", qixis_read_time(buf));
+       return 0;
+}
+
+void mmdc_init(void)
+{
+       struct mmdc_p_regs *mmdc =
+               (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+       out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+       /* configure timing parms */
+       out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+       out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+       out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+       out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+       /* other parms  */
+       out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+       out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+       out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+       out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+       /* out of reset delays */
+       out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+       /* physical parms */
+       out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+       out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+       out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+       /* dram init sequence: update MRs */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+                               CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+       set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+                               CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+                               FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+                               CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+       set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+       mdelay(1);
+
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+       mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+       out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+       set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+                               AUTO_RD_DQS_GATING_CALIBRATION_EN,
+                               AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+       set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+                               AUTO_RD_CALIBRATION_EN,
+                               AUTO_RD_CALIBRATION_EN);
+
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+       out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+       out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+       set_wait_for_bits_clear(&mmdc->mdref,
+                               CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+                               START_REFRESH);
+
+       /* disable CON_REQ */
+       out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+       mmdc_init();
+
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+       fsl_lsch2_early_init_f();
+
+       return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+       u8 mux_sdhc_cd = 0x80;
+
+       i2c_set_bus_num(0);
+
+       i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+       return 0;
+}
+#endif
+
+int board_init(void)
+{
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+                                  CONFIG_SYS_CCI400_ADDR;
+
+       /* Set CCI-400 control override register to enable barrier
+        * transaction */
+       out_le32(&cci->ctrl_ord,
+                CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+       enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+       gd->env_addr = (ulong)&default_environment[0];
+#endif
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+       arch_fixup_fdt(blob);
+
+       ft_cpu_setup(blob, bd);
+
+       return 0;
+}
+#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
new file mode 100644 (file)
index 0000000..584f604
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK            0xe0
+#define BRDCFG4_EMISEL_SHIFT           5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66                        0x0
+#define QIXIS_SYSCLK_83                        0x1
+#define QIXIS_SYSCLK_100               0x2
+#define QIXIS_SYSCLK_125               0x3
+#define QIXIS_SYSCLK_133               0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66                        0x0
+#define QIXIS_DDRCLK_100               0x1
+#define QIXIS_DDRCLK_125               0x2
+#define QIXIS_DDRCLK_133               0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100               0x0
+#define QIXIS_SDCLK1_125               0x1
+#define QIXIS_SDCLK1_165               0x2
+#define QIXIS_SDCLK1_100_SP            0x3
+
+#endif
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
new file mode 100644 (file)
index 0000000..3f67c28
--- /dev/null
@@ -0,0 +1,15 @@
+if TARGET_LS1012ARDB
+
+config SYS_BOARD
+       default "ls1012ardb"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_SOC
+       default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+       default "ls1012ardb"
+
+endif
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
new file mode 100644 (file)
index 0000000..79a2a7d
--- /dev/null
@@ -0,0 +1,6 @@
+LS1012ARDB BOARD
+M:     Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:     Maintained
+F:     board/freescale/ls1012ardb/
+F:     include/configs/ls1012ardb.h
+F:     configs/ls1012ardb_qspi_defconfig
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
new file mode 100644 (file)
index 0000000..05fa9d9
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012ardb.o
diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
new file mode 100644 (file)
index 0000000..453b432
--- /dev/null
@@ -0,0 +1,54 @@
+Overview
+--------
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+LS1012ARDB board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+    - QSPI NOR flash memory (2 virtual banks)
+    - the QSPI emulator.s
+ - USB 3.0
+    - one high-speed USB 2.0/3.0 port.
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: Three dual 1:4 mux/demux devices,
+    74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
+    SDIO WiFi, SPI, and Ardiuno shield
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - The LS1012A processor consists of two UART controllers,
+   out of which only UART1 is used on RDB.
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images         | Size  |QSPI Flash Address
+------------------------------------------
+RCW + PBI      | 1MB   | 0x4000_0000
+U-boot                 | 1MB   | 0x4010_0000
+U-boot Env     | 1MB   | 0x4020_0000
+PPA FIT image  | 2MB   | 0x4050_0000
+Linux ITB      | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
new file mode 100644 (file)
index 0000000..f69768d
--- /dev/null
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+       int timeout = 1000;
+
+       out_be32(ptr, value);
+
+       while (in_be32(ptr) & bits) {
+               udelay(100);
+               timeout--;
+       }
+       if (timeout <= 0)
+               puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+       u8 in1;
+
+       puts("Board: LS1012ARDB ");
+
+       /* Initialize i2c early for Serial flash bank information */
+       i2c_set_bus_num(0);
+
+       if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
+               printf("Error reading i2c boot information!\n");
+               return 0; /* Don't want to hang() on this error */
+       }
+
+       puts("Version");
+       if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
+               puts(": RevA");
+       else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
+               puts(": RevB");
+       else
+               puts(": unknown");
+
+       printf(", boot from QSPI");
+       if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
+               puts(": emu\n");
+       else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
+               puts(": bank1\n");
+       else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
+               puts(": bank2\n");
+       else
+               puts("unknown\n");
+
+       return 0;
+}
+
+void mmdc_init(void)
+{
+       struct mmdc_p_regs *mmdc =
+               (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+       out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+       /* configure timing parms */
+       out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+       out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+       out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+       out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+       /* other parms  */
+       out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+       out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+       out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+       out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+       /* out of reset delays */
+       out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+       /* physical parms */
+       out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+       out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+       out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+       /* dram init sequence: update MRs */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+                               CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+       set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+                               CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+                               FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+                               CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+       set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+       mdelay(1);
+
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+       mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+       out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+       set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+                               AUTO_RD_DQS_GATING_CALIBRATION_EN,
+                               AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+       set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+                               AUTO_RD_CALIBRATION_EN,
+                               AUTO_RD_CALIBRATION_EN);
+
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+       out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+       out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+       set_wait_for_bits_clear(&mmdc->mdref,
+                               CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+                               START_REFRESH);
+
+       /* disable CON_REQ */
+       out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+       mmdc_init();
+
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+       fsl_lsch2_early_init_f();
+
+       return 0;
+}
+
+int board_init(void)
+{
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       /*
+        * Set CCI-400 control override register to enable barrier
+        * transaction
+        */
+       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+       gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+       enable_layerscape_ns_access();
+#endif
+
+       return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+       arch_fixup_fdt(blob);
+
+       ft_cpu_setup(blob, bd);
+
+       return 0;
+}
index f819c99dbaaaba313ab3bd21540d33f8219c4b4b..b39b561dc1ac22218e188fcd8678475141d8e386 100644 (file)
@@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = {
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
         */
 #ifdef CONFIG_SYS_FSL_DDR4
-       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-       {2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-       {1,  1666, 0, 4,     8, 0x090A0B0B, 0x0C0D0E0C,},
-       {1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
-       {1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+       {2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+       {2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+       {1,  1666, 0, 8,     8, 0x090A0B0B, 0x0C0D0E0C,},
+       {1,  1900, 0, 8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+       {1,  2200, 0, 8,    10, 0x0B0C0D0C, 0x0E0F110E,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-       {1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-       {1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-       {1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-       {1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-       {2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-       {2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-       {2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-       {2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
-       {2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+       {1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+       {1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+       {1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+       {1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+       {2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+       {2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+       {2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+       {2,  1666, 4, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+       {2,  1666, 0, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 #else
 #error DDR type not defined
 #endif
index a6fd7a35f5455ce43d4458381a76c2db93c8dcf8..913537d45190e1d54cf2c39eb70b00a67174da3c 100644 (file)
@@ -8,41 +8,8 @@ debugging environment.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043AQDS board Overview
  -----------------------
index d3f40822b7c5a0adce8f7c7d7eac01bd012bbbe9..ad709ba216b9565fd8c7ded1b30cfd84676f9514 100644 (file)
@@ -34,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = {
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
         */
 #ifdef CONFIG_SYS_FSL_DDR4
-       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-       {2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-       {1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E0A,},
-       {1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
-       {1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+       {2,  1666, 0,  8,     7, 0x0808090B, 0x0C0D0E0A,},
+       {2,  1900, 0,  8,     6, 0x08080A0C, 0x0D0E0F0A,},
+       {1,  1666, 0,  8,     6, 0x0708090B, 0x0C0D0E0A,},
+       {1,  1900, 0,  8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+       {1,  2200, 0,  8,    10, 0x0B0C0D0C, 0x0E0F110E,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-       {1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-       {1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-       {1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-       {1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-       {2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-       {2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-       {2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-       {2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
-       {2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+       {1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+       {1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+       {1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+       {1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+       {2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+       {2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+       {2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+       {2,  1666, 4,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+       {2,  1666, 0,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 #else
 #error DDR type not defined
 #endif
index ca393e862d7d40e7146fbe1d95d92eec02796d51..7e47ef0d82bcbb54eb2ac82f09d1f4b97ae32d4b 100644 (file)
@@ -238,8 +238,8 @@ int board_early_init_f(void)
        out_be32(&scfg->rcwpmuxcr0, 0x3333);
        out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
        usb_pwrfault =
-               (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
-               (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+               (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+               (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
                (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
        out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 #endif
index 0556e73b3aeee5e947aca007e04e047e067302d6..709ddbbef31a4cb42f68a72a870f599ce54d34ea 100644 (file)
@@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043ARDB board Overview
  -----------------------
index 8ca166b3ac93479b27d90e37dccd4d4b86fe8619..a77ddf3d240ed342e767280eeccc5e73fcf9db9b 100644 (file)
@@ -34,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = {
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
         */
 #ifdef CONFIG_SYS_FSL_DDR4
-       {1,  1666, 0, 6,     7, 0x07090800, 0x00000000,},
-       {1,  1900, 0, 6,     7, 0x07090800, 0x00000000,},
-       {1,  2200, 0, 6,     7, 0x07090800, 0x00000000,},
+       {1,  1666, 0, 12,     7, 0x07090800, 0x00000000,},
+       {1,  1900, 0, 12,     7, 0x07090800, 0x00000000,},
+       {1,  2200, 0, 12,     7, 0x07090800, 0x00000000,},
 #endif
        {}
 };
index 6ddad92f2cf121d26d9989e1b99667ed4694ad5b..5c98866712ae4d10b350c092a42c99b4464bb1f2 100644 (file)
@@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with
 a complete debugging environment.
 
 LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
-  the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
-   - Packet parsing, classification, and distribution (WRIOP)
-   - Queue and Hardware buffer management for scheduling, packet sequencing, and
-     congestion management, buffer allocation and de-allocation (QBMan)
-   - Cryptography acceleration (SEC) at up to 10 Gbps
-   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
-   - Decompression/compression acceleration (DCE) at up to 20 Gbps
-   - Accelerated I/O processing (AIOP) at up to 20 Gbps
-   - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
-   - Up to eight 10 Gbps Ethernet MACs
-   - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 3.0) controllers
-   - Two high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Serial peripheral interface (SPI) controller
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
-  capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
 
  LS2080AQDS board Overview
  -----------------------
index b76ea61ba0b5e7672a707cc74f35afd9204bfb2e..eba62c33b209968804d0e46838ca193f8503e218 100644 (file)
@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-       {2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-       {2,  2300, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+       {2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+       {2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+       {2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  2300, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
        {}
 };
 
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-       {2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-       {2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
-       {2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+       {2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+       {2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+       {2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+       {2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
        {}
 };
 
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-       {2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-       {2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+       {2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+       {2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+       {2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
        {}
 };
 
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-       {2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
-       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-       {2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+       {2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+       {2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
+       {2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
        {}
 };
 
index b3bd40afb77407d09c4a9f54d6b0428ad02ddbe3..897793d85b7db6dac3348e2e87245e6323010629 100644 (file)
@@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
        int err;
+#endif
        u64 base[CONFIG_NR_DRAM_BANKS];
        u64 size[CONFIG_NR_DRAM_BANKS];
 
index 6708ca9cc7d2923fddf450aa999370136e2f193b..b1613ba680081422feb7cf99987567f8653a8035 100644 (file)
@@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A
 Layerscape Architecture processor.
 
 LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
-  the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
-   - Packet parsing, classification, and distribution (WRIOP)
-   - Queue and Hardware buffer management for scheduling, packet sequencing, and
-     congestion management, buffer allocation and de-allocation (QBMan)
-   - Cryptography acceleration (SEC) at up to 10 Gbps
-   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
-   - Decompression/compression acceleration (DCE) at up to 20 Gbps
-   - Accelerated I/O processing (AIOP) at up to 20 Gbps
-   - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
-   - Up to eight 10 Gbps Ethernet MACs
-   - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 3.0) controllers
-   - Two high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Serial peripheral interface (SPI) controller
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
-  capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
index b3c6306b8f3c60ea979b5a716f027f1000c08b5f..8d5a49061ce95ef4d421635b0d479141cef977d9 100644 (file)
@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-       {2,  1666, 0, 5,     9, 0x090A0B0E, 0x0F11110C,},
-       {2,  1900, 0, 6,   0xA, 0x0B0C0E11, 0x1214140F,},
-       {2,  2300, 0, 6,   0xB, 0x0C0D0F12, 0x14161610,},
+       {2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+       {2,  1666, 0, 10,    9, 0x090A0B0E, 0x0F11110C,},
+       {2,  1900, 0, 12,  0xA, 0x0B0C0E11, 0x1214140F,},
+       {2,  2300, 0, 12,  0xB, 0x0C0D0F12, 0x14161610,},
        {}
 };
 
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-       {2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-       {2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
-       {2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+       {2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+       {2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+       {2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+       {2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
        {}
 };
 
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-       {2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-       {2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+       {2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+       {2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+       {2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
        {}
 };
 
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-       {2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
-       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-       {2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+       {2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+       {2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
+       {2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
        {}
 };
 
index fb39af64452f6a2edd743da2839edc009e10e4a6..52e5e3f516d341da0bc7b70e1093aa3d2f2044b0 100644 (file)
@@ -156,7 +156,9 @@ int board_init(void)
 {
        char *env_hwconfig;
        u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+#ifdef CONFIG_FSL_MC_ENET
        u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
        u32 val;
 
        init_final_memctl_regs();
@@ -178,8 +180,10 @@ int board_init(void)
 
        QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+#ifdef CONFIG_FSL_MC_ENET
        /* invert AQR405 IRQ pins polarity */
        out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+#endif
 
        return 0;
 }
@@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
        int err;
+#endif
        u64 base[CONFIG_NR_DRAM_BANKS];
        u64 size[CONFIG_NR_DRAM_BANKS];
 
index 2d4d10f351a1082a8eabc47ce19fc132e6314829..912d6a950f8c4653e222797c599f2e8b91a54020 100644 (file)
@@ -35,18 +35,18 @@ static const struct board_specific_parameters udimm0[] = {
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
         */
 #if defined(CONFIG_SYS_FSL_DDR4)
-       {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-       {2,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-       {1,  1666,  0,  4,  6,  0x0708090B,  0x0C0D0E09,},
-       {1,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-       {1,  2200,  0,  4,  7,  0x08090A0D,  0x0F0F100C,},
+       {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+       {2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+       {1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
+       {1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+       {1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-       {2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-       {2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-       {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-       {1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-       {1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-       {1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+       {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+       {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+       {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+       {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+       {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+       {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 #else
 #error DDR type not defined
 #endif
index adf9fd5f78b448cb010cb2a5493abe9b347570f4..60ab9ff8ade08a6d775656842098d9d0903ce0a4 100644 (file)
@@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
         */
-       {2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-       {2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-       {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-       {1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-       {1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-       {1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+       {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+       {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+       {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+       {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+       {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+       {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
        {}
 };
 
index a6e1673525f5d3cc50f1c1e2ab2e3f610c5c8434..1e087460cb9f27caf1c6437e73347c872d86ecfc 100644 (file)
@@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = {
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
         */
 #ifdef CONFIG_SYS_FSL_DDR4
-       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-       {2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-       {1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-       {1,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-       {1,  2200, 0, 4,     7, 0x08090A0D, 0x0F0F100C,},
+       {2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+       {2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+       {1,  1666, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+       {1,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+       {1,  2200, 0, 8,     7, 0x08090A0D, 0x0F0F100C,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-       {2,  833,  0, 4,     6, 0x06060607, 0x08080807,},
-       {2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
-       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-       {1,  833,  0, 4,     6, 0x06060607, 0x08080807,},
-       {1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
-       {1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+       {2,  833,  0, 8,     6, 0x06060607, 0x08080807,},
+       {2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
+       {2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+       {1,  833,  0, 8,     6, 0x06060607, 0x08080807,},
+       {1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
+       {1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
 #else
 #error DDR type not defined
 #endif
index b9c02f7fe0fd9b402d44b9604e6f4821568eb0a7..012991cf469f978a1cf7c384df7de330e5c52444 100644 (file)
@@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = {
         * ranks| mhz| GB  |adjst| start |   ctl2
         */
 #ifdef CONFIG_SYS_FSL_DDR4
-       {2,  1600, 4, 4,     6, 0x07090A0c, 0x0e0f100a},
+       {2,  1600, 4, 8,     6, 0x07090A0c, 0x0e0f100a},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-       {2,  833,  4, 4,     6, 0x06060607, 0x08080807},
-       {2,  833,  0, 4,     6, 0x06060607, 0x08080807},
-       {2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-       {2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-       {2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
-       {1,  833,  4, 4,     6, 0x06060607, 0x08080807},
-       {1,  833,  0, 4,     6, 0x06060607, 0x08080807},
-       {1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-       {1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-       {1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-       {1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+       {2,  833,  4, 8,     6, 0x06060607, 0x08080807},
+       {2,  833,  0, 8,     6, 0x06060607, 0x08080807},
+       {2,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+       {2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+       {2,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+       {2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
+       {1,  833,  4, 8,     6, 0x06060607, 0x08080807},
+       {1,  833,  0, 8,     6, 0x06060607, 0x08080807},
+       {1,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+       {1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+       {1,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+       {1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
 #else
 #error DDR type not defined
 #endif
index 9c26fdf3bd65450f14daa830b5d26a8eaed5c008..255ab2c543311dbe9b1550b4342364820c5c638d 100644 (file)
@@ -28,17 +28,17 @@ static const struct board_specific_parameters udimm0[] = {
         *   num|  hi| rank|  clk| wrlvl | wrlvl | wrlvl |
         * ranks| mhz| GB  |adjst| start | ctl2  | ctl3  |
         */
-       {2,  1200,  0,  5,  7,  0x0708090a,  0x0b0c0d09},
-       {2,  1400,  0,  5,  7,  0x08090a0c,  0x0d0e0f0a},
-       {2,  1700,  0,  5,  8,  0x090a0b0c,  0x0e10110c},
-       {2,  1900,  0,  5,  8,  0x090b0c0f,  0x1012130d},
-       {2,  2140,  0,  5,  8,  0x090b0c0f,  0x1012130d},
-       {1,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
-       {1,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
-       {1,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
-       {1,  1700,  0,  4,  8,  0x080a0a0c,  0x0c0d0e0a},
-       {1,  1900,  0,  5,  8,  0x090a0c0d,  0x0e0f110c},
-       {1,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
+       {2,  1200,  0, 10,  7,  0x0708090a,  0x0b0c0d09},
+       {2,  1400,  0, 10,  7,  0x08090a0c,  0x0d0e0f0a},
+       {2,  1700,  0, 10,  8,  0x090a0b0c,  0x0e10110c},
+       {2,  1900,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+       {2,  2140,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+       {1,  1200,  0, 10,  7,  0x0808090a,  0x0b0c0c0a},
+       {1,  1500,  0, 10,  6,  0x07070809,  0x0a0b0b09},
+       {1,  1600,  0, 10,  8,  0x090b0b0d,  0x0d0e0f0b},
+       {1,  1700,  0,  8,  8,  0x080a0a0c,  0x0c0d0e0a},
+       {1,  1900,  0, 10,  8,  0x090a0c0d,  0x0e0f110c},
+       {1,  2140,  0,  8,  8,  0x090a0b0d,  0x0e0f110b},
        {}
 };
 
@@ -49,15 +49,15 @@ static const struct board_specific_parameters rdimm0[] = {
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
         */
        /* TODO: need tuning these parameters if RDIMM is used */
-       {4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-       {4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
-       {4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-       {2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-       {2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-       {2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-       {1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-       {1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-       {1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+       {4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+       {4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+       {4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+       {2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+       {2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+       {2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+       {1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+       {1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+       {1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
        {}
 };
 
index 08cbb606d5e8055cb91d5f574f6ebf20380d736d..175cf56a0942344552933092a640c2daa740f3d9 100644 (file)
@@ -28,16 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
         */
-       {2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-       {2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-       {2,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
-       {2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-       {2,  1900, 0, 5,     7, 0x0808080c, 0x0b0c0c09},
-       {1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-       {1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-       {1,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
-       {1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-       {1,  1900, 0, 5,     7, 0x0808080c, 0x0b0c0c09},
+       {2,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+       {2,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+       {2,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+       {2,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+       {2,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
+       {1,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+       {1,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+       {1,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+       {1,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+       {1,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
        {}
 };
 
index 4d0e3c497db2a6cff4b5b6545e4509a33f3da185..0b0cc9af39a094b31278461d7ef916f601b8d165 100644 (file)
@@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
         */
-       {2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-       {2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-       {2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-       {2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
-       {2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-       {2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-       {1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-       {1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-       {1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-       {1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+       {2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+       {2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+       {2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+       {2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+       {2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+       {2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+       {1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+       {1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+       {1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+       {1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
        {}
 };
 
@@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
         */
-       {4,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-       {4,  1666, 0, 5,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
-       {4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-       {2,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-       {2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-       {2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-       {1,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-       {1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-       {1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+       {4,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+       {4,  1666, 0, 10,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
+       {4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+       {2,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+       {2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+       {2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+       {1,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+       {1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+       {1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
        {}
 };
 
index 7b854767e7a81814b08700c753678bed6005ec05..f01ebb22b573ba3a66ad85dbebe6dbaa9aff3a3a 100644 (file)
@@ -27,16 +27,16 @@ static const struct board_specific_parameters udimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a},
-       {2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09},
-       {2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b},
-       {2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a},
-       {2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c},
-       {2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c},
-       {1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a},
-       {1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a},
-       {1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a},
-       {1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b},
+       {2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a},
+       {2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09},
+       {2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b},
+       {2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a},
+       {2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+       {2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+       {1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a},
+       {1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a},
+       {1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a},
+       {1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b},
        {}
 };
 
@@ -46,15 +46,15 @@ static const struct board_specific_parameters rdimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
         */
-       {4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-       {4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
-       {4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-       {2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-       {2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-       {2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-       {1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-       {1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-       {1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+       {4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+       {4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+       {4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+       {2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+       {2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+       {2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+       {1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+       {1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+       {1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
        {}
 };
 
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
new file mode 100644 (file)
index 0000000..349758b
--- /dev/null
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AFRDM=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
new file mode 100644 (file)
index 0000000..2bc178c
--- /dev/null
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
new file mode 100644 (file)
index 0000000..456eebd
--- /dev/null
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
index 9073917914e9630a77d4df47870c248357b0f53d..1d5cec662ce1c94f4af5ca9282aa457e3ace1473 100644 (file)
@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
                | ((add_lat_mclk & 0xf) << 28)
                | ((cpo & 0x1f) << 23)
                | ((wr_lat & 0xf) << 19)
-               | ((wr_lat & 0x10) << 14)
+               | ((wr_lat & 0x10) << 18)
                | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
                | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
                | ((cke_pls & 0x7) << 6)
@@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
        /* Per FSL Application Note: AN2805 */
        ss_en = 1;
 #endif
-       clk_adjust = popts->clk_adjust;
+       if (fsl_ddr_get_version(0) >= 0x40701) {
+               /* clk_adjust in 5-bits on T-series and LS-series */
+               clk_adjust = (popts->clk_adjust & 0x1F) << 22;
+       } else {
+               /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
+               clk_adjust = (popts->clk_adjust & 0xF) << 23;
+       }
+
        ddr->ddr_sdram_clk_cntl = (0
                                   | ((ss_en & 0x1) << 31)
-                                  | ((clk_adjust & 0xF) << 23)
+                                  | clk_adjust
                                   );
        debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }
index 5039f5de0a9063b1aa25e252e2e4a33ea37f557e..d37e2474c91d0b8a2a02fb041865f5f52e14f525 100644 (file)
@@ -206,12 +206,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
        /* part 1 of 2 */
-       if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
-               ddr_out32(&ddr->ddr_sdram_rcw_2,
-                         regs->ddr_sdram_rcw_2 & ~0x0f000000);
+       if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+               if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+                       ddr_out32(&ddr->ddr_sdram_rcw_2,
+                                 regs->ddr_sdram_rcw_2 & ~0x0f000000);
+               }
+               ddr_out32(&ddr->err_disable, regs->err_disable |
+                         DDR_ERR_DISABLE_APED);
        }
-
-       ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
 #else
        ddr_out32(&ddr->err_disable, regs->err_disable);
 #endif
@@ -395,22 +397,24 @@ step2:
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
-               /* if it's RDIMM */
-               if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
-                       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-                               if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
-                                       continue;
-                               set_wait_for_bits_clear(&ddr->sdram_md_cntl,
-                                                       MD_CNTL_MD_EN |
-                                                       MD_CNTL_CS_SEL(i) |
-                                                       0x070000ed,
-                                                       MD_CNTL_MD_EN);
-                               udelay(1);
+               if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+                       /* if it's RDIMM */
+                       if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+                               for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+                                       if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+                                               continue;
+                                       set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+                                                               MD_CNTL_MD_EN |
+                                                               MD_CNTL_CS_SEL(i) |
+                                                               0x070000ed,
+                                                               MD_CNTL_MD_EN);
+                                       udelay(1);
+                               }
                        }
-               }
 
-               ddr_out32(&ddr->err_disable,
-                         regs->err_disable & ~DDR_ERR_DISABLE_APED);
+                       ddr_out32(&ddr->err_disable,
+                                 regs->err_disable & ~DDR_ERR_DISABLE_APED);
+               }
 #endif
        }
 #endif
index d0075ff1fd2b3fb96e8fee513ceb5b276d529cb3..793d12aabb0a4a06b97386e1b690b2d99c5720d9 100644 (file)
@@ -886,7 +886,8 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
        } else
                popts->ecc_mode = 1;
 #endif
-       popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
+       /* 1 = use memory controler to init data */
+       popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
 
        /*
         * Choose DQS config
index 3acf9e88202f6c253f9ada4ea08cce3041ff1c09..57ad9754f56a1af12f63576f190bf8a153ac88c3 100644 (file)
@@ -308,14 +308,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 static void check_and_invalidate_dcache_range
        (struct mmc_cmd *cmd,
         struct mmc_data *data) {
-#ifdef CONFIG_FSL_LAYERSCAPE
        unsigned start = 0;
-#else
-       unsigned start = (unsigned)data->dest ;
-#endif
+       unsigned end = 0;
        unsigned size = roundup(ARCH_DMA_MINALIGN,
                                data->blocks*data->blocksize);
-       unsigned end = start+size ;
 #ifdef CONFIG_FSL_LAYERSCAPE
        dma_addr_t addr;
 
@@ -324,7 +320,10 @@ static void check_and_invalidate_dcache_range
                printf("Error found for upper 32 bits\n");
        else
                start = lower_32_bits(addr);
+#else
+       start = (unsigned)data->dest;
 #endif
+       end = start + size;
        invalidate_dcache_range(start, end);
 }
 
index 4f37e33eb0687e753ac965f5cb0f145552baa94d..c577d9ed6c91d81b28648b2b5adec82b8ab73e47 100644 (file)
@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
        {"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256, RD_FULL,                   WR_QPP},
        {"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL,                   WR_QPP},
        {"S25FL256S_64K",  0x010219, 0x4d01,    64 * 1024,   512, RD_FULL,                   WR_QPP},
+       {"S25FS512S",      0x010220, 0x4D00,   128 * 1024,   512, RD_FULL,                   WR_QPP},
        {"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL,                   WR_QPP},
        {"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024, RD_FULL,                   WR_QPP},
        {"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL,                   WR_QPP},
index fa0e79966cf4253fde639c1f70556b57779d8277..64d4e0f947fd5764464a5aff216c3b9c23718892 100644 (file)
@@ -1072,7 +1072,8 @@ int spi_flash_scan(struct spi_flash *flash)
         * sector that is not overlaid by the parameter sectors.
         * The uniform sector erase command has no effect on parameter sectors.
         */
-       if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+       if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+           (ext_jedec & 0xff00) == 0x4d00) {
                int ret;
                u8 id[6];
 
@@ -1146,7 +1147,7 @@ int spi_flash_scan(struct spi_flash *flash)
         * have 256b pages.
         */
        if (ext_jedec == 0x4d00) {
-               if ((jedec == 0x0215) || (jedec == 0x216))
+               if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
                        flash->page_size = 256;
                else
                        flash->page_size = 512;
index 0ba960e248072de6932aa0917ef28afbec5c3526..2e6b986dbce169a997984c37601b7ebce5a731e6 100644 (file)
@@ -569,7 +569,7 @@ static void fdt_fixup_pcie(void *blob)
        unsigned char header_type;
        int index;
        u32 streamid;
-       pci_dev_t dev;
+       pci_dev_t dev, bdf;
        int bus;
        unsigned short id;
        struct pci_controller *hose;
@@ -611,12 +611,15 @@ static void fdt_fixup_pcie(void *blob)
                                        continue;
                                }
 
+                               /* the DT fixup must be relative to the hose first_busno */
+                               bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
+
                                /* map PCI b.d.f to streamID in LUT */
-                               ls_pcie_lut_set_mapping(pcie, index, dev >> 8,
+                               ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
                                                        streamid);
 
                                /* update msi-map in device tree */
-                               fdt_pcie_set_msi_map_entry(blob, pcie, dev >> 8,
+                               fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
                                                           streamid);
                        }
                }
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
new file mode 100644 (file)
index 0000000..ccd94ec
--- /dev/null
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define        CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TEXT_BASE           0x40100000
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ            100000000
+#define CONFIG_DDR_CLK_FREQ            125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F      1
+
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY              CONFIG_SYS_CLK_FREQ/4   /* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR                0x400d0000
+#define CONFIG_ENV_SPI_BUS             0
+#define CONFIG_ENV_SPI_CS              0
+#define CONFIG_ENV_SPI_MAX_HZ          1000000
+#define CONFIG_ENV_SPI_MODE            0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE                0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE            (1 << 24)
+#define FSL_QSPI_FLASH_NUM             2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                        0x40000          /* 256KB */
+#define CONFIG_ENV_OFFSET              0x200000        /* 2MB */
+#define CONFIG_ENV_SECT_SIZE           0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
+
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ                  1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE           128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "initrd_high=0xffffffff\0"              \
+       "verify=no\0"                           \
+       "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
+       "loadaddr=0x80100000\0"                 \
+       "kernel_addr=0x100000\0"                \
+       "ramdisk_addr=0x800000\0"               \
+       "ramdisk_size=0x2000000\0"              \
+       "fdt_high=0xffffffffffffffff\0"         \
+       "initrd_high=0xffffffffffffffff\0"      \
+       "kernel_start=0xa00000\0"               \
+       "kernel_load=0xa0000000\0"              \
+       "kernel_size=0x2800000\0"               \
+       "console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS                "console=ttyS0,115200 root=/dev/ram0 " \
+                               "earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND             "sf probe 0:0; sf read $kernel_load "\
+                                       "$kernel_start $kernel_size && "\
+                                       "bootm $kernel_load"
+#define CONFIG_BOOTDELAY               10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE              512     /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING         1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS             64      /* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
new file mode 100644 (file)
index 0000000..3e7c430
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   1
+#define CONFIG_NR_DRAM_BANKS           2
+#define CONFIG_SYS_SDRAM_SIZE          0x20000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1         0x04180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2         0x84180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END         0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END         0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
new file mode 100644 (file)
index 0000000..2d84095
--- /dev/null
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   1
+#define CONFIG_NR_DRAM_BANKS           2
+#define CONFIG_SYS_SDRAM_SIZE          0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1         0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2         0x85180000
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR       0x66
+#define QIXIS_LBMAP_BRDCFG_REG         0x04
+#define QIXIS_LBMAP_SWITCH             6
+#define QIXIS_LBMAP_MASK               0xf7
+#define QIXIS_LBMAP_SHIFT              0
+#define QIXIS_LBMAP_DFLTBANK           0x00
+#define QIXIS_LBMAP_ALTBANK            0x08
+#define QIXIS_RST_CTL_RESET            0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START  0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI           0x77
+#define I2C_MUX_PCA_ADDR_SEC           0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR               0x18
+#define I2C_MUX_CH_DEFAULT             0x8
+#define I2C_MUX_CH_CH7301              0xC
+#define I2C_MUX_CH5                    0xD
+#define I2C_MUX_CH7                    0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM    0
+#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+
+/* DSPI */
+#define CONFIG_FSL_DSPI1
+#define CONFIG_DEFAULT_SPI_BUS 1
+
+#define CONFIG_CMD_SPI
+#define MMAP_DSPI          DSPI1_BASE_ADDR
+
+#define CONFIG_SYS_DSPI_CTAR0   1
+
+#define CONFIG_SYS_DSPI_CTAR1  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+                               DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+                               DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+
+#define CONFIG_SYS_DSPI_CTAR2  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+                               DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
+                               DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
+
+#define CONFIG_SYS_DSPI_CTAR3  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+                               DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+                               DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_EON /* cs3 */
+
+#define CONFIG_SF_DEFAULT_SPEED      10000000
+#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
+#define CONFIG_SF_DEFAULT_BUS        1
+#define CONFIG_SF_DEFAULT_CS         0
+
+/*
+* USB
+*/
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define        CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA                                AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID            1
+#define CONFIG_SYS_SCSI_MAX_LUN                        1
+#define CONFIG_SYS_SCSI_MAX_DEVICE             (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+                                               CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI             /* Enable PCI/PCIE */
+#define CONFIG_PCIE1           /* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF  0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE      0x00001000      /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF  0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE      0x00001000      /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS         0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF    0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE                0x00010000      /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END         0x9fffffff
+
+#define CONFIG_MISC_INIT_R
+
+#endif /* __LS1012AQDS_H__ */
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
new file mode 100644 (file)
index 0000000..f63c66a
--- /dev/null
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   1
+#define CONFIG_NR_DRAM_BANKS           2
+#define CONFIG_SYS_SDRAM_SIZE          0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1         0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2         0x85180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END         0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * I2C IO expander
+ */
+
+#define I2C_MUX_IO1_ADDR       0x24
+#define __SW_BOOT_MASK         0xFC
+#define __SW_BOOT_EMU          0x10
+#define __SW_BOOT_BANK1                0x00
+#define __SW_BOOT_BANK2                0x01
+#define __SW_REV_MASK          0x07
+#define __SW_REV_A             0xF8
+#define __SW_REV_B             0xF0
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define        CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA                                AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID            1
+#define CONFIG_SYS_SCSI_MAX_LUN                        1
+#define CONFIG_SYS_SCSI_MAX_DEVICE             (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+                                               CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI             /* Enable PCI/PCIE */
+#define CONFIG_PCIE1           /* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF  0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE      0x00001000      /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF  0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE      0x00001000      /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS         0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF    0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE                0x00010000      /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END         0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
new file mode 100644 (file)
index 0000000..281a819
--- /dev/null
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef FSL_MMDC_H
+#define FSL_MMDC_H
+
+#define CONFIG_SYS_MMDC_CORE_ODT_TIMING                0x12554000
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0      0xbabf7954
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1      0xff328f64
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2      0x01ff00db
+
+#define CONFIG_SYS_MMDC_CORE_MISC              0x00000680
+#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT       0x00000800
+#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY    0x00002000
+#define CONFIG_SYS_MMDC_PHY_ODT_CTRL           0x0000022a
+
+#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY        0x00bf1023
+
+#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION    0x0000007f
+
+#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL         0xa1390003
+
+#define        FORCE_ZQ_AUTO_CALIBRATION               (0x1 << 16)
+
+/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
+#define WR_LVL_HW_EN                           0x00000001
+
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
+#define MPR_COMPARE_EN                         0x00000001
+
+#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG   0x40404040
+
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN      0x10000000
+
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
+#define AUTO_RD_CALIBRATION_EN                 0x00000010
+
+#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL     0x00030035
+
+#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
+
+#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL       0x103e8000
+
+#define START_REFRESH                          0x00000001
+
+/* MMDC Core Special Command Register (MDSCR) */
+#define CMD_ADDR_MSB_MR_OP(x)   (x << 24)
+
+#define  CMD_ADDR_LSB_MR_ADDR(x)    (x << 16)
+
+#define DISABLE_CFG_REQ                0x0
+#define CONFIGURATION_REQ      (0x1  << 15)
+#define WL_EN                  (0x1  << 9)
+
+#define        CMD_NORMAL              (0x0 << 4)
+#define        CMD_PRECHARGE           (0x1 << 4)
+#define        CMD_AUTO_REFRESH        (0x2 << 4)
+#define        CMD_LOAD_MODE_REG       (0x3 << 4)
+#define        CMD_ZQ_CALIBRATION      (0x4 << 4)
+#define        CMD_PRECHARGE_BANK_OPEN (0x5 << 4)
+#define        CMD_MRR                 (0x6 << 4)
+
+#define CMD_BANK_ADDR_0                0x0
+#define CMD_BANK_ADDR_1                0x1
+#define CMD_BANK_ADDR_2                0x2
+#define CMD_BANK_ADDR_3                0x3
+#define CMD_BANK_ADDR_4                0x4
+#define CMD_BANK_ADDR_5                0x5
+#define CMD_BANK_ADDR_6                0x6
+#define CMD_BANK_ADDR_7                0x7
+
+/* MMDC Registers */
+struct mmdc_p_regs {
+       u32 mdctl;
+       u32 mdpdc;
+       u32 mdotc;
+       u32 mdcfg0;
+       u32 mdcfg1;
+       u32 mdcfg2;
+       u32 mdmisc;
+       u32 mdscr;
+       u32 mdref;
+       u32 res1[2];
+       u32 mdrwd;
+       u32 mdor;
+       u32 mdmrr;
+       u32 mdcfg3lp;
+       u32 mdmr4;
+       u32 mdasp;
+       u32 res2[239];
+       u32 maarcr;
+       u32 mapsr;
+       u32 maexidr0;
+       u32 maexidr1;
+       u32 madpcr0;
+       u32 madpcr1;
+       u32 madpsr0;
+       u32 madpsr1;
+       u32 madpsr2;
+       u32 madpsr3;
+       u32 madpsr4;
+       u32 madpsr5;
+       u32 masbs0;
+       u32 masbs1;
+       u32 res3[2];
+       u32 magenp;
+       u32 res4[239];
+       u32 mpzqhwctrl;
+       u32 mpzqswctrl;
+       u32 mpwlgcr;
+       u32 mpwldectrl0;
+       u32 mpwldectrl1;
+       u32 mpwldlst;
+       u32 mpodtctrl;
+       u32 mprddqby0dl;
+       u32 mprddqby1dl;
+       u32 mprddqby2dl;
+       u32 mprddqby3dl;
+       u32 res5[4];
+       u32 mpdgctrl0;
+       u32 mpdgctrl1;
+       u32 mpdgdlst0;
+       u32 mprddlctl;
+       u32 mprddlst;
+       u32 mpwrdlctl;
+       u32 mpwrdlst;
+       u32 mpsdctrl;
+       u32 mpzqlp2ctl;
+       u32 mprddlhwctl;
+       u32 mpwrdlhwctl;
+       u32 mprddlhwst0;
+       u32 mprddlhwst1;
+       u32 mpwrdlhwst0;
+       u32 mpwrdlhwst1;
+       u32 mpwlhwerr;
+       u32 mpdghwst0;
+       u32 mpdghwst1;
+       u32 mpdghwst2;
+       u32 mpdghwst3;
+       u32 mppdcmpr1;
+       u32 mppdcmpr2;
+       u32 mpswdar0;
+       u32 mpswdrdr0;
+       u32 mpswdrdr1;
+       u32 mpswdrdr2;
+       u32 mpswdrdr3;
+       u32 mpswdrdr4;
+       u32 mpswdrdr5;
+       u32 mpswdrdr6;
+       u32 mpswdrdr7;
+       u32 mpmur0;
+       u32 mpwrcadl;
+       u32 mpdccr;
+};
+
+#endif /* FSL_MMDC_H */
index c5e42e69fe2b3476487bd5c8d6cc73fab7fecb00..253eddf1590bd89cc810b64247431a9476dca360 100644 (file)
@@ -59,10 +59,14 @@ struct fsl_xhci {
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
 #endif
 
 #define FSL_USB_XHCI_ADDR      {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \