default "sa1100" if CPU_SA1100
default "armv8" if ARM64
+config SYS_ARM_ARCH
+ int
+ default 4 if CPU_ARM720T
+ default 4 if CPU_ARM920T
+ default 5 if CPU_ARM926EJS
+ default 5 if CPU_ARM946ES
+ default 6 if CPU_ARM1136
+ default 6 if CPU_ARM1176
+ default 7 if CPU_V7
+ default 7 if CPU_V7M
+ default 5 if CPU_PXA
+ default 4 if CPU_SA1100
+ default 8 if ARM64
+
config SEMIHOSTING
bool "support boot from semihosting"
help
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
+ select ARM64
select OF_CONTROL
endchoice
arch-$(CONFIG_CPU_ARM720T) =-march=armv4
arch-$(CONFIG_CPU_ARM920T) =-march=armv4t
arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
-arch-$(CONFIG_CPU_ARM946ES) =-march=armv4
+arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te
arch-$(CONFIG_CPU_SA1100) =-march=armv4
arch-$(CONFIG_CPU_PXA) =
arch-$(CONFIG_CPU_ARM1136) =-march=armv5
}
#endif
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
void enable_usb_clocks(int index)
{
u32 *usbclkctrl = 0;
{
}
+/**
+ * vcores_init() - Assign omap_vcores based on board
+ *
+ * Function to pick the vcores based on board. This is expected to be
+ * overridden in the SoC family board file where desired.
+ */
+void __weak vcores_init(void)
+{
+}
+
void s_init(void)
{
}
#endif
setup_early_clocks();
do_board_detect();
+ vcores_init();
prcm_init();
}
};
struct vcores_data dra752_volts = {
- .mpu.value = VDD_MPU_DRA752,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA752,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA752,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA752,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA752,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
};
struct vcores_data dra722_volts = {
- .mpu.value = VDD_MPU_DRA72x,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA72x,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
- .gpu.value = VDD_GPU_DRA72x,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA72x,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .iva.value = VDD_IVA_DRA72x,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
}
#endif
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
void enable_usb_clocks(int index)
{
u32 cm_l3init_usb_otg_ss_clkctrl = 0;
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
- /* Enable 32 KHz clock for dwc3 */
+ /* Enable 32 KHz clock for USB_PHY1 */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ /* Enable 32 KHz clock for USB_PHY3 */
+ if (is_dra7xx())
+ setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
- /* Disable 32 KHz clock for dwc3 */
+ /* Disable 32 KHz clock for USB_PHY1 */
clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ /* Disable 32 KHz clock for USB_PHY3 */
+ if (is_dra7xx())
+ clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
.cm_clkmode_dpll_gmac = 0x4a0052a8,
.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
+ .cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698,
.cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0,
/* cm1.mpu */
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra186-p2771-0000.dtb \
tegra210-e2220-1170.dtb \
tegra210-p2371-0000.dtb \
tegra210-p2371-2180.dtb \
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
- socfpga_cyclone5_sr1500.dtb
+ socfpga_cyclone5_sr1500.dtb \
+ socfpga_cyclone5_vining_fpga.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
--- /dev/null
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "samtec VIN|ING FPGA";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ aliases {
+ ethernet0 = &gmac1;
+ udc0 = &usb0;
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rtc: rtc@68 {
+ compatible = "stm,m41t82";
+ reg = <0x68>;
+ };
+};
+
+&qspi {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ flash0: n25q128@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128", "spi-flash";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+
+ flash1: n25q00@1 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00", "spi-flash";
+ reg = <1>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--- /dev/null
+/dts-v1/;
+
+#include "tegra186.dtsi"
+
+/ {
+ model = "NVIDIA P2771-0000";
+ compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ sdhci0 = "/sdhci@3460000";
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0x60000000>;
+ };
+
+ sdhci@3460000 {
+ status = "okay";
+ bus-width = <8>;
+ };
+};
--- /dev/null
+#include "skeleton.dtsi"
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "nvidia,tegra186";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gpio@2200000 {
+ compatible = "nvidia,tegra186-gpio";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0x2200000 0x0 0x10000>,
+ <0x0 0x2210000 0x0 0x10000>;
+ interrupts =
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uarta: serial@3100000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03100000 0x0 0x10000>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sdhci@3460000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03460000 0x0 0x200>;
+ interrupts = <GIC_SPI 31 0x04>;
+ status = "disabled";
+ };
+
+ gpio@c2f0000 {
+ compatible = "nvidia,tegra186-gpio-aon";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0xc2f0000 0x0 0x1000>,
+ <0x0 0xc2f1000 0x0 0x1000>;
+ interrupts =
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880
-/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA752 1100
-#define VDD_EVE_DRA752 1060
-#define VDD_GPU_DRA752 1060
-#define VDD_CORE_DRA752 1060
-#define VDD_IVA_DRA752 1060
-
-/* DRA72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA72x 1100
-#define VDD_EVE_DRA72x 1060
-#define VDD_GPU_DRA72x 1060
-#define VDD_CORE_DRA72x 1060
-#define VDD_IVA_DRA72x 1060
+/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA7_NOM 1150
+#define VDD_CORE_DRA7_NOM 1150
+#define VDD_EVE_DRA7_NOM 1060
+#define VDD_GPU_DRA7_NOM 1060
+#define VDD_IVA_DRA7_NOM 1060
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
+#define VDD_EVE_DRA7_OD 1150
+#define VDD_GPU_DRA7_OD 1150
+#define VDD_IVA_DRA7_OD 1150
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
+#define VDD_EVE_DRA7_HIGH 1250
+#define VDD_GPU_DRA7_HIGH 1250
+#define VDD_IVA_DRA7_HIGH 1250
/* Efuse register offsets for DRA7xx platform */
#define DRA752_EFUSE_BASE 0x4A002000
/* STD_FUSE_OPP_VMIN_MPU_4 */
#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
+/* Common voltage and Efuse register macros */
+/* DRA74x/DRA75x/DRA72x */
+#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM
+#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM
+#define VDD_EVE_DRA7 VDD_EVE_DRA7_NOM
+#define VDD_GPU_DRA7 VDD_GPU_DRA7_NOM
+#define VDD_IVA_DRA7 VDD_IVA_DRA7_NOM
+
+#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM
+#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM
+#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM
+#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_NOM
+#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_NOM
+
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
void setup_early_clocks(void);
void prcm_init(void);
void do_board_detect(void);
+void vcores_init(void);
void bypass_dpll(u32 const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
#ifndef _TEGRA_GPIO_H_
#define _TEGRA_GPIO_H_
+#include <dt-bindings/gpio/tegra-gpio.h>
+
#define TEGRA_GPIOS_PER_PORT 8
#define TEGRA_PORTS_PER_BANK 4
#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
int id; /* device id/number, 0-3 */
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
+#ifndef CONFIG_TEGRA186
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
+#endif
struct gpio_desc cd_gpio; /* Change Detect GPIO */
struct gpio_desc pwr_gpio; /* Power GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-enum gpio_pin {
- GPIO_PA0 = 0, /* pin 0 */
- GPIO_PA1,
- GPIO_PA2,
- GPIO_PA3,
- GPIO_PA4,
- GPIO_PA5,
- GPIO_PA6,
- GPIO_PA7,
- GPIO_PB0, /* pin 8 */
- GPIO_PB1,
- GPIO_PB2,
- GPIO_PB3,
- GPIO_PB4,
- GPIO_PB5,
- GPIO_PB6,
- GPIO_PB7,
- GPIO_PC0, /* pin 16 */
- GPIO_PC1,
- GPIO_PC2,
- GPIO_PC3,
- GPIO_PC4,
- GPIO_PC5,
- GPIO_PC6,
- GPIO_PC7,
- GPIO_PD0, /* pin 24 */
- GPIO_PD1,
- GPIO_PD2,
- GPIO_PD3,
- GPIO_PD4,
- GPIO_PD5,
- GPIO_PD6,
- GPIO_PD7,
- GPIO_PE0, /* pin 32 */
- GPIO_PE1,
- GPIO_PE2,
- GPIO_PE3,
- GPIO_PE4,
- GPIO_PE5,
- GPIO_PE6,
- GPIO_PE7,
- GPIO_PF0, /* pin 40 */
- GPIO_PF1,
- GPIO_PF2,
- GPIO_PF3,
- GPIO_PF4,
- GPIO_PF5,
- GPIO_PF6,
- GPIO_PF7,
- GPIO_PG0, /* pin 48 */
- GPIO_PG1,
- GPIO_PG2,
- GPIO_PG3,
- GPIO_PG4,
- GPIO_PG5,
- GPIO_PG6,
- GPIO_PG7,
- GPIO_PH0, /* pin 56 */
- GPIO_PH1,
- GPIO_PH2,
- GPIO_PH3,
- GPIO_PH4,
- GPIO_PH5,
- GPIO_PH6,
- GPIO_PH7,
- GPIO_PI0, /* pin 64 */
- GPIO_PI1,
- GPIO_PI2,
- GPIO_PI3,
- GPIO_PI4,
- GPIO_PI5,
- GPIO_PI6,
- GPIO_PI7,
- GPIO_PJ0, /* pin 72 */
- GPIO_PJ1,
- GPIO_PJ2,
- GPIO_PJ3,
- GPIO_PJ4,
- GPIO_PJ5,
- GPIO_PJ6,
- GPIO_PJ7,
- GPIO_PK0, /* pin 80 */
- GPIO_PK1,
- GPIO_PK2,
- GPIO_PK3,
- GPIO_PK4,
- GPIO_PK5,
- GPIO_PK6,
- GPIO_PK7,
- GPIO_PL0, /* pin 88 */
- GPIO_PL1,
- GPIO_PL2,
- GPIO_PL3,
- GPIO_PL4,
- GPIO_PL5,
- GPIO_PL6,
- GPIO_PL7,
- GPIO_PM0, /* pin 96 */
- GPIO_PM1,
- GPIO_PM2,
- GPIO_PM3,
- GPIO_PM4,
- GPIO_PM5,
- GPIO_PM6,
- GPIO_PM7,
- GPIO_PN0, /* pin 104 */
- GPIO_PN1,
- GPIO_PN2,
- GPIO_PN3,
- GPIO_PN4,
- GPIO_PN5,
- GPIO_PN6,
- GPIO_PN7,
- GPIO_PO0, /* pin 112 */
- GPIO_PO1,
- GPIO_PO2,
- GPIO_PO3,
- GPIO_PO4,
- GPIO_PO5,
- GPIO_PO6,
- GPIO_PO7,
- GPIO_PP0, /* pin 120 */
- GPIO_PP1,
- GPIO_PP2,
- GPIO_PP3,
- GPIO_PP4,
- GPIO_PP5,
- GPIO_PP6,
- GPIO_PP7,
- GPIO_PQ0, /* pin 128 */
- GPIO_PQ1,
- GPIO_PQ2,
- GPIO_PQ3,
- GPIO_PQ4,
- GPIO_PQ5,
- GPIO_PQ6,
- GPIO_PQ7,
- GPIO_PR0, /* pin 136 */
- GPIO_PR1,
- GPIO_PR2,
- GPIO_PR3,
- GPIO_PR4,
- GPIO_PR5,
- GPIO_PR6,
- GPIO_PR7,
- GPIO_PS0, /* pin 144 */
- GPIO_PS1,
- GPIO_PS2,
- GPIO_PS3,
- GPIO_PS4,
- GPIO_PS5,
- GPIO_PS6,
- GPIO_PS7,
- GPIO_PT0, /* pin 152 */
- GPIO_PT1,
- GPIO_PT2,
- GPIO_PT3,
- GPIO_PT4,
- GPIO_PT5,
- GPIO_PT6,
- GPIO_PT7,
- GPIO_PU0, /* pin 160 */
- GPIO_PU1,
- GPIO_PU2,
- GPIO_PU3,
- GPIO_PU4,
- GPIO_PU5,
- GPIO_PU6,
- GPIO_PU7,
- GPIO_PV0, /* pin 168 */
- GPIO_PV1,
- GPIO_PV2,
- GPIO_PV3,
- GPIO_PV4,
- GPIO_PV5,
- GPIO_PV6,
- GPIO_PV7,
- GPIO_PW0, /* pin 176 */
- GPIO_PW1,
- GPIO_PW2,
- GPIO_PW3,
- GPIO_PW4,
- GPIO_PW5,
- GPIO_PW6,
- GPIO_PW7,
- GPIO_PX0, /* pin 184 */
- GPIO_PX1,
- GPIO_PX2,
- GPIO_PX3,
- GPIO_PX4,
- GPIO_PX5,
- GPIO_PX6,
- GPIO_PX7,
- GPIO_PY0, /* pin 192 */
- GPIO_PY1,
- GPIO_PY2,
- GPIO_PY3,
- GPIO_PY4,
- GPIO_PY5,
- GPIO_PY6,
- GPIO_PY7,
- GPIO_PZ0, /* pin 200 */
- GPIO_PZ1,
- GPIO_PZ2,
- GPIO_PZ3,
- GPIO_PZ4,
- GPIO_PZ5,
- GPIO_PZ6,
- GPIO_PZ7,
- GPIO_PAA0, /* pin 208 */
- GPIO_PAA1,
- GPIO_PAA2,
- GPIO_PAA3,
- GPIO_PAA4,
- GPIO_PAA5,
- GPIO_PAA6,
- GPIO_PAA7,
- GPIO_PBB0, /* pin 216 */
- GPIO_PBB1,
- GPIO_PBB2,
- GPIO_PBB3,
- GPIO_PBB4,
- GPIO_PBB5,
- GPIO_PBB6,
- GPIO_PBB7,
- GPIO_PCC0, /* pin 224 */
- GPIO_PCC1,
- GPIO_PCC2,
- GPIO_PCC3,
- GPIO_PCC4,
- GPIO_PCC5,
- GPIO_PCC6,
- GPIO_PCC7,
- GPIO_PDD0, /* pin 232 */
- GPIO_PDD1,
- GPIO_PDD2,
- GPIO_PDD3,
- GPIO_PDD4,
- GPIO_PDD5,
- GPIO_PDD6,
- GPIO_PDD7,
- GPIO_PEE0, /* pin 240 */
- GPIO_PEE1,
- GPIO_PEE2,
- GPIO_PEE3,
- GPIO_PEE4,
- GPIO_PEE5,
- GPIO_PEE6,
- GPIO_PEE7,
- GPIO_PFF0, /* pin 248 */
- GPIO_PFF1,
- GPIO_PFF2,
- GPIO_PFF3,
- GPIO_PFF4,
- GPIO_PFF5,
- GPIO_PFF6,
- GPIO_PFF7, /* pin 255 */
-};
-
#endif /* _TEGRA124_GPIO_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_H_
+#define _TEGRA186_GPIO_H_
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_TEGRA_H_
+#define _TEGRA186_TEGRA_H_
+
+#define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */
+#define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */
+#define NV_PA_SDRAM_BASE 0x80000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#endif
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-enum gpio_pin {
- GPIO_PA0 = 0, /* pin 0 */
- GPIO_PA1,
- GPIO_PA2,
- GPIO_PA3,
- GPIO_PA4,
- GPIO_PA5,
- GPIO_PA6,
- GPIO_PA7,
- GPIO_PB0, /* pin 8 */
- GPIO_PB1,
- GPIO_PB2,
- GPIO_PB3,
- GPIO_PB4,
- GPIO_PB5,
- GPIO_PB6,
- GPIO_PB7,
- GPIO_PC0, /* pin 16 */
- GPIO_PC1,
- GPIO_PC2,
- GPIO_PC3,
- GPIO_PC4,
- GPIO_PC5,
- GPIO_PC6,
- GPIO_PC7,
- GPIO_PD0, /* pin 24 */
- GPIO_PD1,
- GPIO_PD2,
- GPIO_PD3,
- GPIO_PD4,
- GPIO_PD5,
- GPIO_PD6,
- GPIO_PD7,
- GPIO_PE0, /* pin 32 */
- GPIO_PE1,
- GPIO_PE2,
- GPIO_PE3,
- GPIO_PE4,
- GPIO_PE5,
- GPIO_PE6,
- GPIO_PE7,
- GPIO_PF0, /* pin 40 */
- GPIO_PF1,
- GPIO_PF2,
- GPIO_PF3,
- GPIO_PF4,
- GPIO_PF5,
- GPIO_PF6,
- GPIO_PF7,
- GPIO_PG0, /* pin 48 */
- GPIO_PG1,
- GPIO_PG2,
- GPIO_PG3,
- GPIO_PG4,
- GPIO_PG5,
- GPIO_PG6,
- GPIO_PG7,
- GPIO_PH0, /* pin 56 */
- GPIO_PH1,
- GPIO_PH2,
- GPIO_PH3,
- GPIO_PH4,
- GPIO_PH5,
- GPIO_PH6,
- GPIO_PH7,
- GPIO_PI0, /* pin 64 */
- GPIO_PI1,
- GPIO_PI2,
- GPIO_PI3,
- GPIO_PI4,
- GPIO_PI5,
- GPIO_PI6,
- GPIO_PI7,
- GPIO_PJ0, /* pin 72 */
- GPIO_PJ1,
- GPIO_PJ2,
- GPIO_PJ3,
- GPIO_PJ4,
- GPIO_PJ5,
- GPIO_PJ6,
- GPIO_PJ7,
- GPIO_PK0, /* pin 80 */
- GPIO_PK1,
- GPIO_PK2,
- GPIO_PK3,
- GPIO_PK4,
- GPIO_PK5,
- GPIO_PK6,
- GPIO_PK7,
- GPIO_PL0, /* pin 88 */
- GPIO_PL1,
- GPIO_PL2,
- GPIO_PL3,
- GPIO_PL4,
- GPIO_PL5,
- GPIO_PL6,
- GPIO_PL7,
- GPIO_PM0, /* pin 96 */
- GPIO_PM1,
- GPIO_PM2,
- GPIO_PM3,
- GPIO_PM4,
- GPIO_PM5,
- GPIO_PM6,
- GPIO_PM7,
- GPIO_PN0, /* pin 104 */
- GPIO_PN1,
- GPIO_PN2,
- GPIO_PN3,
- GPIO_PN4,
- GPIO_PN5,
- GPIO_PN6,
- GPIO_PN7,
- GPIO_PO0, /* pin 112 */
- GPIO_PO1,
- GPIO_PO2,
- GPIO_PO3,
- GPIO_PO4,
- GPIO_PO5,
- GPIO_PO6,
- GPIO_PO7,
- GPIO_PP0, /* pin 120 */
- GPIO_PP1,
- GPIO_PP2,
- GPIO_PP3,
- GPIO_PP4,
- GPIO_PP5,
- GPIO_PP6,
- GPIO_PP7,
- GPIO_PQ0, /* pin 128 */
- GPIO_PQ1,
- GPIO_PQ2,
- GPIO_PQ3,
- GPIO_PQ4,
- GPIO_PQ5,
- GPIO_PQ6,
- GPIO_PQ7,
- GPIO_PR0, /* pin 136 */
- GPIO_PR1,
- GPIO_PR2,
- GPIO_PR3,
- GPIO_PR4,
- GPIO_PR5,
- GPIO_PR6,
- GPIO_PR7,
- GPIO_PS0, /* pin 144 */
- GPIO_PS1,
- GPIO_PS2,
- GPIO_PS3,
- GPIO_PS4,
- GPIO_PS5,
- GPIO_PS6,
- GPIO_PS7,
- GPIO_PT0, /* pin 152 */
- GPIO_PT1,
- GPIO_PT2,
- GPIO_PT3,
- GPIO_PT4,
- GPIO_PT5,
- GPIO_PT6,
- GPIO_PT7,
- GPIO_PU0, /* pin 160 */
- GPIO_PU1,
- GPIO_PU2,
- GPIO_PU3,
- GPIO_PU4,
- GPIO_PU5,
- GPIO_PU6,
- GPIO_PU7,
- GPIO_PV0, /* pin 168 */
- GPIO_PV1,
- GPIO_PV2,
- GPIO_PV3,
- GPIO_PV4,
- GPIO_PV5,
- GPIO_PV6,
- GPIO_PV7,
- GPIO_PW0, /* pin 176 */
- GPIO_PW1,
- GPIO_PW2,
- GPIO_PW3,
- GPIO_PW4,
- GPIO_PW5,
- GPIO_PW6,
- GPIO_PW7,
- GPIO_PX0, /* pin 184 */
- GPIO_PX1,
- GPIO_PX2,
- GPIO_PX3,
- GPIO_PX4,
- GPIO_PX5,
- GPIO_PX6,
- GPIO_PX7,
- GPIO_PY0, /* pin 192 */
- GPIO_PY1,
- GPIO_PY2,
- GPIO_PY3,
- GPIO_PY4,
- GPIO_PY5,
- GPIO_PY6,
- GPIO_PY7,
- GPIO_PZ0, /* pin 200 */
- GPIO_PZ1,
- GPIO_PZ2,
- GPIO_PZ3,
- GPIO_PZ4,
- GPIO_PZ5,
- GPIO_PZ6,
- GPIO_PZ7,
- GPIO_PAA0, /* pin 208 */
- GPIO_PAA1,
- GPIO_PAA2,
- GPIO_PAA3,
- GPIO_PAA4,
- GPIO_PAA5,
- GPIO_PAA6,
- GPIO_PAA7,
- GPIO_PBB0, /* pin 216 */
- GPIO_PBB1,
- GPIO_PBB2,
- GPIO_PBB3,
- GPIO_PBB4,
- GPIO_PBB5,
- GPIO_PBB6,
- GPIO_PBB7, /* pin 223 */
-};
-
#endif /* TEGRA20_GPIO_H_ */
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-enum gpio_pin {
- GPIO_PA0 = 0, /* pin 0 */
- GPIO_PA1,
- GPIO_PA2,
- GPIO_PA3,
- GPIO_PA4,
- GPIO_PA5,
- GPIO_PA6,
- GPIO_PA7,
- GPIO_PB0, /* pin 8 */
- GPIO_PB1,
- GPIO_PB2,
- GPIO_PB3,
- GPIO_PB4,
- GPIO_PB5,
- GPIO_PB6,
- GPIO_PB7,
- GPIO_PC0, /* pin 16 */
- GPIO_PC1,
- GPIO_PC2,
- GPIO_PC3,
- GPIO_PC4,
- GPIO_PC5,
- GPIO_PC6,
- GPIO_PC7,
- GPIO_PD0, /* pin 24 */
- GPIO_PD1,
- GPIO_PD2,
- GPIO_PD3,
- GPIO_PD4,
- GPIO_PD5,
- GPIO_PD6,
- GPIO_PD7,
- GPIO_PE0, /* pin 32 */
- GPIO_PE1,
- GPIO_PE2,
- GPIO_PE3,
- GPIO_PE4,
- GPIO_PE5,
- GPIO_PE6,
- GPIO_PE7,
- GPIO_PF0, /* pin 40 */
- GPIO_PF1,
- GPIO_PF2,
- GPIO_PF3,
- GPIO_PF4,
- GPIO_PF5,
- GPIO_PF6,
- GPIO_PF7,
- GPIO_PG0, /* pin 48 */
- GPIO_PG1,
- GPIO_PG2,
- GPIO_PG3,
- GPIO_PG4,
- GPIO_PG5,
- GPIO_PG6,
- GPIO_PG7,
- GPIO_PH0, /* pin 56 */
- GPIO_PH1,
- GPIO_PH2,
- GPIO_PH3,
- GPIO_PH4,
- GPIO_PH5,
- GPIO_PH6,
- GPIO_PH7,
- GPIO_PI0, /* pin 64 */
- GPIO_PI1,
- GPIO_PI2,
- GPIO_PI3,
- GPIO_PI4,
- GPIO_PI5,
- GPIO_PI6,
- GPIO_PI7,
- GPIO_PJ0, /* pin 72 */
- GPIO_PJ1,
- GPIO_PJ2,
- GPIO_PJ3,
- GPIO_PJ4,
- GPIO_PJ5,
- GPIO_PJ6,
- GPIO_PJ7,
- GPIO_PK0, /* pin 80 */
- GPIO_PK1,
- GPIO_PK2,
- GPIO_PK3,
- GPIO_PK4,
- GPIO_PK5,
- GPIO_PK6,
- GPIO_PK7,
- GPIO_PL0, /* pin 88 */
- GPIO_PL1,
- GPIO_PL2,
- GPIO_PL3,
- GPIO_PL4,
- GPIO_PL5,
- GPIO_PL6,
- GPIO_PL7,
- GPIO_PM0, /* pin 96 */
- GPIO_PM1,
- GPIO_PM2,
- GPIO_PM3,
- GPIO_PM4,
- GPIO_PM5,
- GPIO_PM6,
- GPIO_PM7,
- GPIO_PN0, /* pin 104 */
- GPIO_PN1,
- GPIO_PN2,
- GPIO_PN3,
- GPIO_PN4,
- GPIO_PN5,
- GPIO_PN6,
- GPIO_PN7,
- GPIO_PO0, /* pin 112 */
- GPIO_PO1,
- GPIO_PO2,
- GPIO_PO3,
- GPIO_PO4,
- GPIO_PO5,
- GPIO_PO6,
- GPIO_PO7,
- GPIO_PP0, /* pin 120 */
- GPIO_PP1,
- GPIO_PP2,
- GPIO_PP3,
- GPIO_PP4,
- GPIO_PP5,
- GPIO_PP6,
- GPIO_PP7,
- GPIO_PQ0, /* pin 128 */
- GPIO_PQ1,
- GPIO_PQ2,
- GPIO_PQ3,
- GPIO_PQ4,
- GPIO_PQ5,
- GPIO_PQ6,
- GPIO_PQ7,
- GPIO_PR0, /* pin 136 */
- GPIO_PR1,
- GPIO_PR2,
- GPIO_PR3,
- GPIO_PR4,
- GPIO_PR5,
- GPIO_PR6,
- GPIO_PR7,
- GPIO_PS0, /* pin 144 */
- GPIO_PS1,
- GPIO_PS2,
- GPIO_PS3,
- GPIO_PS4,
- GPIO_PS5,
- GPIO_PS6,
- GPIO_PS7,
- GPIO_PT0, /* pin 152 */
- GPIO_PT1,
- GPIO_PT2,
- GPIO_PT3,
- GPIO_PT4,
- GPIO_PT5,
- GPIO_PT6,
- GPIO_PT7,
- GPIO_PU0, /* pin 160 */
- GPIO_PU1,
- GPIO_PU2,
- GPIO_PU3,
- GPIO_PU4,
- GPIO_PU5,
- GPIO_PU6,
- GPIO_PU7,
- GPIO_PV0, /* pin 168 */
- GPIO_PV1,
- GPIO_PV2,
- GPIO_PV3,
- GPIO_PV4,
- GPIO_PV5,
- GPIO_PV6,
- GPIO_PV7,
- GPIO_PW0, /* pin 176 */
- GPIO_PW1,
- GPIO_PW2,
- GPIO_PW3,
- GPIO_PW4,
- GPIO_PW5,
- GPIO_PW6,
- GPIO_PW7,
- GPIO_PX0, /* pin 184 */
- GPIO_PX1,
- GPIO_PX2,
- GPIO_PX3,
- GPIO_PX4,
- GPIO_PX5,
- GPIO_PX6,
- GPIO_PX7,
- GPIO_PY0, /* pin 192 */
- GPIO_PY1,
- GPIO_PY2,
- GPIO_PY3,
- GPIO_PY4,
- GPIO_PY5,
- GPIO_PY6,
- GPIO_PY7,
- GPIO_PZ0, /* pin 200 */
- GPIO_PZ1,
- GPIO_PZ2,
- GPIO_PZ3,
- GPIO_PZ4,
- GPIO_PZ5,
- GPIO_PZ6,
- GPIO_PZ7,
- GPIO_PAA0, /* pin 208 */
- GPIO_PAA1,
- GPIO_PAA2,
- GPIO_PAA3,
- GPIO_PAA4,
- GPIO_PAA5,
- GPIO_PAA6,
- GPIO_PAA7,
- GPIO_PBB0, /* pin 216 */
- GPIO_PBB1,
- GPIO_PBB2,
- GPIO_PBB3,
- GPIO_PBB4,
- GPIO_PBB5,
- GPIO_PBB6,
- GPIO_PBB7,
- GPIO_PCC0, /* pin 224 */
- GPIO_PCC1,
- GPIO_PCC2,
- GPIO_PCC3,
- GPIO_PCC4,
- GPIO_PCC5,
- GPIO_PCC6,
- GPIO_PCC7,
- GPIO_PDD0, /* pin 232 */
- GPIO_PDD1,
- GPIO_PDD2,
- GPIO_PDD3,
- GPIO_PDD4,
- GPIO_PDD5,
- GPIO_PDD6,
- GPIO_PDD7,
- GPIO_PEE0, /* pin 240 */
- GPIO_PEE1,
- GPIO_PEE2,
- GPIO_PEE3,
- GPIO_PEE4,
- GPIO_PEE5,
- GPIO_PEE6,
- GPIO_PEE7,
- GPIO_PFF0, /* pin 248 */
- GPIO_PFF1,
- GPIO_PFF2,
- GPIO_PFF3,
- GPIO_PFF4,
- GPIO_PFF5,
- GPIO_PFF6,
- GPIO_PFF7, /* pin 255 */
-};
-
#endif /* _TEGRA210_GPIO_H_ */
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-enum gpio_pin {
- GPIO_PA0 = 0, /* pin 0 */
- GPIO_PA1,
- GPIO_PA2,
- GPIO_PA3,
- GPIO_PA4,
- GPIO_PA5,
- GPIO_PA6,
- GPIO_PA7,
- GPIO_PB0, /* pin 8 */
- GPIO_PB1,
- GPIO_PB2,
- GPIO_PB3,
- GPIO_PB4,
- GPIO_PB5,
- GPIO_PB6,
- GPIO_PB7,
- GPIO_PC0, /* pin 16 */
- GPIO_PC1,
- GPIO_PC2,
- GPIO_PC3,
- GPIO_PC4,
- GPIO_PC5,
- GPIO_PC6,
- GPIO_PC7,
- GPIO_PD0, /* pin 24 */
- GPIO_PD1,
- GPIO_PD2,
- GPIO_PD3,
- GPIO_PD4,
- GPIO_PD5,
- GPIO_PD6,
- GPIO_PD7,
- GPIO_PE0, /* pin 32 */
- GPIO_PE1,
- GPIO_PE2,
- GPIO_PE3,
- GPIO_PE4,
- GPIO_PE5,
- GPIO_PE6,
- GPIO_PE7,
- GPIO_PF0, /* pin 40 */
- GPIO_PF1,
- GPIO_PF2,
- GPIO_PF3,
- GPIO_PF4,
- GPIO_PF5,
- GPIO_PF6,
- GPIO_PF7,
- GPIO_PG0, /* pin 48 */
- GPIO_PG1,
- GPIO_PG2,
- GPIO_PG3,
- GPIO_PG4,
- GPIO_PG5,
- GPIO_PG6,
- GPIO_PG7,
- GPIO_PH0, /* pin 56 */
- GPIO_PH1,
- GPIO_PH2,
- GPIO_PH3,
- GPIO_PH4,
- GPIO_PH5,
- GPIO_PH6,
- GPIO_PH7,
- GPIO_PI0, /* pin 64 */
- GPIO_PI1,
- GPIO_PI2,
- GPIO_PI3,
- GPIO_PI4,
- GPIO_PI5,
- GPIO_PI6,
- GPIO_PI7,
- GPIO_PJ0, /* pin 72 */
- GPIO_PJ1,
- GPIO_PJ2,
- GPIO_PJ3,
- GPIO_PJ4,
- GPIO_PJ5,
- GPIO_PJ6,
- GPIO_PJ7,
- GPIO_PK0, /* pin 80 */
- GPIO_PK1,
- GPIO_PK2,
- GPIO_PK3,
- GPIO_PK4,
- GPIO_PK5,
- GPIO_PK6,
- GPIO_PK7,
- GPIO_PL0, /* pin 88 */
- GPIO_PL1,
- GPIO_PL2,
- GPIO_PL3,
- GPIO_PL4,
- GPIO_PL5,
- GPIO_PL6,
- GPIO_PL7,
- GPIO_PM0, /* pin 96 */
- GPIO_PM1,
- GPIO_PM2,
- GPIO_PM3,
- GPIO_PM4,
- GPIO_PM5,
- GPIO_PM6,
- GPIO_PM7,
- GPIO_PN0, /* pin 104 */
- GPIO_PN1,
- GPIO_PN2,
- GPIO_PN3,
- GPIO_PN4,
- GPIO_PN5,
- GPIO_PN6,
- GPIO_PN7,
- GPIO_PO0, /* pin 112 */
- GPIO_PO1,
- GPIO_PO2,
- GPIO_PO3,
- GPIO_PO4,
- GPIO_PO5,
- GPIO_PO6,
- GPIO_PO7,
- GPIO_PP0, /* pin 120 */
- GPIO_PP1,
- GPIO_PP2,
- GPIO_PP3,
- GPIO_PP4,
- GPIO_PP5,
- GPIO_PP6,
- GPIO_PP7,
- GPIO_PQ0, /* pin 128 */
- GPIO_PQ1,
- GPIO_PQ2,
- GPIO_PQ3,
- GPIO_PQ4,
- GPIO_PQ5,
- GPIO_PQ6,
- GPIO_PQ7,
- GPIO_PR0, /* pin 136 */
- GPIO_PR1,
- GPIO_PR2,
- GPIO_PR3,
- GPIO_PR4,
- GPIO_PR5,
- GPIO_PR6,
- GPIO_PR7,
- GPIO_PS0, /* pin 144 */
- GPIO_PS1,
- GPIO_PS2,
- GPIO_PS3,
- GPIO_PS4,
- GPIO_PS5,
- GPIO_PS6,
- GPIO_PS7,
- GPIO_PT0, /* pin 152 */
- GPIO_PT1,
- GPIO_PT2,
- GPIO_PT3,
- GPIO_PT4,
- GPIO_PT5,
- GPIO_PT6,
- GPIO_PT7,
- GPIO_PU0, /* pin 160 */
- GPIO_PU1,
- GPIO_PU2,
- GPIO_PU3,
- GPIO_PU4,
- GPIO_PU5,
- GPIO_PU6,
- GPIO_PU7,
- GPIO_PV0, /* pin 168 */
- GPIO_PV1,
- GPIO_PV2,
- GPIO_PV3,
- GPIO_PV4,
- GPIO_PV5,
- GPIO_PV6,
- GPIO_PV7,
- GPIO_PW0, /* pin 176 */
- GPIO_PW1,
- GPIO_PW2,
- GPIO_PW3,
- GPIO_PW4,
- GPIO_PW5,
- GPIO_PW6,
- GPIO_PW7,
- GPIO_PX0, /* pin 184 */
- GPIO_PX1,
- GPIO_PX2,
- GPIO_PX3,
- GPIO_PX4,
- GPIO_PX5,
- GPIO_PX6,
- GPIO_PX7,
- GPIO_PY0, /* pin 192 */
- GPIO_PY1,
- GPIO_PY2,
- GPIO_PY3,
- GPIO_PY4,
- GPIO_PY5,
- GPIO_PY6,
- GPIO_PY7,
- GPIO_PZ0, /* pin 200 */
- GPIO_PZ1,
- GPIO_PZ2,
- GPIO_PZ3,
- GPIO_PZ4,
- GPIO_PZ5,
- GPIO_PZ6,
- GPIO_PZ7,
- GPIO_PAA0, /* pin 208 */
- GPIO_PAA1,
- GPIO_PAA2,
- GPIO_PAA3,
- GPIO_PAA4,
- GPIO_PAA5,
- GPIO_PAA6,
- GPIO_PAA7,
- GPIO_PBB0, /* pin 216 */
- GPIO_PBB1,
- GPIO_PBB2,
- GPIO_PBB3,
- GPIO_PBB4,
- GPIO_PBB5,
- GPIO_PBB6,
- GPIO_PBB7,
- GPIO_PCC0, /* pin 224 */
- GPIO_PCC1,
- GPIO_PCC2,
- GPIO_PCC3,
- GPIO_PCC4,
- GPIO_PCC5,
- GPIO_PCC6,
- GPIO_PCC7,
- GPIO_PDD0, /* pin 232 */
- GPIO_PDD1,
- GPIO_PDD2,
- GPIO_PDD3,
- GPIO_PDD4,
- GPIO_PDD5,
- GPIO_PDD6,
- GPIO_PDD7,
- GPIO_PEE0, /* pin 240 */
- GPIO_PEE1,
- GPIO_PEE2,
- GPIO_PEE3,
- GPIO_PEE4,
- GPIO_PEE5,
- GPIO_PEE6,
- GPIO_PEE7, /* pin 247 */
-};
-
#endif /* _TEGRA30_GPIO_H_ */
*/
#include <config.h>
+#include <asm/unified.h>
/*
* Endian independent macros for shifting bytes within registers.
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
+ u32 cm_coreaon_usb_phy3_core_clkctrl;
u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */
--- /dev/null
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+ .syntax unified
+#endif
+
+#ifdef CONFIG_CPU_V7M
+#define AR_CLASS(x...)
+#define M_CLASS(x...) x
+#else
+#define AR_CLASS(x...) x
+#define M_CLASS(x...)
+#endif
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE PSR_T_BIT
+
+#define ARM(x...)
+#define THUMB(x...) x
+#ifdef __ASSEMBLY__
+#define W(instr) instr.w
+#else
+#define WASM(instr) #instr ".w"
+#endif
+
+#else /* !CONFIG_THUMB2_KERNEL */
+
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE 0
+
+#define ARM(x...) x
+#define THUMB(x...)
+#ifdef __ASSEMBLY__
+#define W(instr) instr
+#else
+#define WASM(instr) #instr
+#endif
+
+#endif /* CONFIG_THUMB2_KERNEL */
+
+#ifndef CONFIG_ARM_ASM_UNIFIED
+
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+ .macro it, cond
+ .endm
+ .macro itt, cond
+ .endm
+ .macro ite, cond
+ .endm
+ .macro ittt, cond
+ .endm
+ .macro itte, cond
+ .endm
+ .macro itet, cond
+ .endm
+ .macro itee, cond
+ .endm
+ .macro itttt, cond
+ .endm
+ .macro ittte, cond
+ .endm
+ .macro ittet, cond
+ .endm
+ .macro ittee, cond
+ .endm
+ .macro itett, cond
+ .endm
+ .macro itete, cond
+ .endm
+ .macro iteet, cond
+ .endm
+ .macro iteee, cond
+ .endm
+#else /* !__ASSEMBLY__ */
+__asm__(
+" .macro it, cond\n"
+" .endm\n"
+" .macro itt, cond\n"
+" .endm\n"
+" .macro ite, cond\n"
+" .endm\n"
+" .macro ittt, cond\n"
+" .endm\n"
+" .macro itte, cond\n"
+" .endm\n"
+" .macro itet, cond\n"
+" .endm\n"
+" .macro itee, cond\n"
+" .endm\n"
+" .macro itttt, cond\n"
+" .endm\n"
+" .macro ittte, cond\n"
+" .endm\n"
+" .macro ittet, cond\n"
+" .endm\n"
+" .macro ittee, cond\n"
+" .endm\n"
+" .macro itett, cond\n"
+" .endm\n"
+" .macro itete, cond\n"
+" .endm\n"
+" .macro iteet, cond\n"
+" .endm\n"
+" .macro iteee, cond\n"
+" .endm\n");
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_ARM_ASM_UNIFIED */
+
+#endif /* !__ASM_UNIFIED_H */
# SPDX-License-Identifier: GPL-2.0+
#
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
- _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o \
- _uldivmod.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
+ lib1funcs.o uldivmod.o div0.o \
+ div64.o muldi3.o
ifdef CONFIG_CPU_V7M
obj-y += vectors_m.o crt0.o
extra-y += eabi_compat.o
endif
+asflags-y += -DCONFIG_ARM_ASM_UNIFIED
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+asflags-y += -D__LINUX_ARM_ARCH__=4
+else
+asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
+endif
+
# some files can only build in ARM or THUMB2, not THUMB1
ifdef CONFIG_SYS_THUMB_BUILD
+asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL
ifndef CONFIG_HAS_THUMB2
# for C files, just apend -marm, which will override previous -mthumb*
AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
-
endif
endif
+++ /dev/null
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
- Free Software Foundation, Inc.
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-#ifdef __ARMEB__
-#define al r1
-#define ah r0
-#else
-#define al r0
-#define ah r1
-#endif
-
-.globl __ashldi3
-__ashldi3:
-ENTRY(__aeabi_llsl)
-
- subs r3, r2, #32
- rsb ip, r2, #32
- movmi ah, ah, lsl r2
- movpl ah, al, lsl r3
- orrmi ah, ah, al, lsr ip
- mov al, al, lsl r2
- mov pc, lr
-ENDPROC(__aeabi_llsl)
+++ /dev/null
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
- Free Software Foundation, Inc.
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-#ifdef __ARMEB__
-#define al r1
-#define ah r0
-#else
-#define al r0
-#define ah r1
-#endif
-
-.globl __ashrdi3
-__ashrdi3:
-ENTRY(__aeabi_lasr)
-
- subs r3, r2, #32
- rsb ip, r2, #32
- movmi al, al, lsr r2
- movpl al, ah, asr r3
- orrmi al, al, ah, lsl ip
- mov ah, ah, asr r2
- mov pc, lr
-ENDPROC(__aeabi_lasr)
+++ /dev/null
-#include <linux/linkage.h>
-
-.macro ARM_DIV_BODY dividend, divisor, result, curbit
-
-#if __LINUX_ARM_ARCH__ >= 5
-
- clz \curbit, \divisor
- clz \result, \dividend
- sub \result, \curbit, \result
- mov \curbit, #1
- mov \divisor, \divisor, lsl \result
- mov \curbit, \curbit, lsl \result
- mov \result, #0
-
-#else
-
- @ Initially shift the divisor left 3 bits if possible,
- @ set curbit accordingly. This allows for curbit to be located
- @ at the left end of each 4 bit nibbles in the division loop
- @ to save one loop in most cases.
- tst \divisor, #0xe0000000
- moveq \divisor, \divisor, lsl #3
- moveq \curbit, #8
- movne \curbit, #1
-
- @ Unless the divisor is very big, shift it up in multiples of
- @ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
- @ larger than the dividend.
-1: cmp \divisor, #0x10000000
- cmplo \divisor, \dividend
- movlo \divisor, \divisor, lsl #4
- movlo \curbit, \curbit, lsl #4
- blo 1b
-
- @ For very big divisors, we must shift it a bit at a time, or
- @ we will be in danger of overflowing.
-1: cmp \divisor, #0x80000000
- cmplo \divisor, \dividend
- movlo \divisor, \divisor, lsl #1
- movlo \curbit, \curbit, lsl #1
- blo 1b
-
- mov \result, #0
-
-#endif
-
- @ Division loop
-1: cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
- orrhs \result, \result, \curbit
- cmp \dividend, \divisor, lsr #1
- subhs \dividend, \dividend, \divisor, lsr #1
- orrhs \result, \result, \curbit, lsr #1
- cmp \dividend, \divisor, lsr #2
- subhs \dividend, \dividend, \divisor, lsr #2
- orrhs \result, \result, \curbit, lsr #2
- cmp \dividend, \divisor, lsr #3
- subhs \dividend, \dividend, \divisor, lsr #3
- orrhs \result, \result, \curbit, lsr #3
- cmp \dividend, #0 @ Early termination?
- movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
- movne \divisor, \divisor, lsr #4
- bne 1b
-
-.endm
-
-.macro ARM_DIV2_ORDER divisor, order
-
-#if __LINUX_ARM_ARCH__ >= 5
-
- clz \order, \divisor
- rsb \order, \order, #31
-
-#else
-
- cmp \divisor, #(1 << 16)
- movhs \divisor, \divisor, lsr #16
- movhs \order, #16
- movlo \order, #0
-
- cmp \divisor, #(1 << 8)
- movhs \divisor, \divisor, lsr #8
- addhs \order, \order, #8
-
- cmp \divisor, #(1 << 4)
- movhs \divisor, \divisor, lsr #4
- addhs \order, \order, #4
-
- cmp \divisor, #(1 << 2)
- addhi \order, \order, #3
- addls \order, \order, \divisor, lsr #1
-
-#endif
-
-.endm
-
- .align 5
-.globl __divsi3
-__divsi3:
-ENTRY(__aeabi_idiv)
- cmp r1, #0
- eor ip, r0, r1 @ save the sign of the result.
- beq Ldiv0
- rsbmi r1, r1, #0 @ loops below use unsigned.
- subs r2, r1, #1 @ division by 1 or -1 ?
- beq 10f
- movs r3, r0
- rsbmi r3, r0, #0 @ positive dividend value
- cmp r3, r1
- bls 11f
- tst r1, r2 @ divisor is power of 2 ?
- beq 12f
-
- ARM_DIV_BODY r3, r1, r0, r2
-
- cmp ip, #0
- rsbmi r0, r0, #0
- mov pc, lr
-
-10: teq ip, r0 @ same sign ?
- rsbmi r0, r0, #0
- mov pc, lr
-
-11: movlo r0, #0
- moveq r0, ip, asr #31
- orreq r0, r0, #1
- mov pc, lr
-
-12: ARM_DIV2_ORDER r1, r2
-
- cmp ip, #0
- mov r0, r3, lsr r2
- rsbmi r0, r0, #0
- mov pc, lr
-
-Ldiv0:
-
- str lr, [sp, #-4]!
- bl __div0
- mov r0, #0 @ About as wrong as it could be.
- ldr pc, [sp], #4
-ENDPROC(__aeabi_idiv)
+++ /dev/null
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
- Free Software Foundation, Inc.
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-#ifdef __ARMEB__
-#define al r1
-#define ah r0
-#else
-#define al r0
-#define ah r1
-#endif
-
-.globl __lshrdi3
-__lshrdi3:
-ENTRY(__aeabi_llsr)
-
- subs r3, r2, #32
- rsb ip, r2, #32
- movmi al, al, lsr r2
- movpl al, ah, lsr r3
- orrmi al, al, ah, lsl ip
- mov ah, ah, lsr r2
- mov pc, lr
-ENDPROC(__aeabi_llsr)
+++ /dev/null
-#include <linux/linkage.h>
-
-.macro ARM_MOD_BODY dividend, divisor, order, spare
-
-#if __LINUX_ARM_ARCH__ >= 5
-
- clz \order, \divisor
- clz \spare, \dividend
- sub \order, \order, \spare
- mov \divisor, \divisor, lsl \order
-
-#else
-
- mov \order, #0
-
- @ Unless the divisor is very big, shift it up in multiples of
- @ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
- @ larger than the dividend.
-1: cmp \divisor, #0x10000000
- cmplo \divisor, \dividend
- movlo \divisor, \divisor, lsl #4
- addlo \order, \order, #4
- blo 1b
-
- @ For very big divisors, we must shift it a bit at a time, or
- @ we will be in danger of overflowing.
-1: cmp \divisor, #0x80000000
- cmplo \divisor, \dividend
- movlo \divisor, \divisor, lsl #1
- addlo \order, \order, #1
- blo 1b
-
-#endif
-
- @ Perform all needed substractions to keep only the reminder.
- @ Do comparisons in batch of 4 first.
- subs \order, \order, #3 @ yes, 3 is intended here
- blt 2f
-
-1: cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
- cmp \dividend, \divisor, lsr #1
- subhs \dividend, \dividend, \divisor, lsr #1
- cmp \dividend, \divisor, lsr #2
- subhs \dividend, \dividend, \divisor, lsr #2
- cmp \dividend, \divisor, lsr #3
- subhs \dividend, \dividend, \divisor, lsr #3
- cmp \dividend, #1
- mov \divisor, \divisor, lsr #4
- subges \order, \order, #4
- bge 1b
-
- tst \order, #3
- teqne \dividend, #0
- beq 5f
-
- @ Either 1, 2 or 3 comparison/substractions are left.
-2: cmn \order, #2
- blt 4f
- beq 3f
- cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
- mov \divisor, \divisor, lsr #1
-3: cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
- mov \divisor, \divisor, lsr #1
-4: cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
-5:
-.endm
-
- .align 5
-ENTRY(__modsi3)
- cmp r1, #0
- beq Ldiv0
- rsbmi r1, r1, #0 @ loops below use unsigned.
- movs ip, r0 @ preserve sign of dividend
- rsbmi r0, r0, #0 @ if negative make positive
- subs r2, r1, #1 @ compare divisor with 1
- cmpne r0, r1 @ compare dividend with divisor
- moveq r0, #0
- tsthi r1, r2 @ see if divisor is power of 2
- andeq r0, r0, r2
- bls 10f
-
- ARM_MOD_BODY r0, r1, r2, r3
-
-10: cmp ip, #0
- rsbmi r0, r0, #0
- mov pc, lr
-ENDPROC(__modsi3)
-
-Ldiv0:
-
- str lr, [sp, #-4]!
- bl __div0
- mov r0, #0 @ About as wrong as it could be.
- ldr pc, [sp], #4
+++ /dev/null
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-dividend .req r0
-divisor .req r1
-result .req r2
-curbit .req r3
-/* ip .req r12 */
-/* sp .req r13 */
-/* lr .req r14 */
-/* pc .req r15 */
- .text
- .globl __udivsi3
- .type __udivsi3 ,function
- .globl __aeabi_uidiv
- .type __aeabi_uidiv ,function
- .align 0
- __udivsi3:
- __aeabi_uidiv:
- cmp divisor, #0
- beq Ldiv0
- mov curbit, #1
- mov result, #0
- cmp dividend, divisor
- bcc Lgot_result
-Loop1:
- @ Unless the divisor is very big, shift it up in multiples of
- @ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
- @ larger than the dividend.
- cmp divisor, #0x10000000
- cmpcc divisor, dividend
- movcc divisor, divisor, lsl #4
- movcc curbit, curbit, lsl #4
- bcc Loop1
-Lbignum:
- @ For very big divisors, we must shift it a bit at a time, or
- @ we will be in danger of overflowing.
- cmp divisor, #0x80000000
- cmpcc divisor, dividend
- movcc divisor, divisor, lsl #1
- movcc curbit, curbit, lsl #1
- bcc Lbignum
-Loop3:
- @ Test for possible subtractions, and note which bits
- @ are done in the result. On the final pass, this may subtract
- @ too much from the dividend, but the result will be ok, since the
- @ "bit" will have been shifted out at the bottom.
- cmp dividend, divisor
- subcs dividend, dividend, divisor
- orrcs result, result, curbit
- cmp dividend, divisor, lsr #1
- subcs dividend, dividend, divisor, lsr #1
- orrcs result, result, curbit, lsr #1
- cmp dividend, divisor, lsr #2
- subcs dividend, dividend, divisor, lsr #2
- orrcs result, result, curbit, lsr #2
- cmp dividend, divisor, lsr #3
- subcs dividend, dividend, divisor, lsr #3
- orrcs result, result, curbit, lsr #3
- cmp dividend, #0 @ Early termination?
- movnes curbit, curbit, lsr #4 @ No, any more bits to do?
- movne divisor, divisor, lsr #4
- bne Loop3
-Lgot_result:
- mov r0, result
- mov pc, lr
-Ldiv0:
- str lr, [sp, #-4]!
- bl __div0 (PLT)
- mov r0, #0 @ about as wrong as it could be
- ldmia sp!, {pc}
- .size __udivsi3 , . - __udivsi3
-
-ENTRY(__aeabi_uidivmod)
-
- stmfd sp!, {r0, r1, ip, lr}
- bl __aeabi_uidiv
- ldmfd sp!, {r1, r2, ip, lr}
- mul r3, r0, r2
- sub r1, r1, r3
- mov pc, lr
-ENDPROC(__aeabi_uidivmod)
-
-ENTRY(__aeabi_idivmod)
-
- stmfd sp!, {r0, r1, ip, lr}
- bl __aeabi_idiv
- ldmfd sp!, {r1, r2, ip, lr}
- mul r3, r0, r2
- sub r1, r1, r3
- mov pc, lr
-ENDPROC(__aeabi_idivmod)
+++ /dev/null
-/*
- * Copyright 2010, Google Inc.
- *
- * Brought in from coreboot uldivmod.S
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-/* We don't use Thumb instructions for now */
-#define ARM(x...) x
-#define THUMB(x...)
-
-/*
- * A, Q = r0 + (r1 << 32)
- * B, R = r2 + (r3 << 32)
- * A / B = Q ... R
- */
-
-A_0 .req r0
-A_1 .req r1
-B_0 .req r2
-B_1 .req r3
-C_0 .req r4
-C_1 .req r5
-D_0 .req r6
-D_1 .req r7
-
-Q_0 .req r0
-Q_1 .req r1
-R_0 .req r2
-R_1 .req r3
-
-THUMB(
-TMP .req r8
-)
-
-ENTRY(__aeabi_uldivmod)
- stmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
- @ Test if B == 0
- orrs ip, B_0, B_1 @ Z set -> B == 0
- beq L_div_by_0
- @ Test if B is power of 2: (B & (B - 1)) == 0
- subs C_0, B_0, #1
- sbc C_1, B_1, #0
- tst C_0, B_0
- tsteq B_1, C_1
- beq L_pow2
- @ Test if A_1 == B_1 == 0
- orrs ip, A_1, B_1
- beq L_div_32_32
-
-L_div_64_64:
-/* CLZ only exists in ARM architecture version 5 and above. */
-#ifdef HAVE_CLZ
- mov C_0, #1
- mov C_1, #0
- @ D_0 = clz A
- teq A_1, #0
- clz D_0, A_1
- clzeq ip, A_0
- addeq D_0, D_0, ip
- @ D_1 = clz B
- teq B_1, #0
- clz D_1, B_1
- clzeq ip, B_0
- addeq D_1, D_1, ip
- @ if clz B - clz A > 0
- subs D_0, D_1, D_0
- bls L_done_shift
- @ B <<= (clz B - clz A)
- subs D_1, D_0, #32
- rsb ip, D_0, #32
- movmi B_1, B_1, lsl D_0
-ARM( orrmi B_1, B_1, B_0, lsr ip )
-THUMB( lsrmi TMP, B_0, ip )
-THUMB( orrmi B_1, B_1, TMP )
- movpl B_1, B_0, lsl D_1
- mov B_0, B_0, lsl D_0
- @ C = 1 << (clz B - clz A)
- movmi C_1, C_1, lsl D_0
-ARM( orrmi C_1, C_1, C_0, lsr ip )
-THUMB( lsrmi TMP, C_0, ip )
-THUMB( orrmi C_1, C_1, TMP )
- movpl C_1, C_0, lsl D_1
- mov C_0, C_0, lsl D_0
-L_done_shift:
- mov D_0, #0
- mov D_1, #0
- @ C: current bit; D: result
-#else
- @ C: current bit; D: result
- mov C_0, #1
- mov C_1, #0
- mov D_0, #0
- mov D_1, #0
-L_lsl_4:
- cmp B_1, #0x10000000
- cmpcc B_1, A_1
- cmpeq B_0, A_0
- bcs L_lsl_1
- @ B <<= 4
- mov B_1, B_1, lsl #4
- orr B_1, B_1, B_0, lsr #28
- mov B_0, B_0, lsl #4
- @ C <<= 4
- mov C_1, C_1, lsl #4
- orr C_1, C_1, C_0, lsr #28
- mov C_0, C_0, lsl #4
- b L_lsl_4
-L_lsl_1:
- cmp B_1, #0x80000000
- cmpcc B_1, A_1
- cmpeq B_0, A_0
- bcs L_subtract
- @ B <<= 1
- mov B_1, B_1, lsl #1
- orr B_1, B_1, B_0, lsr #31
- mov B_0, B_0, lsl #1
- @ C <<= 1
- mov C_1, C_1, lsl #1
- orr C_1, C_1, C_0, lsr #31
- mov C_0, C_0, lsl #1
- b L_lsl_1
-#endif
-L_subtract:
- @ if A >= B
- cmp A_1, B_1
- cmpeq A_0, B_0
- bcc L_update
- @ A -= B
- subs A_0, A_0, B_0
- sbc A_1, A_1, B_1
- @ D |= C
- orr D_0, D_0, C_0
- orr D_1, D_1, C_1
-L_update:
- @ if A == 0: break
- orrs ip, A_1, A_0
- beq L_exit
- @ C >>= 1
- movs C_1, C_1, lsr #1
- movs C_0, C_0, rrx
- @ if C == 0: break
- orrs ip, C_1, C_0
- beq L_exit
- @ B >>= 1
- movs B_1, B_1, lsr #1
- mov B_0, B_0, rrx
- b L_subtract
-L_exit:
- @ Note: A, B & Q, R are aliases
- mov R_0, A_0
- mov R_1, A_1
- mov Q_0, D_0
- mov Q_1, D_1
- ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-
-L_div_32_32:
- @ Note: A_0 & r0 are aliases
- @ Q_1 r1
- mov r1, B_0
- bl __aeabi_uidivmod
- mov R_0, r1
- mov R_1, #0
- mov Q_1, #0
- ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-
-L_pow2:
-#ifdef HAVE_CLZ
- @ Note: A, B and Q, R are aliases
- @ R = A & (B - 1)
- and C_0, A_0, C_0
- and C_1, A_1, C_1
- @ Q = A >> log2(B)
- @ Note: B must not be 0 here!
- clz D_0, B_0
- add D_1, D_0, #1
- rsbs D_0, D_0, #31
- bpl L_1
- clz D_0, B_1
- rsb D_0, D_0, #31
- mov A_0, A_1, lsr D_0
- add D_0, D_0, #32
-L_1:
- movpl A_0, A_0, lsr D_0
-ARM( orrpl A_0, A_0, A_1, lsl D_1 )
-THUMB( lslpl TMP, A_1, D_1 )
-THUMB( orrpl A_0, A_0, TMP )
- mov A_1, A_1, lsr D_0
- @ Mov back C to R
- mov R_0, C_0
- mov R_1, C_1
- ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-#else
- @ Note: A, B and Q, R are aliases
- @ R = A & (B - 1)
- and C_0, A_0, C_0
- and C_1, A_1, C_1
- @ Q = A >> log2(B)
- @ Note: B must not be 0 here!
- @ Count the leading zeroes in B.
- mov D_0, #0
- orrs B_0, B_0, B_0
- @ If B is greater than 1 << 31, divide A and B by 1 << 32.
- moveq A_0, A_1
- moveq A_1, #0
- moveq B_0, B_1
- @ Count the remaining leading zeroes in B.
- movs B_1, B_0, lsl #16
- addeq D_0, #16
- moveq B_0, B_0, lsr #16
- tst B_0, #0xff
- addeq D_0, #8
- moveq B_0, B_0, lsr #8
- tst B_0, #0xf
- addeq D_0, #4
- moveq B_0, B_0, lsr #4
- tst B_0, #0x3
- addeq D_0, #2
- moveq B_0, B_0, lsr #2
- tst B_0, #0x1
- addeq D_0, #1
- @ Shift A to the right by the appropriate amount.
- rsb D_1, D_0, #32
- mov Q_0, A_0, lsr D_0
- orr Q_0, A_1, lsl D_1
- mov Q_1, A_1, lsr D_0
- @ Move C to R
- mov R_0, C_0
- mov R_1, C_1
- ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-#endif
-
-L_div_by_0:
- bl __div0
- @ As wrong as it could be
- mov Q_0, #0
- mov Q_1, #0
- mov R_0, #0
- mov R_1, #0
- ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-ENDPROC(__aeabi_uldivmod)
+++ /dev/null
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-/* # 145 "libgcc1.S" */
-dividend .req r0
-divisor .req r1
-overdone .req r2
-curbit .req r3
-/* ip .req r12 */
-/* sp .req r13 */
-/* lr .req r14 */
-/* pc .req r15 */
- .text
- .type __umodsi3 ,function
- .align 0
- ENTRY(__umodsi3)
- cmp divisor, #0
- beq Ldiv0
- mov curbit, #1
- cmp dividend, divisor
- movcc pc, lr
-Loop1:
- @ Unless the divisor is very big, shift it up in multiples of
- @ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
- @ larger than the dividend.
- cmp divisor, #0x10000000
- cmpcc divisor, dividend
- movcc divisor, divisor, lsl #4
- movcc curbit, curbit, lsl #4
- bcc Loop1
-Lbignum:
- @ For very big divisors, we must shift it a bit at a time, or
- @ we will be in danger of overflowing.
- cmp divisor, #0x80000000
- cmpcc divisor, dividend
- movcc divisor, divisor, lsl #1
- movcc curbit, curbit, lsl #1
- bcc Lbignum
-Loop3:
- @ Test for possible subtractions. On the final pass, this may
- @ subtract too much from the dividend, so keep track of which
- @ subtractions are done, we can fix them up afterwards...
- mov overdone, #0
- cmp dividend, divisor
- subcs dividend, dividend, divisor
- cmp dividend, divisor, lsr #1
- subcs dividend, dividend, divisor, lsr #1
- orrcs overdone, overdone, curbit, ror #1
- cmp dividend, divisor, lsr #2
- subcs dividend, dividend, divisor, lsr #2
- orrcs overdone, overdone, curbit, ror #2
- cmp dividend, divisor, lsr #3
- subcs dividend, dividend, divisor, lsr #3
- orrcs overdone, overdone, curbit, ror #3
- mov ip, curbit
- cmp dividend, #0 @ Early termination?
- movnes curbit, curbit, lsr #4 @ No, any more bits to do?
- movne divisor, divisor, lsr #4
- bne Loop3
- @ Any subtractions that we should not have done will be recorded in
- @ the top three bits of "overdone". Exactly which were not needed
- @ are governed by the position of the bit, stored in ip.
- @ If we terminated early, because dividend became zero,
- @ then none of the below will match, since the bit in ip will not be
- @ in the bottom nibble.
- ands overdone, overdone, #0xe0000000
- moveq pc, lr @ No fixups needed
- tst overdone, ip, ror #3
- addne dividend, dividend, divisor, lsr #3
- tst overdone, ip, ror #2
- addne dividend, dividend, divisor, lsr #2
- tst overdone, ip, ror #1
- addne dividend, dividend, divisor, lsr #1
- mov pc, lr
-Ldiv0:
- str lr, [sp, #-4]!
- bl __div0 (PLT)
- mov r0, #0 @ about as wrong as it could be
- ldmia sp!, {pc}
- .size __umodsi3 , . - __umodsi3
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */
-ENDPROC(__umodsi3)
--- /dev/null
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+ Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.pushsection .text.__ashldi3, "ax"
+ENTRY(__ashldi3)
+ENTRY(__aeabi_llsl)
+
+ subs r3, r2, #32
+ rsb ip, r2, #32
+ movmi ah, ah, lsl r2
+ movpl ah, al, lsl r3
+ ARM( orrmi ah, ah, al, lsr ip )
+ THUMB( lsrmi r3, al, ip )
+ THUMB( orrmi ah, ah, r3 )
+ mov al, al, lsl r2
+ ret lr
+
+ENDPROC(__ashldi3)
+ENDPROC(__aeabi_llsl)
+.popsection
--- /dev/null
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+ Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.pushsection .text.__ashrdi3, "ax"
+ENTRY(__ashrdi3)
+ENTRY(__aeabi_lasr)
+
+ subs r3, r2, #32
+ rsb ip, r2, #32
+ movmi al, al, lsr r2
+ movpl al, ah, asr r3
+ ARM( orrmi al, al, ah, lsl ip )
+ THUMB( lslmi r3, ah, ip )
+ THUMB( orrmi al, al, r3 )
+ mov ah, ah, asr r2
+ ret lr
+
+ENDPROC(__ashrdi3)
+ENDPROC(__aeabi_lasr)
+.popsection
--- /dev/null
+/*
+ * linux/arch/arm/lib/div64.S
+ *
+ * Optimized computation of 64-bit dividend / 32-bit divisor
+ *
+ * Author: Nicolas Pitre
+ * Created: Oct 5, 2003
+ * Copyright: Monta Vista Software, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#ifdef __UBOOT__
+#define UNWIND(x...)
+#endif
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+/*
+ * __do_div64: perform a division with 64-bit dividend and 32-bit divisor.
+ *
+ * Note: Calling convention is totally non standard for optimal code.
+ * This is meant to be used by do_div() from include/asm/div64.h only.
+ *
+ * Input parameters:
+ * xh-xl = dividend (clobbered)
+ * r4 = divisor (preserved)
+ *
+ * Output values:
+ * yh-yl = result
+ * xh = remainder
+ *
+ * Clobbered regs: xl, ip
+ */
+
+.pushsection .text.__do_div64, "ax"
+ENTRY(__do_div64)
+UNWIND(.fnstart)
+
+ @ Test for easy paths first.
+ subs ip, r4, #1
+ bls 9f @ divisor is 0 or 1
+ tst ip, r4
+ beq 8f @ divisor is power of 2
+
+ @ See if we need to handle upper 32-bit result.
+ cmp xh, r4
+ mov yh, #0
+ blo 3f
+
+ @ Align divisor with upper part of dividend.
+ @ The aligned divisor is stored in yl preserving the original.
+ @ The bit position is stored in ip.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz yl, r4
+ clz ip, xh
+ sub yl, yl, ip
+ mov ip, #1
+ mov ip, ip, lsl yl
+ mov yl, r4, lsl yl
+
+#else
+
+ mov yl, r4
+ mov ip, #1
+1: cmp yl, #0x80000000
+ cmpcc yl, xh
+ movcc yl, yl, lsl #1
+ movcc ip, ip, lsl #1
+ bcc 1b
+
+#endif
+
+ @ The division loop for needed upper bit positions.
+ @ Break out early if dividend reaches 0.
+2: cmp xh, yl
+ orrcs yh, yh, ip
+ subscs xh, xh, yl
+ movsne ip, ip, lsr #1
+ mov yl, yl, lsr #1
+ bne 2b
+
+ @ See if we need to handle lower 32-bit result.
+3: cmp xh, #0
+ mov yl, #0
+ cmpeq xl, r4
+ movlo xh, xl
+ retlo lr
+
+ @ The division loop for lower bit positions.
+ @ Here we shift remainer bits leftwards rather than moving the
+ @ divisor for comparisons, considering the carry-out bit as well.
+ mov ip, #0x80000000
+4: movs xl, xl, lsl #1
+ adcs xh, xh, xh
+ beq 6f
+ cmpcc xh, r4
+5: orrcs yl, yl, ip
+ subcs xh, xh, r4
+ movs ip, ip, lsr #1
+ bne 4b
+ ret lr
+
+ @ The top part of remainder became zero. If carry is set
+ @ (the 33th bit) this is a false positive so resume the loop.
+ @ Otherwise, if lower part is also null then we are done.
+6: bcs 5b
+ cmp xl, #0
+ reteq lr
+
+ @ We still have remainer bits in the low part. Bring them up.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz xh, xl @ we know xh is zero here so...
+ add xh, xh, #1
+ mov xl, xl, lsl xh
+ mov ip, ip, lsr xh
+
+#else
+
+7: movs xl, xl, lsl #1
+ mov ip, ip, lsr #1
+ bcc 7b
+
+#endif
+
+ @ Current remainder is now 1. It is worthless to compare with
+ @ divisor at this point since divisor can not be smaller than 3 here.
+ @ If possible, branch for another shift in the division loop.
+ @ If no bit position left then we are done.
+ movs ip, ip, lsr #1
+ mov xh, #1
+ bne 4b
+ ret lr
+
+8: @ Division by a power of 2: determine what that divisor order is
+ @ then simply shift values around
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz ip, r4
+ rsb ip, ip, #31
+
+#else
+
+ mov yl, r4
+ cmp r4, #(1 << 16)
+ mov ip, #0
+ movhs yl, yl, lsr #16
+ movhs ip, #16
+
+ cmp yl, #(1 << 8)
+ movhs yl, yl, lsr #8
+ addhs ip, ip, #8
+
+ cmp yl, #(1 << 4)
+ movhs yl, yl, lsr #4
+ addhs ip, ip, #4
+
+ cmp yl, #(1 << 2)
+ addhi ip, ip, #3
+ addls ip, ip, yl, lsr #1
+
+#endif
+
+ mov yh, xh, lsr ip
+ mov yl, xl, lsr ip
+ rsb ip, ip, #32
+ ARM( orr yl, yl, xh, lsl ip )
+ THUMB( lsl xh, xh, ip )
+ THUMB( orr yl, yl, xh )
+ mov xh, xl, lsl ip
+ mov xh, xh, lsr ip
+ ret lr
+
+ @ eq -> division by 1: obvious enough...
+9: moveq yl, xl
+ moveq yh, xh
+ moveq xh, #0
+ reteq lr
+UNWIND(.fnend)
+
+UNWIND(.fnstart)
+UNWIND(.pad #4)
+UNWIND(.save {lr})
+Ldiv0_64:
+ @ Division by 0:
+ str lr, [sp, #-8]!
+ bl __div0
+
+ @ as wrong as it could be...
+ mov yl, #0
+ mov yh, #0
+ mov xh, #0
+ ldr pc, [sp], #8
+
+UNWIND(.fnend)
+ENDPROC(__do_div64)
+.popsection
--- /dev/null
+/*
+ * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
+ *
+ * Author: Nicolas Pitre <nico@fluxnic.net>
+ * - contributed to gcc-3.4 on Sep 30, 2003
+ * - adapted for the Linux kernel on Oct 2, 2003
+ */
+
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * U-Boot compatibility bit, define empty UNWIND() macro as, since we
+ * do not support stack unwinding and define CONFIG_AEABI to make all
+ * of the functions available without diverging from Linux code.
+ */
+#ifdef __UBOOT__
+#define UNWIND(x...)
+#define CONFIG_AEABI
+#endif
+
+.macro ARM_DIV_BODY dividend, divisor, result, curbit
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz \curbit, \divisor
+ clz \result, \dividend
+ sub \result, \curbit, \result
+ mov \curbit, #1
+ mov \divisor, \divisor, lsl \result
+ mov \curbit, \curbit, lsl \result
+ mov \result, #0
+
+#else
+
+ @ Initially shift the divisor left 3 bits if possible,
+ @ set curbit accordingly. This allows for curbit to be located
+ @ at the left end of each 4 bit nibbles in the division loop
+ @ to save one loop in most cases.
+ tst \divisor, #0xe0000000
+ moveq \divisor, \divisor, lsl #3
+ moveq \curbit, #8
+ movne \curbit, #1
+
+ @ Unless the divisor is very big, shift it up in multiples of
+ @ four bits, since this is the amount of unwinding in the main
+ @ division loop. Continue shifting until the divisor is
+ @ larger than the dividend.
+1: cmp \divisor, #0x10000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #4
+ movlo \curbit, \curbit, lsl #4
+ blo 1b
+
+ @ For very big divisors, we must shift it a bit at a time, or
+ @ we will be in danger of overflowing.
+1: cmp \divisor, #0x80000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #1
+ movlo \curbit, \curbit, lsl #1
+ blo 1b
+
+ mov \result, #0
+
+#endif
+
+ @ Division loop
+1: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ orrhs \result, \result, \curbit
+ cmp \dividend, \divisor, lsr #1
+ subhs \dividend, \dividend, \divisor, lsr #1
+ orrhs \result, \result, \curbit, lsr #1
+ cmp \dividend, \divisor, lsr #2
+ subhs \dividend, \dividend, \divisor, lsr #2
+ orrhs \result, \result, \curbit, lsr #2
+ cmp \dividend, \divisor, lsr #3
+ subhs \dividend, \dividend, \divisor, lsr #3
+ orrhs \result, \result, \curbit, lsr #3
+ cmp \dividend, #0 @ Early termination?
+ movsne \curbit, \curbit, lsr #4 @ No, any more bits to do?
+ movne \divisor, \divisor, lsr #4
+ bne 1b
+
+.endm
+
+
+.macro ARM_DIV2_ORDER divisor, order
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz \order, \divisor
+ rsb \order, \order, #31
+
+#else
+
+ cmp \divisor, #(1 << 16)
+ movhs \divisor, \divisor, lsr #16
+ movhs \order, #16
+ movlo \order, #0
+
+ cmp \divisor, #(1 << 8)
+ movhs \divisor, \divisor, lsr #8
+ addhs \order, \order, #8
+
+ cmp \divisor, #(1 << 4)
+ movhs \divisor, \divisor, lsr #4
+ addhs \order, \order, #4
+
+ cmp \divisor, #(1 << 2)
+ addhi \order, \order, #3
+ addls \order, \order, \divisor, lsr #1
+
+#endif
+
+.endm
+
+
+.macro ARM_MOD_BODY dividend, divisor, order, spare
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz \order, \divisor
+ clz \spare, \dividend
+ sub \order, \order, \spare
+ mov \divisor, \divisor, lsl \order
+
+#else
+
+ mov \order, #0
+
+ @ Unless the divisor is very big, shift it up in multiples of
+ @ four bits, since this is the amount of unwinding in the main
+ @ division loop. Continue shifting until the divisor is
+ @ larger than the dividend.
+1: cmp \divisor, #0x10000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #4
+ addlo \order, \order, #4
+ blo 1b
+
+ @ For very big divisors, we must shift it a bit at a time, or
+ @ we will be in danger of overflowing.
+1: cmp \divisor, #0x80000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #1
+ addlo \order, \order, #1
+ blo 1b
+
+#endif
+
+ @ Perform all needed subtractions to keep only the reminder.
+ @ Do comparisons in batch of 4 first.
+ subs \order, \order, #3 @ yes, 3 is intended here
+ blt 2f
+
+1: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ cmp \dividend, \divisor, lsr #1
+ subhs \dividend, \dividend, \divisor, lsr #1
+ cmp \dividend, \divisor, lsr #2
+ subhs \dividend, \dividend, \divisor, lsr #2
+ cmp \dividend, \divisor, lsr #3
+ subhs \dividend, \dividend, \divisor, lsr #3
+ cmp \dividend, #1
+ mov \divisor, \divisor, lsr #4
+ subsge \order, \order, #4
+ bge 1b
+
+ tst \order, #3
+ teqne \dividend, #0
+ beq 5f
+
+ @ Either 1, 2 or 3 comparison/subtractions are left.
+2: cmn \order, #2
+ blt 4f
+ beq 3f
+ cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ mov \divisor, \divisor, lsr #1
+3: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ mov \divisor, \divisor, lsr #1
+4: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+5:
+.endm
+
+
+.pushsection .text.__udivsi3, "ax"
+ENTRY(__udivsi3)
+ENTRY(__aeabi_uidiv)
+UNWIND(.fnstart)
+
+ subs r2, r1, #1
+ reteq lr
+ bcc Ldiv0
+ cmp r0, r1
+ bls 11f
+ tst r1, r2
+ beq 12f
+
+ ARM_DIV_BODY r0, r1, r2, r3
+
+ mov r0, r2
+ ret lr
+
+11: moveq r0, #1
+ movne r0, #0
+ ret lr
+
+12: ARM_DIV2_ORDER r1, r2
+
+ mov r0, r0, lsr r2
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__udivsi3)
+ENDPROC(__aeabi_uidiv)
+.popsection
+
+.pushsection .text.__umodsi3, "ax"
+ENTRY(__umodsi3)
+UNWIND(.fnstart)
+
+ subs r2, r1, #1 @ compare divisor with 1
+ bcc Ldiv0
+ cmpne r0, r1 @ compare dividend with divisor
+ moveq r0, #0
+ tsthi r1, r2 @ see if divisor is power of 2
+ andeq r0, r0, r2
+ retls lr
+
+ ARM_MOD_BODY r0, r1, r2, r3
+
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__umodsi3)
+.popsection
+
+.pushsection .text.__divsi3, "ax"
+ENTRY(__divsi3)
+ENTRY(__aeabi_idiv)
+UNWIND(.fnstart)
+
+ cmp r1, #0
+ eor ip, r0, r1 @ save the sign of the result.
+ beq Ldiv0
+ rsbmi r1, r1, #0 @ loops below use unsigned.
+ subs r2, r1, #1 @ division by 1 or -1 ?
+ beq 10f
+ movs r3, r0
+ rsbmi r3, r0, #0 @ positive dividend value
+ cmp r3, r1
+ bls 11f
+ tst r1, r2 @ divisor is power of 2 ?
+ beq 12f
+
+ ARM_DIV_BODY r3, r1, r0, r2
+
+ cmp ip, #0
+ rsbmi r0, r0, #0
+ ret lr
+
+10: teq ip, r0 @ same sign ?
+ rsbmi r0, r0, #0
+ ret lr
+
+11: movlo r0, #0
+ moveq r0, ip, asr #31
+ orreq r0, r0, #1
+ ret lr
+
+12: ARM_DIV2_ORDER r1, r2
+
+ cmp ip, #0
+ mov r0, r3, lsr r2
+ rsbmi r0, r0, #0
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__divsi3)
+ENDPROC(__aeabi_idiv)
+.popsection
+
+.pushsection .text.__modsi3, "ax"
+ENTRY(__modsi3)
+UNWIND(.fnstart)
+
+ cmp r1, #0
+ beq Ldiv0
+ rsbmi r1, r1, #0 @ loops below use unsigned.
+ movs ip, r0 @ preserve sign of dividend
+ rsbmi r0, r0, #0 @ if negative make positive
+ subs r2, r1, #1 @ compare divisor with 1
+ cmpne r0, r1 @ compare dividend with divisor
+ moveq r0, #0
+ tsthi r1, r2 @ see if divisor is power of 2
+ andeq r0, r0, r2
+ bls 10f
+
+ ARM_MOD_BODY r0, r1, r2, r3
+
+10: cmp ip, #0
+ rsbmi r0, r0, #0
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__modsi3)
+.popsection
+
+#ifdef CONFIG_AEABI
+
+.pushsection .text.__aeabi_uidivmod, "ax"
+ENTRY(__aeabi_uidivmod)
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr} )
+
+ stmfd sp!, {r0, r1, ip, lr}
+ bl __aeabi_uidiv
+ ldmfd sp!, {r1, r2, ip, lr}
+ mul r3, r0, r2
+ sub r1, r1, r3
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__aeabi_uidivmod)
+.popsection
+
+.pushsection .text.__aeabi_uidivmod, "ax"
+ENTRY(__aeabi_idivmod)
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr} )
+
+ stmfd sp!, {r0, r1, ip, lr}
+ bl __aeabi_idiv
+ ldmfd sp!, {r1, r2, ip, lr}
+ mul r3, r0, r2
+ sub r1, r1, r3
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__aeabi_idivmod)
+.popsection
+
+#endif
+
+.pushsection .text.Ldiv0, "ax"
+Ldiv0:
+UNWIND(.fnstart)
+UNWIND(.pad #4)
+UNWIND(.save {lr})
+
+ str lr, [sp, #-8]!
+ bl __div0
+ mov r0, #0 @ About as wrong as it could be.
+ ldr pc, [sp], #8
+
+UNWIND(.fnend)
+ENDPROC(Ldiv0)
+.popsection
+
+.pushsection .text.__gnu_thumb1_case_sqi, "ax"
+/* Thumb-1 specialities */
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
+ENTRY(__gnu_thumb1_case_sqi)
+ push {r1}
+ mov r1, lr
+ lsrs r1, r1, #1
+ lsls r1, r1, #1
+ ldrsb r1, [r1, r0]
+ lsls r1, r1, #1
+ add lr, lr, r1
+ pop {r1}
+ bx lr
+ENDPROC(__gnu_thumb1_case_sqi)
+.popsection
+
+_.pushsection .text.__gnu_thumb1_case_uqi, "ax"
+ENTRY(__gnu_thumb1_case_uqi)
+ push {r1}
+ mov r1, lr
+ lsrs r1, r1, #1
+ lsls r1, r1, #1
+ ldrb r1, [r1, r0]
+ lsls r1, r1, #1
+ add lr, lr, r1
+ pop {r1}
+ bx lr
+ENDPROC(__gnu_thumb1_case_uqi)
+.popsection
+
+.pushsection .text.__gnu_thumb1_case_shi, "ax"
+ENTRY(__gnu_thumb1_case_shi)
+ push {r0, r1}
+ mov r1, lr
+ lsrs r1, r1, #1
+ lsls r0, r0, #1
+ lsls r1, r1, #1
+ ldrsh r1, [r1, r0]
+ lsls r1, r1, #1
+ add lr, lr, r1
+ pop {r0, r1}
+ bx lr
+ENDPROC(__gnu_thumb1_case_shi)
+.popsection
+
+.pushsection .text.__gnu_thumb1_case_uhi, "ax"
+ENTRY(__gnu_thumb1_case_uhi)
+ push {r0, r1}
+ mov r1, lr
+ lsrs r1, r1, #1
+ lsls r0, r0, #1
+ lsls r1, r1, #1
+ ldrh r1, [r1, r0]
+ lsls r1, r1, #1
+ add lr, lr, r1
+ pop {r0, r1}
+ bx lr
+ENDPROC(__gnu_thumb1_case_uhi)
+.popsection
+#endif
--- /dev/null
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+ Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.pushsection .text.__lshldi3, "ax"
+ENTRY(__lshrdi3)
+ENTRY(__aeabi_llsr)
+
+ subs r3, r2, #32
+ rsb ip, r2, #32
+ movmi al, al, lsr r2
+ movpl al, ah, lsr r3
+ ARM( orrmi al, al, ah, lsl ip )
+ THUMB( lslmi r3, ah, ip )
+ THUMB( orrmi al, al, r3 )
+ mov ah, ah, lsr r2
+ ret lr
+
+ENDPROC(__lshrdi3)
+ENDPROC(__aeabi_llsr)
+.popsection
#include <linux/linkage.h>
#include <asm/assembler.h>
-#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
-#define W(instr) instr.w
-#else
-#define W(instr) instr
-#endif
-
#define LDR1W_SHIFT 0
#define STR1W_SHIFT 0
--- /dev/null
+/*
+ * linux/arch/arm/lib/muldi3.S
+ *
+ * Author: Nicolas Pitre
+ * Created: Oct 19, 2005
+ * Copyright: Monta Vista Software, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+.pushsection .text.__muldi3, "ax"
+ENTRY(__muldi3)
+ENTRY(__aeabi_lmul)
+
+ mul xh, yl, xh
+ mla xh, xl, yh, xh
+ mov ip, xl, lsr #16
+ mov yh, yl, lsr #16
+ bic xl, xl, ip, lsl #16
+ bic yl, yl, yh, lsl #16
+ mla xh, yh, ip, xh
+ mul yh, xl, yh
+ mul xl, yl, xl
+ mul ip, yl, ip
+ adds xl, xl, yh, lsl #16
+ adc xh, xh, yh, lsr #16
+ adds xl, xl, ip, lsl #16
+ adc xh, xh, ip, lsr #16
+ ret lr
+
+ENDPROC(__muldi3)
+ENDPROC(__aeabi_lmul)
+.popsection
--- /dev/null
+/*
+ * Copyright 2010, Google Inc.
+ *
+ * Brought in from coreboot uldivmod.S
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * A, Q = r0 + (r1 << 32)
+ * B, R = r2 + (r3 << 32)
+ * A / B = Q ... R
+ */
+
+A_0 .req r0
+A_1 .req r1
+B_0 .req r2
+B_1 .req r3
+C_0 .req r4
+C_1 .req r5
+D_0 .req r6
+D_1 .req r7
+
+Q_0 .req r0
+Q_1 .req r1
+R_0 .req r2
+R_1 .req r3
+
+THUMB(
+TMP .req r8
+)
+
+.pushsection .text.__aeabi_uldivmod, "ax"
+ENTRY(__aeabi_uldivmod)
+
+ stmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
+ @ Test if B == 0
+ orrs ip, B_0, B_1 @ Z set -> B == 0
+ beq L_div_by_0
+ @ Test if B is power of 2: (B & (B - 1)) == 0
+ subs C_0, B_0, #1
+ sbc C_1, B_1, #0
+ tst C_0, B_0
+ tsteq B_1, C_1
+ beq L_pow2
+ @ Test if A_1 == B_1 == 0
+ orrs ip, A_1, B_1
+ beq L_div_32_32
+
+L_div_64_64:
+/* CLZ only exists in ARM architecture version 5 and above. */
+#ifdef HAVE_CLZ
+ mov C_0, #1
+ mov C_1, #0
+ @ D_0 = clz A
+ teq A_1, #0
+ clz D_0, A_1
+ clzeq ip, A_0
+ addeq D_0, D_0, ip
+ @ D_1 = clz B
+ teq B_1, #0
+ clz D_1, B_1
+ clzeq ip, B_0
+ addeq D_1, D_1, ip
+ @ if clz B - clz A > 0
+ subs D_0, D_1, D_0
+ bls L_done_shift
+ @ B <<= (clz B - clz A)
+ subs D_1, D_0, #32
+ rsb ip, D_0, #32
+ movmi B_1, B_1, lsl D_0
+ARM( orrmi B_1, B_1, B_0, lsr ip )
+THUMB( lsrmi TMP, B_0, ip )
+THUMB( orrmi B_1, B_1, TMP )
+ movpl B_1, B_0, lsl D_1
+ mov B_0, B_0, lsl D_0
+ @ C = 1 << (clz B - clz A)
+ movmi C_1, C_1, lsl D_0
+ARM( orrmi C_1, C_1, C_0, lsr ip )
+THUMB( lsrmi TMP, C_0, ip )
+THUMB( orrmi C_1, C_1, TMP )
+ movpl C_1, C_0, lsl D_1
+ mov C_0, C_0, lsl D_0
+L_done_shift:
+ mov D_0, #0
+ mov D_1, #0
+ @ C: current bit; D: result
+#else
+ @ C: current bit; D: result
+ mov C_0, #1
+ mov C_1, #0
+ mov D_0, #0
+ mov D_1, #0
+L_lsl_4:
+ cmp B_1, #0x10000000
+ cmpcc B_1, A_1
+ cmpeq B_0, A_0
+ bcs L_lsl_1
+ @ B <<= 4
+ mov B_1, B_1, lsl #4
+ orr B_1, B_1, B_0, lsr #28
+ mov B_0, B_0, lsl #4
+ @ C <<= 4
+ mov C_1, C_1, lsl #4
+ orr C_1, C_1, C_0, lsr #28
+ mov C_0, C_0, lsl #4
+ b L_lsl_4
+L_lsl_1:
+ cmp B_1, #0x80000000
+ cmpcc B_1, A_1
+ cmpeq B_0, A_0
+ bcs L_subtract
+ @ B <<= 1
+ mov B_1, B_1, lsl #1
+ orr B_1, B_1, B_0, lsr #31
+ mov B_0, B_0, lsl #1
+ @ C <<= 1
+ mov C_1, C_1, lsl #1
+ orr C_1, C_1, C_0, lsr #31
+ mov C_0, C_0, lsl #1
+ b L_lsl_1
+#endif
+L_subtract:
+ @ if A >= B
+ cmp A_1, B_1
+ cmpeq A_0, B_0
+ bcc L_update
+ @ A -= B
+ subs A_0, A_0, B_0
+ sbc A_1, A_1, B_1
+ @ D |= C
+ orr D_0, D_0, C_0
+ orr D_1, D_1, C_1
+L_update:
+ @ if A == 0: break
+ orrs ip, A_1, A_0
+ beq L_exit
+ @ C >>= 1
+ movs C_1, C_1, lsr #1
+ movs C_0, C_0, rrx
+ @ if C == 0: break
+ orrs ip, C_1, C_0
+ beq L_exit
+ @ B >>= 1
+ movs B_1, B_1, lsr #1
+ mov B_0, B_0, rrx
+ b L_subtract
+L_exit:
+ @ Note: A, B & Q, R are aliases
+ mov R_0, A_0
+ mov R_1, A_1
+ mov Q_0, D_0
+ mov Q_1, D_1
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+
+L_div_32_32:
+ @ Note: A_0 & r0 are aliases
+ @ Q_1 r1
+ mov r1, B_0
+ bl __aeabi_uidivmod
+ mov R_0, r1
+ mov R_1, #0
+ mov Q_1, #0
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+
+L_pow2:
+#ifdef HAVE_CLZ
+ @ Note: A, B and Q, R are aliases
+ @ R = A & (B - 1)
+ and C_0, A_0, C_0
+ and C_1, A_1, C_1
+ @ Q = A >> log2(B)
+ @ Note: B must not be 0 here!
+ clz D_0, B_0
+ add D_1, D_0, #1
+ rsbs D_0, D_0, #31
+ bpl L_1
+ clz D_0, B_1
+ rsb D_0, D_0, #31
+ mov A_0, A_1, lsr D_0
+ add D_0, D_0, #32
+L_1:
+ movpl A_0, A_0, lsr D_0
+ARM( orrpl A_0, A_0, A_1, lsl D_1 )
+THUMB( lslpl TMP, A_1, D_1 )
+THUMB( orrpl A_0, A_0, TMP )
+ mov A_1, A_1, lsr D_0
+ @ Mov back C to R
+ mov R_0, C_0
+ mov R_1, C_1
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+#else
+ @ Note: A, B and Q, R are aliases
+ @ R = A & (B - 1)
+ and C_0, A_0, C_0
+ and C_1, A_1, C_1
+ @ Q = A >> log2(B)
+ @ Note: B must not be 0 here!
+ @ Count the leading zeroes in B.
+ mov D_0, #0
+ orrs B_0, B_0, B_0
+ @ If B is greater than 1 << 31, divide A and B by 1 << 32.
+ moveq A_0, A_1
+ moveq A_1, #0
+ moveq B_0, B_1
+ @ Count the remaining leading zeroes in B.
+ movs B_1, B_0, lsl #16
+ addeq D_0, #16
+ moveq B_0, B_0, lsr #16
+ tst B_0, #0xff
+ addeq D_0, #8
+ moveq B_0, B_0, lsr #8
+ tst B_0, #0xf
+ addeq D_0, #4
+ moveq B_0, B_0, lsr #4
+ tst B_0, #0x3
+ addeq D_0, #2
+ moveq B_0, B_0, lsr #2
+ tst B_0, #0x1
+ addeq D_0, #1
+ @ Shift A to the right by the appropriate amount.
+ rsb D_1, D_0, #32
+ mov Q_0, A_0, lsr D_0
+ ARM( orr Q_0, Q_0, A_1, lsl D_1 )
+ THUMB( lsl A_1, D_1 )
+ THUMB( orr Q_0, A_1 )
+ mov Q_1, A_1, lsr D_0
+ @ Move C to R
+ mov R_0, C_0
+ mov R_1, C_1
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+#endif
+
+L_div_by_0:
+ bl __div0
+ @ As wrong as it could be
+ mov Q_0, #0
+ mov Q_1, #0
+ mov R_0, #0
+ mov R_1, #0
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+ENDPROC(__aeabi_uldivmod)
+.popsection
#define K2G_GPIO_DIR_OFFSET 0x0
#define K2G_GPIO_SETDATA_OFFSET 0x8
+/* BOOTCFG RESETMUX8 */
+#define KS2_RSTMUX8 (KS2_DEVICE_STATE_CTRL_BASE + 0x328)
+
+/* RESETMUX register definitions */
+#define RSTMUX_LOCK8_SHIFT 0x0
+#define RSTMUX_LOCK8_MASK (0x1 << 0)
+#define RSTMUX_OMODE8_SHIFT 0x1
+#define RSTMUX_OMODE8_MASK (0x7 << 1)
+#define RSTMUX_OMODE8_DEV_RESET 0x2
+#define RSTMUX_OMODE8_INT 0x3
+#define RSTMUX_OMODE8_INT_AND_DEV_RESET 0x4
+
#endif /* __ASM_ARCH_HARDWARE_K2G_H */
bool "EBV SoCrates (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+ bool "samtec VIN|ING FPGA (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
+ default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+ default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
select SPL
select SUPPORT_SPL
select TEGRA_COMMON
+ select TEGRA_GPIO
config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
config TEGRA210
bool "Tegra210 family"
+ select TEGRA_GPIO
+ select TEGRA_ARMV8_COMMON
+
+config TEGRA186
+ bool "Tegra186 family"
+ select TEGRA186_GPIO
select TEGRA_ARMV8_COMMON
endchoice
source "arch/arm/mach-tegra/tegra114/Kconfig"
source "arch/arm/mach-tegra/tegra124/Kconfig"
source "arch/arm/mach-tegra/tegra210/Kconfig"
+source "arch/arm/mach-tegra/tegra186/Kconfig"
endif
# SPDX-License-Identifier: GPL-2.0+
#
+ifndef CONFIG_TEGRA186
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += cpu.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
+endif
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/
obj-$(CONFIG_TEGRA124) += tegra124/
+obj-$(CONFIG_TEGRA186) += tegra186/
obj-$(CONFIG_TEGRA210) += tegra210/
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = (1.5 * 1024 * 1024 * 1024);
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+void pad_init_mmc(struct mmc_host *host)
+{
+}
+
+int board_mmc_init(bd_t *bd)
+{
+ tegra_mmc_init();
+
+ return 0;
+}
+
+int ft_system_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
--- /dev/null
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TEGRA186
+
+choice
+ prompt "Tegra186 board select"
+
+config TARGET_P2771_0000
+ bool "NVIDIA Tegra186 P2771-0000 board"
+ help
+ P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
+ combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
+ micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO
+ expansion headers.
+
+endchoice
+
+config SYS_SOC
+ default "tegra186"
+
+source "board/nvidia/p2771-0000/Kconfig"
+
+endif
--- /dev/null
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += ../arm64-mmu.o
+obj-y += ../board186.o
+obj-y += ../lowlevel_init.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o
void gpio_early_init(void)
{
/* Turn on the alive signal */
- gpio_request(GPIO_PV2, "ALIVE");
- gpio_direction_output(GPIO_PV2, 1);
+ gpio_request(TEGRA_GPIO(V, 2), "ALIVE");
+ gpio_direction_output(TEGRA_GPIO(V, 2), 1);
/* Remove the reset on the external periph */
- gpio_request(GPIO_PI4, "nRST_PERIPH");
- gpio_direction_output(GPIO_PI4, 1);
+ gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH");
+ gpio_direction_output(TEGRA_GPIO(I, 4), 1);
}
void pmu_write(uchar reg, uchar data)
pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
/* Switch the power on */
- gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
- gpio_direction_output(GPIO_PJ2, 1);
+ gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC");
+ gpio_direction_output(TEGRA_GPIO(J, 2), 1);
}
/*
#ifdef CONFIG_BOARD_EARLY_INIT_F
void gpio_early_init(void)
{
- gpio_request(GPIO_PI4, NULL);
- gpio_direction_output(GPIO_PI4, 1);
+ gpio_request(TEGRA_GPIO(I, 4), NULL);
+ gpio_direction_output(TEGRA_GPIO(I, 4), 1);
}
#endif
}
/* GPIO: PEX = 3.3V */
- err = gpio_request(GPIO_PL7, "PEX");
+ err = gpio_request(TEGRA_GPIO(L, 7), "PEX");
if (err < 0)
return err;
- gpio_direction_output(GPIO_PL7, 1);
+ gpio_direction_output(TEGRA_GPIO(L, 7), 1);
/* TPS659110: LDO2_REG = 1.05V, ACTIVE */
data[0] = 0x15;
#ifndef _PINMUX_CONFIG_E2220_1170_H_
#define _PINMUX_CONFIG_E2220_1170_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A5, IN),
- GPIO_INIT(A6, IN),
- GPIO_INIT(B4, IN),
- GPIO_INIT(E6, IN),
- GPIO_INIT(G2, OUT0),
- GPIO_INIT(G3, OUT0),
- GPIO_INIT(H0, OUT0),
- GPIO_INIT(H1, OUT0),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H3, OUT0),
- GPIO_INIT(H4, OUT0),
- GPIO_INIT(H5, IN),
- GPIO_INIT(H6, OUT0),
- GPIO_INIT(H7, OUT0),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(I3, OUT0),
- GPIO_INIT(K0, IN),
- GPIO_INIT(K1, OUT0),
- GPIO_INIT(K2, OUT0),
- GPIO_INIT(K3, OUT0),
- GPIO_INIT(K4, IN),
- GPIO_INIT(K5, OUT0),
- GPIO_INIT(K6, IN),
- GPIO_INIT(K7, OUT0),
- GPIO_INIT(L0, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S5, OUT0),
- GPIO_INIT(S6, OUT0),
- GPIO_INIT(S7, OUT0),
- GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, OUT0),
- GPIO_INIT(V1, OUT0),
- GPIO_INIT(V2, OUT0),
- GPIO_INIT(V3, IN),
- GPIO_INIT(V5, OUT0),
- GPIO_INIT(V6, OUT0),
- GPIO_INIT(X0, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X2, IN),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X5, IN),
- GPIO_INIT(X6, IN),
- GPIO_INIT(X7, IN),
- GPIO_INIT(Y0, IN),
- GPIO_INIT(Y1, IN),
- GPIO_INIT(Z0, IN),
- GPIO_INIT(Z4, OUT0),
- GPIO_INIT(BB2, OUT0),
- GPIO_INIT(BB3, OUT0),
- GPIO_INIT(BB4, IN),
- GPIO_INIT(CC1, IN),
- GPIO_INIT(CC5, OUT0),
- GPIO_INIT(CC6, IN),
- GPIO_INIT(CC7, OUT0),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(A, 6, IN),
+ GPIO_INIT(B, 4, IN),
+ GPIO_INIT(E, 6, IN),
+ GPIO_INIT(G, 2, OUT0),
+ GPIO_INIT(G, 3, OUT0),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 1, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(H, 6, OUT0),
+ GPIO_INIT(H, 7, OUT0),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(I, 3, OUT0),
+ GPIO_INIT(K, 0, IN),
+ GPIO_INIT(K, 1, OUT0),
+ GPIO_INIT(K, 2, OUT0),
+ GPIO_INIT(K, 3, OUT0),
+ GPIO_INIT(K, 4, IN),
+ GPIO_INIT(K, 5, OUT0),
+ GPIO_INIT(K, 6, IN),
+ GPIO_INIT(K, 7, OUT0),
+ GPIO_INIT(L, 0, OUT0),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 5, OUT0),
+ GPIO_INIT(S, 6, OUT0),
+ GPIO_INIT(S, 7, OUT0),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(T, 1, OUT0),
+ GPIO_INIT(V, 1, OUT0),
+ GPIO_INIT(V, 2, OUT0),
+ GPIO_INIT(V, 3, IN),
+ GPIO_INIT(V, 5, OUT0),
+ GPIO_INIT(V, 6, OUT0),
+ GPIO_INIT(X, 0, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 2, IN),
+ GPIO_INIT(X, 3, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 5, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(X, 7, IN),
+ GPIO_INIT(Y, 0, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 4, OUT0),
+ GPIO_INIT(BB, 2, OUT0),
+ GPIO_INIT(BB, 3, OUT0),
+ GPIO_INIT(BB, 4, IN),
+ GPIO_INIT(CC, 1, IN),
+ GPIO_INIT(CC, 5, OUT0),
+ GPIO_INIT(CC, 6, IN),
+ GPIO_INIT(CC, 7, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
#define _PINMUX_CONFIG_JETSON_TK1_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(G0, IN),
- GPIO_INIT(G1, IN),
- GPIO_INIT(G2, IN),
- GPIO_INIT(G3, IN),
- GPIO_INIT(G4, IN),
- GPIO_INIT(H2, OUT0),
- GPIO_INIT(H4, IN),
- GPIO_INIT(H7, IN),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I6, IN),
- GPIO_INIT(J0, IN),
- GPIO_INIT(K1, OUT0),
- GPIO_INIT(K2, IN),
- GPIO_INIT(K4, OUT0),
- GPIO_INIT(K6, OUT0),
- GPIO_INIT(N7, IN),
- GPIO_INIT(O1, IN),
- GPIO_INIT(O4, IN),
- GPIO_INIT(P2, OUT0),
- GPIO_INIT(Q0, IN),
- GPIO_INIT(Q3, IN),
- GPIO_INIT(Q5, IN),
- GPIO_INIT(R0, OUT0),
- GPIO_INIT(R2, OUT0),
- GPIO_INIT(R4, IN),
- GPIO_INIT(R7, IN),
- GPIO_INIT(S7, IN),
- GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, IN),
- GPIO_INIT(U0, IN),
- GPIO_INIT(U1, IN),
- GPIO_INIT(U2, IN),
- GPIO_INIT(U3, IN),
- GPIO_INIT(U4, IN),
- GPIO_INIT(U5, IN),
- GPIO_INIT(U6, IN),
- GPIO_INIT(V0, IN),
- GPIO_INIT(V1, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X7, OUT0),
- GPIO_INIT(BB3, OUT0),
- GPIO_INIT(BB5, OUT0),
- GPIO_INIT(BB6, OUT0),
- GPIO_INIT(BB7, OUT0),
- GPIO_INIT(CC1, IN),
- GPIO_INIT(CC2, IN),
- GPIO_INIT(EE2, OUT1),
+ /* port, pin, init_val */
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(G, 1, IN),
+ GPIO_INIT(G, 2, IN),
+ GPIO_INIT(G, 3, IN),
+ GPIO_INIT(G, 4, IN),
+ GPIO_INIT(H, 2, OUT0),
+ GPIO_INIT(H, 4, IN),
+ GPIO_INIT(H, 7, IN),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 6, IN),
+ GPIO_INIT(J, 0, IN),
+ GPIO_INIT(K, 1, OUT0),
+ GPIO_INIT(K, 2, IN),
+ GPIO_INIT(K, 4, OUT0),
+ GPIO_INIT(K, 6, OUT0),
+ GPIO_INIT(N, 7, IN),
+ GPIO_INIT(O, 1, IN),
+ GPIO_INIT(O, 4, IN),
+ GPIO_INIT(P, 2, OUT0),
+ GPIO_INIT(Q, 0, IN),
+ GPIO_INIT(Q, 3, IN),
+ GPIO_INIT(Q, 5, IN),
+ GPIO_INIT(R, 0, OUT0),
+ GPIO_INIT(R, 2, OUT0),
+ GPIO_INIT(R, 4, IN),
+ GPIO_INIT(R, 7, IN),
+ GPIO_INIT(S, 7, IN),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(T, 1, IN),
+ GPIO_INIT(U, 0, IN),
+ GPIO_INIT(U, 1, IN),
+ GPIO_INIT(U, 2, IN),
+ GPIO_INIT(U, 3, IN),
+ GPIO_INIT(U, 4, IN),
+ GPIO_INIT(U, 5, IN),
+ GPIO_INIT(U, 6, IN),
+ GPIO_INIT(V, 0, IN),
+ GPIO_INIT(V, 1, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 7, OUT0),
+ GPIO_INIT(BB, 3, OUT0),
+ GPIO_INIT(BB, 5, OUT0),
+ GPIO_INIT(BB, 6, OUT0),
+ GPIO_INIT(BB, 7, OUT0),
+ GPIO_INIT(CC, 1, IN),
+ GPIO_INIT(CC, 2, IN),
+ GPIO_INIT(EE, 2, OUT1),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
int tegra_board_id(void)
{
- static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1,
- GPIO_PX4, -1};
+ static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
+ TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
+ -1};
gpio_claim_vector(vector, "board_id%d");
return gpio_get_values_as_int(vector);
#ifndef _PINMUX_CONFIG_NYAN_BIG_H_
#define _PINMUX_CONFIG_NYAN_BIG_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A0, IN),
- GPIO_INIT(C7, IN),
- GPIO_INIT(G0, IN),
- GPIO_INIT(G1, IN),
- GPIO_INIT(G2, IN),
- GPIO_INIT(G3, IN),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H4, IN),
- GPIO_INIT(H6, IN),
- GPIO_INIT(H7, OUT1),
- GPIO_INIT(I0, IN),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I5, OUT1),
- GPIO_INIT(I6, IN),
- GPIO_INIT(I7, IN),
- GPIO_INIT(J0, IN),
- GPIO_INIT(J7, IN),
- GPIO_INIT(K1, OUT0),
- GPIO_INIT(K2, IN),
- GPIO_INIT(K4, OUT0),
- GPIO_INIT(K6, OUT0),
- GPIO_INIT(K7, IN),
- GPIO_INIT(N7, IN),
- GPIO_INIT(P2, OUT0),
- GPIO_INIT(Q0, IN),
- GPIO_INIT(Q2, IN),
- GPIO_INIT(Q3, IN),
- GPIO_INIT(Q6, IN),
- GPIO_INIT(Q7, IN),
- GPIO_INIT(R0, OUT0),
- GPIO_INIT(R1, IN),
- GPIO_INIT(R4, IN),
- GPIO_INIT(R7, IN),
- GPIO_INIT(S3, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S7, IN),
- GPIO_INIT(T1, IN),
- GPIO_INIT(U4, IN),
- GPIO_INIT(U5, IN),
- GPIO_INIT(U6, IN),
- GPIO_INIT(V0, IN),
- GPIO_INIT(W3, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X7, OUT0),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 0, IN),
+ GPIO_INIT(C, 7, IN),
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(G, 1, IN),
+ GPIO_INIT(G, 2, IN),
+ GPIO_INIT(G, 3, IN),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 4, IN),
+ GPIO_INIT(H, 6, IN),
+ GPIO_INIT(H, 7, OUT1),
+ GPIO_INIT(I, 0, IN),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 5, OUT1),
+ GPIO_INIT(I, 6, IN),
+ GPIO_INIT(I, 7, IN),
+ GPIO_INIT(J, 0, IN),
+ GPIO_INIT(J, 7, IN),
+ GPIO_INIT(K, 1, OUT0),
+ GPIO_INIT(K, 2, IN),
+ GPIO_INIT(K, 4, OUT0),
+ GPIO_INIT(K, 6, OUT0),
+ GPIO_INIT(K, 7, IN),
+ GPIO_INIT(N, 7, IN),
+ GPIO_INIT(P, 2, OUT0),
+ GPIO_INIT(Q, 0, IN),
+ GPIO_INIT(Q, 2, IN),
+ GPIO_INIT(Q, 3, IN),
+ GPIO_INIT(Q, 6, IN),
+ GPIO_INIT(Q, 7, IN),
+ GPIO_INIT(R, 0, OUT0),
+ GPIO_INIT(R, 1, IN),
+ GPIO_INIT(R, 4, IN),
+ GPIO_INIT(R, 7, IN),
+ GPIO_INIT(S, 3, OUT0),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 7, IN),
+ GPIO_INIT(T, 1, IN),
+ GPIO_INIT(U, 4, IN),
+ GPIO_INIT(U, 5, IN),
+ GPIO_INIT(U, 6, IN),
+ GPIO_INIT(V, 0, IN),
+ GPIO_INIT(W, 3, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 7, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
#ifndef _PINMUX_CONFIG_P2371_0000_H_
#define _PINMUX_CONFIG_P2371_0000_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config p2371_0000_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A5, IN),
- GPIO_INIT(E4, OUT0),
- GPIO_INIT(E6, IN),
- GPIO_INIT(G0, IN),
- GPIO_INIT(G3, OUT0),
- GPIO_INIT(H0, OUT0),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H3, OUT0),
- GPIO_INIT(H4, OUT0),
- GPIO_INIT(H5, IN),
- GPIO_INIT(H6, OUT0),
- GPIO_INIT(H7, OUT0),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(I3, OUT0),
- GPIO_INIT(K4, IN),
- GPIO_INIT(K5, OUT0),
- GPIO_INIT(K6, IN),
- GPIO_INIT(K7, OUT0),
- GPIO_INIT(L0, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S5, OUT0),
- GPIO_INIT(S6, OUT0),
- GPIO_INIT(S7, OUT0),
- GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, OUT0),
- GPIO_INIT(V1, OUT0),
- GPIO_INIT(V2, OUT0),
- GPIO_INIT(V5, OUT0),
- GPIO_INIT(V6, OUT0),
- GPIO_INIT(V7, OUT1),
- GPIO_INIT(X0, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X2, IN),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X5, IN),
- GPIO_INIT(X6, IN),
- GPIO_INIT(X7, IN),
- GPIO_INIT(Y1, IN),
- GPIO_INIT(Z0, IN),
- GPIO_INIT(Z4, OUT0),
- GPIO_INIT(BB2, OUT0),
- GPIO_INIT(BB3, OUT0),
- GPIO_INIT(CC1, IN),
- GPIO_INIT(CC6, IN),
- GPIO_INIT(CC7, OUT0),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(E, 4, OUT0),
+ GPIO_INIT(E, 6, IN),
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(G, 3, OUT0),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(H, 6, OUT0),
+ GPIO_INIT(H, 7, OUT0),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(I, 3, OUT0),
+ GPIO_INIT(K, 4, IN),
+ GPIO_INIT(K, 5, OUT0),
+ GPIO_INIT(K, 6, IN),
+ GPIO_INIT(K, 7, OUT0),
+ GPIO_INIT(L, 0, OUT0),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 5, OUT0),
+ GPIO_INIT(S, 6, OUT0),
+ GPIO_INIT(S, 7, OUT0),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(T, 1, OUT0),
+ GPIO_INIT(V, 1, OUT0),
+ GPIO_INIT(V, 2, OUT0),
+ GPIO_INIT(V, 5, OUT0),
+ GPIO_INIT(V, 6, OUT0),
+ GPIO_INIT(V, 7, OUT1),
+ GPIO_INIT(X, 0, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 2, IN),
+ GPIO_INIT(X, 3, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 5, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(X, 7, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 4, OUT0),
+ GPIO_INIT(BB, 2, OUT0),
+ GPIO_INIT(BB, 3, OUT0),
+ GPIO_INIT(CC, 1, IN),
+ GPIO_INIT(CC, 6, IN),
+ GPIO_INIT(CC, 7, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
#ifndef _PINMUX_CONFIG_P2371_2180_H_
#define _PINMUX_CONFIG_P2371_2180_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A5, IN),
- GPIO_INIT(B0, IN),
- GPIO_INIT(B1, IN),
- GPIO_INIT(B2, IN),
- GPIO_INIT(B3, IN),
- GPIO_INIT(C0, IN),
- GPIO_INIT(C1, IN),
- GPIO_INIT(C2, IN),
- GPIO_INIT(C3, IN),
- GPIO_INIT(C4, IN),
- GPIO_INIT(E4, IN),
- GPIO_INIT(E5, IN),
- GPIO_INIT(E6, IN),
- GPIO_INIT(H0, OUT0),
- GPIO_INIT(H1, OUT0),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H3, OUT0),
- GPIO_INIT(H4, OUT0),
- GPIO_INIT(H5, IN),
- GPIO_INIT(H6, IN),
- GPIO_INIT(H7, IN),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(K4, IN),
- GPIO_INIT(K5, OUT0),
- GPIO_INIT(K6, IN),
- GPIO_INIT(K7, IN),
- GPIO_INIT(L1, IN),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S5, OUT0),
- GPIO_INIT(S6, OUT0),
- GPIO_INIT(S7, OUT0),
- GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, OUT0),
- GPIO_INIT(U2, IN),
- GPIO_INIT(U3, IN),
- GPIO_INIT(V1, OUT0),
- GPIO_INIT(V2, OUT0),
- GPIO_INIT(V3, IN),
- GPIO_INIT(V5, OUT0),
- GPIO_INIT(V6, OUT0),
- GPIO_INIT(X0, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X2, IN),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X5, IN),
- GPIO_INIT(X6, IN),
- GPIO_INIT(X7, IN),
- GPIO_INIT(Y0, IN),
- GPIO_INIT(Y1, IN),
- GPIO_INIT(Z0, IN),
- GPIO_INIT(Z2, IN),
- GPIO_INIT(Z3, OUT0),
- GPIO_INIT(BB0, IN),
- GPIO_INIT(BB2, OUT0),
- GPIO_INIT(BB3, IN),
- GPIO_INIT(CC1, IN),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(B, 0, IN),
+ GPIO_INIT(B, 1, IN),
+ GPIO_INIT(B, 2, IN),
+ GPIO_INIT(B, 3, IN),
+ GPIO_INIT(C, 0, IN),
+ GPIO_INIT(C, 1, IN),
+ GPIO_INIT(C, 2, IN),
+ GPIO_INIT(C, 3, IN),
+ GPIO_INIT(C, 4, IN),
+ GPIO_INIT(E, 4, IN),
+ GPIO_INIT(E, 5, IN),
+ GPIO_INIT(E, 6, IN),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 1, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(H, 6, IN),
+ GPIO_INIT(H, 7, IN),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(K, 4, IN),
+ GPIO_INIT(K, 5, OUT0),
+ GPIO_INIT(K, 6, IN),
+ GPIO_INIT(K, 7, IN),
+ GPIO_INIT(L, 1, IN),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 5, OUT0),
+ GPIO_INIT(S, 6, OUT0),
+ GPIO_INIT(S, 7, OUT0),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(T, 1, OUT0),
+ GPIO_INIT(U, 2, IN),
+ GPIO_INIT(U, 3, IN),
+ GPIO_INIT(V, 1, OUT0),
+ GPIO_INIT(V, 2, OUT0),
+ GPIO_INIT(V, 3, IN),
+ GPIO_INIT(V, 5, OUT0),
+ GPIO_INIT(V, 6, OUT0),
+ GPIO_INIT(X, 0, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 2, IN),
+ GPIO_INIT(X, 3, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 5, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(X, 7, IN),
+ GPIO_INIT(Y, 0, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 2, IN),
+ GPIO_INIT(Z, 3, OUT0),
+ GPIO_INIT(BB, 0, IN),
+ GPIO_INIT(BB, 2, OUT0),
+ GPIO_INIT(BB, 3, IN),
+ GPIO_INIT(CC, 1, IN),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
void start_cpu_fan(void)
{
/* GPIO_PE4 is PS_VDD_FAN_ENABLE */
- gpio_request(GPIO_PE4, "FAN_VDD");
- gpio_direction_output(GPIO_PE4, 1);
+ gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD");
+ gpio_direction_output(TEGRA_GPIO(E, 4), 1);
}
#ifndef _PINMUX_CONFIG_P2571_H_
#define _PINMUX_CONFIG_P2571_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config p2571_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A0, IN),
- GPIO_INIT(A5, IN),
- GPIO_INIT(D4, IN),
- GPIO_INIT(E4, OUT0),
- GPIO_INIT(G0, IN),
- GPIO_INIT(H0, OUT0),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H3, OUT0),
- GPIO_INIT(H4, OUT0),
- GPIO_INIT(H5, IN),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(V1, OUT0),
- GPIO_INIT(V6, OUT1),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X6, IN),
- GPIO_INIT(X7, IN),
- GPIO_INIT(Y1, IN),
- GPIO_INIT(Z0, IN),
- GPIO_INIT(Z4, OUT0),
- GPIO_INIT(BB2, OUT0),
- GPIO_INIT(CC1, IN),
- GPIO_INIT(CC3, IN),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 0, IN),
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(D, 4, IN),
+ GPIO_INIT(E, 4, OUT0),
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(V, 1, OUT0),
+ GPIO_INIT(V, 6, OUT1),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(X, 7, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 4, OUT0),
+ GPIO_INIT(BB, 2, OUT0),
+ GPIO_INIT(CC, 1, IN),
+ GPIO_INIT(CC, 3, IN),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
--- /dev/null
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TARGET_P2771_0000
+
+config SYS_BOARD
+ default "p2771-0000"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "p2771-0000"
+
+endif
--- /dev/null
+P2771-0000 BOARD
+M: Stephen Warren <swarren@nvidia.com>
+S: Maintained
+F: board/nvidia/p2771-0000/
+F: include/configs/p2771-0000.h
+F: configs/p2771-0000_defconfig
--- /dev/null
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += p2771-0000.o
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
void gpio_early_init_uart(void)
{
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
- gpio_request(GPIO_PI3, "uart_en");
- gpio_direction_output(GPIO_PI3, 0);
+ gpio_request(TEGRA_GPIO(I, 3), "uart_en");
+ gpio_direction_output(TEGRA_GPIO(I, 3), 0);
}
#endif
#ifndef _PINMUX_CONFIG_VENICE2_H_
#define _PINMUX_CONFIG_VENICE2_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config venice2_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A0, IN),
- GPIO_INIT(C7, IN),
- GPIO_INIT(G0, IN),
- GPIO_INIT(G1, IN),
- GPIO_INIT(G2, IN),
- GPIO_INIT(G3, IN),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H4, IN),
- GPIO_INIT(H5, OUT0),
- GPIO_INIT(H6, IN),
- GPIO_INIT(H7, OUT1),
- GPIO_INIT(I0, IN),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(I4, OUT0),
- GPIO_INIT(I5, OUT1),
- GPIO_INIT(I6, IN),
- GPIO_INIT(J0, IN),
- GPIO_INIT(J7, IN),
- GPIO_INIT(K0, IN),
- GPIO_INIT(K1, OUT0),
- GPIO_INIT(K2, IN),
- GPIO_INIT(K3, IN),
- GPIO_INIT(K4, OUT0),
- GPIO_INIT(K6, OUT0),
- GPIO_INIT(K7, IN),
- GPIO_INIT(N7, IN),
- GPIO_INIT(O2, IN),
- GPIO_INIT(O5, IN),
- GPIO_INIT(O6, OUT0),
- GPIO_INIT(O7, IN),
- GPIO_INIT(P2, OUT0),
- GPIO_INIT(Q0, IN),
- GPIO_INIT(Q2, IN),
- GPIO_INIT(Q3, IN),
- GPIO_INIT(Q6, IN),
- GPIO_INIT(Q7, IN),
- GPIO_INIT(R0, OUT0),
- GPIO_INIT(R1, IN),
- GPIO_INIT(R4, IN),
- GPIO_INIT(S0, IN),
- GPIO_INIT(S3, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S7, IN),
- GPIO_INIT(T1, IN),
- GPIO_INIT(U4, IN),
- GPIO_INIT(U5, IN),
- GPIO_INIT(U6, IN),
- GPIO_INIT(V0, IN),
- GPIO_INIT(V1, IN),
- GPIO_INIT(W3, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X7, OUT0),
- GPIO_INIT(CC5, OUT0),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 0, IN),
+ GPIO_INIT(C, 7, IN),
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(G, 1, IN),
+ GPIO_INIT(G, 2, IN),
+ GPIO_INIT(G, 3, IN),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 4, IN),
+ GPIO_INIT(H, 5, OUT0),
+ GPIO_INIT(H, 6, IN),
+ GPIO_INIT(H, 7, OUT1),
+ GPIO_INIT(I, 0, IN),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(I, 4, OUT0),
+ GPIO_INIT(I, 5, OUT1),
+ GPIO_INIT(I, 6, IN),
+ GPIO_INIT(J, 0, IN),
+ GPIO_INIT(J, 7, IN),
+ GPIO_INIT(K, 0, IN),
+ GPIO_INIT(K, 1, OUT0),
+ GPIO_INIT(K, 2, IN),
+ GPIO_INIT(K, 3, IN),
+ GPIO_INIT(K, 4, OUT0),
+ GPIO_INIT(K, 6, OUT0),
+ GPIO_INIT(K, 7, IN),
+ GPIO_INIT(N, 7, IN),
+ GPIO_INIT(O, 2, IN),
+ GPIO_INIT(O, 5, IN),
+ GPIO_INIT(O, 6, OUT0),
+ GPIO_INIT(O, 7, IN),
+ GPIO_INIT(P, 2, OUT0),
+ GPIO_INIT(Q, 0, IN),
+ GPIO_INIT(Q, 2, IN),
+ GPIO_INIT(Q, 3, IN),
+ GPIO_INIT(Q, 6, IN),
+ GPIO_INIT(Q, 7, IN),
+ GPIO_INIT(R, 0, OUT0),
+ GPIO_INIT(R, 1, IN),
+ GPIO_INIT(R, 4, IN),
+ GPIO_INIT(S, 0, IN),
+ GPIO_INIT(S, 3, OUT0),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 7, IN),
+ GPIO_INIT(T, 1, IN),
+ GPIO_INIT(U, 4, IN),
+ GPIO_INIT(U, 5, IN),
+ GPIO_INIT(U, 6, IN),
+ GPIO_INIT(V, 0, IN),
+ GPIO_INIT(V, 1, IN),
+ GPIO_INIT(W, 3, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 3, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 7, OUT0),
+ GPIO_INIT(CC, 5, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
--- /dev/null
+VINING FPGA BOARD
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: include/configs/socfpga_vining_fpga.h
+F: configs/socfpga_vining_fpga_defconfig
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o
--- /dev/null
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00018060,
+ 0x00000000,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x00018060,
+ 0x06018000,
+ 0x06000000,
+ 0x00000018,
+ 0x00006018,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x00000000,
+ 0x300C0000,
+ 0x000000C0,
+ 0x00000000,
+ 0x00000000,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0000C030,
+ 0x0300C000,
+ 0x03000000,
+ 0x0000300C,
+ 0x0000300C,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x01800000,
+ 0x00000006,
+ 0x00601806,
+ 0x00000400,
+ 0x00000000,
+ 0x00C03000,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000200,
+ 0x00601806,
+ 0x00000000,
+ 0x80600000,
+ 0x80000601,
+ 0x00000601,
+ 0x00000100,
+ 0x00300C03,
+ 0xC0300C00,
+ 0xC0300000,
+ 0xC0000300,
+ 0x000C0300,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x300C0300,
+ 0x300C0000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x000300C0,
+ 0x00008000,
+ 0x18060180,
+ 0x18060000,
+ 0x00000000,
+ 0x00000000,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x00000030,
+ 0x00000000,
+ 0x0300C030,
+ 0x00002000,
+ 0x00018060,
+ 0x06018000,
+ 0x06000000,
+ 0x00000018,
+ 0x00006018,
+ 0x00001000,
+ 0x0000C030,
+ 0x00000000,
+ 0x03000000,
+ 0x0000000C,
+ 0x00C0300C,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x0C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xE4400000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x40680A28,
+ 0x41034051,
+ 0x12481A00,
+ 0x80A280D0,
+ 0x34051406,
+ 0x01A02490,
+ 0x080D0000,
+ 0x51406802,
+ 0x02490340,
+ 0xD000001A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000FF0,
+ 0x72200000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x6A1C0000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x1A870001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x40680208,
+ 0x49034051,
+ 0x12481A02,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A00040,
+ 0x280D0002,
+ 0x5140680A,
+ 0x02490340,
+ 0xD012481A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0x7FFFFFFF,
+ 0x14F36080,
+ 0x1A041404,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0x8A28A3D5,
+ 0xF6D1451E,
+ 0x034AD348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x05140680,
+ 0xD569A47A,
+ 0x1E8A28A3,
+ 0x48F6D145,
+ 0x00035292,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00600391,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0x7FFFFFFF,
+ 0x14F36080,
+ 0x1A041404,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0x8A28A3D5,
+ 0xF4D1451E,
+ 0x034AD348,
+ 0x821A0186,
+ 0x0000D000,
+ 0x00000680,
+ 0xD569A47A,
+ 0x1EF228A3,
+ 0x48F4D145,
+ 0x00034AD3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0x7FFFFFFF,
+ 0x14F36080,
+ 0x1A041404,
+ 0x00D00000,
+ 0x0C864000,
+ 0x59647A03,
+ 0xCB2CA3DD,
+ 0xF6D9651E,
+ 0x034AD348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xDD59647A,
+ 0x1E8A28A3,
+ 0x48F6D965,
+ 0x00034AD3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0x7FFFFFFF,
+ 0x14F16080,
+ 0x1A041404,
+ 0x00D00000,
+ 0x04864000,
+ 0x69A47A01,
+ 0xF228A3D5,
+ 0xF4D1451E,
+ 0x03529248,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD559647A,
+ 0x1E8A28A3,
+ 0x48F6D145,
+ 0x00034AD3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x40002000,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x08000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x20001000,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 2, /* FLASHIO0 */
+ 2, /* FLASHIO1 */
+ 2, /* FLASHIO2 */
+ 2, /* FLASHIO3 */
+ 2, /* FLASHIO4 */
+ 2, /* FLASHIO5 */
+ 2, /* FLASHIO6 */
+ 2, /* FLASHIO7 */
+ 2, /* FLASHIO8 */
+ 2, /* FLASHIO9 */
+ 2, /* FLASHIO10 */
+ 2, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 1, /* GENERALIO3 */
+ 1, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 3, /* GENERALIO9 */
+ 3, /* GENERALIO10 */
+ 3, /* GENERALIO11 */
+ 3, /* GENERALIO12 */
+ 0, /* GENERALIO13 */
+ 0, /* GENERALIO14 */
+ 2, /* GENERALIO15 */
+ 2, /* GENERALIO16 */
+ 0, /* GENERALIO17 */
+ 0, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 2, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 1, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 1, /* SPIS1USEFPGA */
+ 1, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 488281
+#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ 0x4C
+#define RW_MGR_GUARANTEED_READ_CONT 0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7B
+#define RW_MGR_IDLE_LOOP2 0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1 0x61
+#define RW_MGR_READ_B2B_WAIT2 0x6B
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7D
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 99
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 99
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080421,
+ 0x10080520,
+ 0x10090046,
+ 0x100a0088,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080441,
+ 0x100804c0,
+ 0x100a0026,
+ 0x10090110,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_late_init(void)
+{
+ const unsigned int phy_nrst_gpio = 0;
+ const unsigned int usb_nrst_gpio = 35;
+ int ret;
+
+ status_led_set(1, STATUS_LED_ON);
+ status_led_set(2, STATUS_LED_ON);
+
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio");
+ if (!ret)
+ gpio_direction_output(phy_nrst_gpio, 1);
+ else
+ printf("Cannot remove PHY from reset!\n");
+
+ ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
+ if (!ret)
+ gpio_direction_output(usb_nrst_gpio, 1);
+ else
+ printf("Cannot remove USB from reset!\n");
+
+ mdelay(50);
+
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int misc_init_r(void)
+{
+ uchar data[128];
+ char str[32];
+ u32 serial;
+ int ret;
+
+ /* EEPROM is at bus 0. */
+ ret = i2c_set_bus_num(0);
+ if (ret) {
+ puts("Cannot select EEPROM I2C bus.\n");
+ return 0;
+ }
+
+ /* EEPROM is at address 0x50. */
+ ret = eeprom_read(0x50, 0, data, sizeof(data));
+ if (ret) {
+ puts("Cannot read I2C EEPROM.\n");
+ return 0;
+ }
+
+ /* Check EEPROM signature. */
+ if (!(data[0] == 0xa5 && data[1] == 0x5a)) {
+ puts("Invalid I2C EEPROM signature.\n");
+ setenv("unit_serial", "invalid");
+ setenv("unit_ident", "VINing-xxxx-STD");
+ setenv("hostname", "vining-invalid");
+ return 0;
+ }
+
+ /* If 'unit_serial' is already set, do nothing. */
+ if (!getenv("unit_serial")) {
+ /* This field is Big Endian ! */
+ serial = (data[0x54] << 24) | (data[0x55] << 16) |
+ (data[0x56] << 8) | (data[0x57] << 0);
+ memset(str, 0, sizeof(str));
+ sprintf(str, "%07i", serial);
+ setenv("unit_serial", str);
+ }
+
+ if (!getenv("unit_ident")) {
+ memset(str, 0, sizeof(str));
+ memcpy(str, &data[0x2e], 18);
+ setenv("unit_ident", str);
+ }
+
+ /* Set ethernet address from EEPROM. */
+ if (!getenv("ethaddr") && is_valid_ethaddr(&data[0x62]))
+ eth_setenv_enetaddr("ethaddr", &data[0x62]);
+
+ return 0;
+}
+#endif
.index = 1,
};
+int usb_gadget_handle_interrupts(int index)
+{
+ u32 status;
+
+ status = dwc3_omap_uboot_interrupt_status(index);
+ if (status)
+ dwc3_uboot_handle_interrupt(index);
+
+ return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
if (init == USB_INIT_DEVICE) {
usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+ dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+ ti_usb_phy_uboot_init(&usb_phy1_device);
+ dwc3_uboot_init(&usb_otg_ss1);
}
-
- dwc3_omap_uboot_init(&usb_otg_ss1_glue);
- ti_usb_phy_uboot_init(&usb_phy1_device);
- dwc3_uboot_init(&usb_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+ ti_usb_phy_uboot_init(&usb_phy2_device);
+ dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+ dwc3_uboot_init(&usb_otg_ss2);
}
-
- ti_usb_phy_uboot_init(&usb_phy2_device);
- dwc3_omap_uboot_init(&usb_otg_ss2_glue);
- dwc3_uboot_init(&usb_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
case 1:
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
+ if (init == USB_INIT_DEVICE) {
+ ti_usb_phy_uboot_exit(index);
+ dwc3_uboot_exit(index);
+ dwc3_omap_uboot_exit(index);
+ }
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
disable_usb_clocks(index);
return 0;
}
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#ifdef CONFIG_DRIVER_TI_CPSW
}
static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851b32,
- .sdram_config = 0x61851b32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xcccf36ab,
- .sdram_tim2 = 0x308f7fda,
- .sdram_tim3 = 0x409f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
+ .sdram_tim1 = 0xcccf36ab,
+ .sdram_tim2 = 0x308f7fda,
+ .sdram_tim3 = 0x409f88a8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
};
/* Ext phy ctrl regs 1-35 */
};
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851b32,
- .sdram_config = 0x61851b32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xcccf36b3,
- .sdram_tim2 = 0x308f7fda,
- .sdram_tim3 = 0x407f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
+ .sdram_tim1 = 0xcccf36b3,
+ .sdram_tim2 = 0x308f7fda,
+ .sdram_tim3 = 0x407f88a8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
};
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
}
struct vcores_data beagle_x15_volts = {
- .mpu.value = VDD_MPU_DRA752,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA752,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA752,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA752,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS6,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA752,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+struct vcores_data am572x_idk_volts = {
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6,
+ .gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS7,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8,
+ .iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
#ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
#endif /* CONFIG_SPL_BUILD */
+void vcores_init(void)
+{
+ if (board_is_am572x_idk())
+ *omap_vcores = &am572x_idk_volts;
+ else
+ *omap_vcores = &beagle_x15_volts;
+}
+
void hw_data_init(void)
{
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
- *omap_vcores = &beagle_x15_volts;
*ctrl = &dra7xx_ctrl;
}
.index = 1,
};
+int usb_gadget_handle_interrupts(int index)
+{
+ u32 status;
+
+ status = dwc3_omap_uboot_interrupt_status(index);
+ if (status)
+ dwc3_uboot_handle_interrupt(index);
+
+ return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
printf("port %d can't be used as device\n", index);
disable_usb_clocks(index);
return -EINVAL;
- } else {
- usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
- OTG_SS_CLKCTRL_MODULEMODE_HW |
- OPTFCLKEN_REFCLK960M);
}
-
- ti_usb_phy_uboot_init(&usb_phy1_device);
- dwc3_omap_uboot_init(&usb_otg_ss1_glue);
- dwc3_uboot_init(&usb_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
+#ifdef CONFIG_USB_DWC3
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+ ti_usb_phy_uboot_init(&usb_phy2_device);
+ dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+ dwc3_uboot_init(&usb_otg_ss2);
+#endif
} else {
printf("port %d can't be used as host\n", index);
disable_usb_clocks(index);
return -EINVAL;
}
- ti_usb_phy_uboot_init(&usb_phy2_device);
- dwc3_omap_uboot_init(&usb_otg_ss2_glue);
- dwc3_uboot_init(&usb_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
int board_usb_cleanup(int index, enum usb_init_type init)
{
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
case 1:
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
+ if (init == USB_INIT_DEVICE) {
+ ti_usb_phy_uboot_exit(index);
+ dwc3_uboot_exit(index);
+ dwc3_omap_uboot_exit(index);
+ }
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
disable_usb_clocks(index);
return 0;
}
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#ifdef CONFIG_DRIVER_TI_CPSW
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
+
+static void k2g_reset_mux_config(void)
+{
+ /* Unlock the reset mux register */
+ clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+
+ /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
+ clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
+ RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
+
+ /* lock the reset mux register to prevent any spurious writes. */
+ setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+}
+
int board_early_init_f(void)
{
init_plls();
k2g_mux_config();
+ k2g_reset_mux_config();
+
/* deassert FLASH_HOLD */
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
BIT(9));
pinmux_tristate_disable(PMUX_PINGRP_DTE);
/* Reset ASIX using LAN_RESET */
- gpio_request(GPIO_PV4, "LAN_RESET");
- gpio_direction_output(GPIO_PV4, 0);
+ gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
+ gpio_direction_output(TEGRA_GPIO(V, 4), 0);
pinmux_tristate_disable(PMUX_PINGRP_GPV);
udelay(5);
- gpio_set_value(GPIO_PV4, 1);
+ gpio_set_value(TEGRA_GPIO(V, 4), 1);
/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
pinmux_tristate_disable(PMUX_PINGRP_SPIG);
void pin_mux_usb(void)
{
/* Reset ASIX using LAN_RESET */
- gpio_request(GPIO_PDD0, "LAN_RESET");
- gpio_direction_output(GPIO_PDD0, 0);
+ gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET");
+ gpio_direction_output(TEGRA_GPIO(DD, 0), 0);
udelay(5);
- gpio_set_value(GPIO_PDD0, 1);
+ gpio_set_value(TEGRA_GPIO(DD, 0), 1);
}
debug("spl_init()\n");
#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#ifdef CONFIG_MALLOC_F_ADDR
+ gd->malloc_base = CONFIG_MALLOC_F_ADDR;
+#endif
gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
gd->malloc_ptr = 0;
#endif
#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
- if (!(gd->flags & GD_FLG_SPL_INIT))
- panic_str("spl_init must be called before heap reloc");
-
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
gd->malloc_limit = CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_LOGIC=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA186=y
+CONFIG_TARGET_P2771_0000=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Tegra186 (P2771-0000) # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_SR1500=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="samtec"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_MIPS=y
CONFIG_ARCH_ATH79=y
CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_NS16550=y
CONFIG_DM_SERIAL=y
--- /dev/null
+NVIDIA Tegra186 GPIO controllers
+
+Tegra186 contains two GPIO controllers; a main controller and an "AON"
+controller. This binding document applies to both controllers. The register
+layouts for the controllers share many similarities, but also some significant
+differences. Hence, this document describes closely related but different
+bindings and compatible values.
+
+The Tegra186 GPIO controller allows software to set the IO direction of, and
+read/write the value of, numerous GPIO signals. Routing of GPIO signals to
+package balls is under the control of a separate pin controller HW block. Two
+major sets of registers exist:
+
+a) Security registers, which allow configuration of allowed access to the GPIO
+register set. These registers exist in a single contiguous block of physical
+address space. The size of this block, and the security features available,
+varies between the different GPIO controllers.
+
+Access to this set of registers is not necessary in all circumstances. Code
+that wishes to configure access to the GPIO registers needs access to these
+registers to do so. Code which simply wishes to read or write GPIO data does not
+need access to these registers.
+
+b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
+controllers, these registers are exposed via multiple "physical aliases" in
+address space, each of which access the same underlying state. See the hardware
+documentation for rationale. Any particular GPIO client is expected to access
+just one of these physical aliases.
+
+Tegra HW documentation describes a unified naming convention for all GPIOs
+implemented by the SoC. Each GPIO is assigned to a port, and a port may control
+a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
+name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
+or GPIO_PCC3.
+
+The number of ports implemented by each GPIO controller varies. The number of
+implemented GPIOs within each port varies. GPIO registers within a controller
+are grouped and laid out according to the port they affect.
+
+The mapping from port name to the GPIO controller that implements that port, and
+the mapping from port name to register offset within a controller, are both
+extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
+describes the port-level mapping. In that file, the naming convention for ports
+matches the HW documentation. The values chosen for the names are alphabetically
+sorted within a particular controller. Drivers need to map between the DT GPIO
+IDs and HW register offsets using a lookup table.
+
+Each GPIO controller can generate a number of interrupt signals. Each signal
+represents the aggregate status for all GPIOs within a set of ports. Thus, the
+number of interrupt signals generated by a controller varies as a rough function
+of the number of ports it implements. Note that the HW documentation refers to
+both the overall controller HW module and the sets-of-ports as "controllers".
+
+Each GPIO controller in fact generates multiple interrupts signals for each set
+of ports. Each GPIO may be configured to feed into a specific one of the
+interrupt signals generated by a set-of-ports. The intent is for each generated
+signal to be routed to a different CPU, thus allowing different CPUs to each
+handle subsets of the interrupts within a port. The status of each of these
+per-port-set signals is reported via a separate register. Thus, a driver needs
+to know which status register to observe. This binding currently defines no
+configuration mechanism for this. By default, drivers should use register
+GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
+define a property to configure this.
+
+Required properties:
+- compatible
+ Array of strings.
+ One of:
+ - "nvidia,tegra186-gpio".
+ - "nvidia,tegra186-gpio-aon".
+- reg-names
+ Array of strings.
+ Contains a list of names for the register spaces described by the reg
+ property. May contain the following entries, in any order:
+ - "gpio": Mandatory. GPIO control registers. This may cover either:
+ a) The single physical alias that this OS should use.
+ b) All physical aliases that exist in the controller. This is
+ appropriate when the OS is responsible for managing assignment of
+ the physical aliases.
+ - "security": Optional. Security configuration registers.
+ Users of this binding MUST look up entries in the reg property by name,
+ using this reg-names property to do so.
+- reg
+ Array of (physical base address, length) tuples.
+ Must contain one entry per entry in the reg-names property, in a matching
+ order.
+- interrupts
+ Array of interrupt specifiers.
+ The interrupt outputs from the HW block, one per set of ports, in the
+ order the HW manual describes them. The number of entries required varies
+ depending on compatible value:
+ - "nvidia,tegra186-gpio": 6 entries.
+ - "nvidia,tegra186-gpio-aon": 1 entry.
+- gpio-controller
+ Boolean.
+ Marks the device node as a GPIO controller/provider.
+- #gpio-cells
+ Single-cell integer.
+ Must be <2>.
+ Indicates how many cells are used in a consumer's GPIO specifier.
+ In the specifier:
+ - The first cell is the pin number.
+ See <dt-bindings/gpio/tegra186-gpio.h>.
+ - The second cell contains flags:
+ - Bit 0 specifies polarity
+ - 0: Active-high (normal).
+ - 1: Active-low (inverted).
+- interrupt-controller
+ Boolean.
+ Marks the device node as an interrupt controller/provider.
+- #interrupt-cells
+ Single-cell integer.
+ Must be <2>.
+ Indicates how many cells are used in a consumer's interrupt specifier.
+ In the specifier:
+ - The first cell is the GPIO number.
+ See <dt-bindings/gpio/tegra186-gpio.h>.
+ - The second cell is contains flags:
+ - Bits [3:0] indicate trigger type and level:
+ - 1: Low-to-high edge triggered.
+ - 2: High-to-low edge triggered.
+ - 4: Active high level-sensitive.
+ - 8: Active low level-sensitive.
+ Valid combinations are 1, 2, 3, 4, 8.
+
+Example:
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+gpio@2200000 {
+ compatible = "nvidia,tegra186-gpio";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0x2200000 0x0 0x10000>,
+ <0x0 0x2210000 0x0 0x10000>;
+ interrupts =
+ <0 47 IRQ_TYPE_LEVEL_HIGH>,
+ <0 50 IRQ_TYPE_LEVEL_HIGH>,
+ <0 53 IRQ_TYPE_LEVEL_HIGH>,
+ <0 56 IRQ_TYPE_LEVEL_HIGH>,
+ <0 59 IRQ_TYPE_LEVEL_HIGH>,
+ <0 180 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+
+gpio@c2f0000 {
+ compatible = "nvidia,tegra186-gpio-aon";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0xc2f0000 0x0 0x1000>,
+ <0x0 0xc2f1000 0x0 0x1000>;
+ interrupts =
+ <0 60 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
of 'anonymous' GPIOs that do not belong to any device or bank.
Select a suitable value depending on your needs.
+config TEGRA_GPIO
+ bool "Tegra20..210 GPIO driver"
+ depends on DM_GPIO
+ help
+ Support for the GPIO controller contained in NVIDIA Tegra20 through
+ Tegra210.
+
+config TEGRA186_GPIO
+ bool "Tegra186 GPIO driver"
+ depends on DM_GPIO
+ help
+ Support for the GPIO controller contained in NVIDIA Tegra186. This
+ covers both the "main" and "AON" controller instances, even though
+ they have slightly different register layout.
+
config GPIO_UNIPHIER
bool "UniPhier GPIO"
depends on ARCH_UNIPHIER
obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
+obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o
obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
*/
#include <common.h>
-#include <netdev.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
*/
#include <common.h>
-#include <clk.h>
#include <dm.h>
#include <syscon.h>
#include <asm/errno.h>
--- /dev/null
+/*
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION.
+ * (based on tegra_gpio.c)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/gpio.h>
+#include <dm/device-internal.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "tegra186_gpio_priv.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra186_gpio_port_data {
+ const char *name;
+ uint32_t offset;
+};
+
+struct tegra186_gpio_ctlr_data {
+ const struct tegra186_gpio_port_data *ports;
+ uint32_t port_count;
+};
+
+struct tegra186_gpio_platdata {
+ const char *name;
+ uint32_t *regs;
+};
+
+static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
+ uint32_t gpio)
+{
+ struct tegra186_gpio_platdata *plat = dev->platdata;
+ uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
+
+ return &(plat->regs[index]);
+}
+
+static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset,
+ bool output)
+{
+ uint32_t *reg;
+ uint32_t rval;
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset);
+ rval = readl(reg);
+ if (output)
+ rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+ else
+ rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+ writel(rval, reg);
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+ rval = readl(reg);
+ if (output)
+ rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+ else
+ rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+ rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
+ writel(rval, reg);
+
+ return 0;
+}
+
+static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val)
+{
+ uint32_t *reg;
+ uint32_t rval;
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset);
+ rval = readl(reg);
+ if (val)
+ rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+ else
+ rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+ writel(rval, reg);
+
+ return 0;
+}
+
+static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ return tegra186_gpio_set_out(dev, offset, false);
+}
+
+static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ int ret;
+
+ ret = tegra186_gpio_set_val(dev, offset, value != 0);
+ if (ret)
+ return ret;
+ return tegra186_gpio_set_out(dev, offset, true);
+}
+
+static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ uint32_t *reg;
+ uint32_t rval;
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+ rval = readl(reg);
+
+ if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE,
+ offset);
+ else
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset);
+
+ rval = readl(reg);
+ return !!rval;
+}
+
+static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ return tegra186_gpio_set_val(dev, offset, value != 0);
+}
+
+static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ uint32_t *reg;
+ uint32_t rval;
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+ rval = readl(reg);
+ if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct fdtdec_phandle_args *args)
+{
+ int gpio, port, ret;
+
+ gpio = args->args[0];
+ port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT;
+ ret = device_get_child(dev, port, &desc->dev);
+ if (ret)
+ return ret;
+ desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT;
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops tegra186_gpio_ops = {
+ .direction_input = tegra186_gpio_direction_input,
+ .direction_output = tegra186_gpio_direction_output,
+ .get_value = tegra186_gpio_get_value,
+ .set_value = tegra186_gpio_set_value,
+ .get_function = tegra186_gpio_get_function,
+ .xlate = tegra186_gpio_xlate,
+};
+
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child device
+ * for each port within the controller.
+ */
+static int tegra186_gpio_bind(struct udevice *parent)
+{
+ struct tegra186_gpio_platdata *parent_plat = parent->platdata;
+ struct tegra186_gpio_ctlr_data *ctlr_data =
+ (struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
+ uint32_t *regs;
+ int port, ret;
+
+ /* If this is a child device, there is nothing to do here */
+ if (parent_plat)
+ return 0;
+
+ regs = (uint32_t *)dev_get_addr_name(parent, "gpio");
+ if (regs == (uint32_t *)FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ for (port = 0; port < ctlr_data->port_count; port++) {
+ struct tegra186_gpio_platdata *plat;
+ struct udevice *dev;
+
+ plat = calloc(1, sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+ plat->name = ctlr_data->ports[port].name;
+ plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
+
+ ret = device_bind(parent, parent->driver, plat->name, plat,
+ -1, &dev);
+ if (ret)
+ return ret;
+ dev->of_offset = parent->of_offset;
+ }
+
+ return 0;
+}
+
+static int tegra186_gpio_probe(struct udevice *dev)
+{
+ struct tegra186_gpio_platdata *plat = dev->platdata;
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ /* Only child devices have ports */
+ if (!plat)
+ return 0;
+
+ uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT;
+ uc_priv->bank_name = plat->name;
+
+ return 0;
+}
+
+static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = {
+ {"A", 0x2000},
+ {"B", 0x3000},
+ {"C", 0x3200},
+ {"D", 0x3400},
+ {"E", 0x2200},
+ {"F", 0x2400},
+ {"G", 0x4200},
+ {"H", 0x1000},
+ {"I", 0x0800},
+ {"J", 0x5000},
+ {"K", 0x5200},
+ {"L", 0x1200},
+ {"M", 0x5600},
+ {"N", 0x0000},
+ {"O", 0x0200},
+ {"P", 0x4000},
+ {"Q", 0x0400},
+ {"R", 0x0a00},
+ {"T", 0x0600},
+ {"X", 0x1400},
+ {"Y", 0x1600},
+ {"BB", 0x2600},
+ {"CC", 0x5400},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = {
+ .ports = tegra186_gpio_main_ports,
+ .port_count = ARRAY_SIZE(tegra186_gpio_main_ports),
+};
+
+static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = {
+ {"S", 0x0200},
+ {"U", 0x0400},
+ {"V", 0x0800},
+ {"W", 0x0a00},
+ {"Z", 0x0e00},
+ {"AA", 0x0c00},
+ {"EE", 0x0600},
+ {"FF", 0x0000},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = {
+ .ports = tegra186_gpio_aon_ports,
+ .port_count = ARRAY_SIZE(tegra186_gpio_aon_ports),
+};
+
+static const struct udevice_id tegra186_gpio_ids[] = {
+ {
+ .compatible = "nvidia,tegra186-gpio",
+ .data = (ulong)&tegra186_gpio_main_data,
+ },
+ {
+ .compatible = "nvidia,tegra186-gpio-aon",
+ .data = (ulong)&tegra186_gpio_aon_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(tegra186_gpio) = {
+ .name = "tegra186_gpio",
+ .id = UCLASS_GPIO,
+ .of_match = tegra186_gpio_ids,
+ .bind = tegra186_gpio_bind,
+ .probe = tegra186_gpio_probe,
+ .ops = &tegra186_gpio_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_PRIV_H_
+#define _TEGRA186_GPIO_PRIV_H_
+
+/*
+ * For each GPIO, there are a set of registers than affect it, all packed
+ * back-to-back.
+ */
+#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
+#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
+#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4)
+#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5)
+#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7)
+
+#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04
+
+#define TEGRA186_GPIO_INPUT 0x08
+
+#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
+#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
+
+#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
+#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1
+
+#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
+
+/*
+ * 8 GPIOs are packed into a port. Their registers appear back-to-back in the
+ * port's address space.
+ */
+#define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20
+#define TEGRA186_GPIO_PER_GPIO_COUNT 8
+
+/*
+ * Per-port registers are packed immediately following all of a port's
+ * per-GPIO registers.
+ */
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8
+
+/*
+ * The registers for multiple ports are packed together back-to-back to form
+ * the overall controller.
+ */
+#define TEGRA186_GPIO_PER_PORT_STRIDE 0x200
+
+#endif
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#ifndef CONFIG_TEGRA186
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
+#endif
#include <asm/arch-tegra/mmc.h>
#include <asm/arch-tegra/tegra_mmc.h>
#include <mmc.h>
*/
if (clock == 0)
goto out;
+#ifndef CONFIG_TEGRA186
clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
&div);
+#else
+ div = (20000000 + clock - 1) / clock;
+#endif
debug("div = %d\n", div);
writew(0, &host->reg->clkcon);
gpio_get_number(&host->cd_gpio));
host->clock = 0;
+#ifndef CONFIG_TEGRA186
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
+#endif
if (dm_gpio_is_valid(&host->pwr_gpio))
dm_gpio_set_value(&host->pwr_gpio, 1);
* (actually 52MHz)
*/
host->cfg.f_min = 375000;
+#ifndef CONFIG_TEGRA186
host->cfg.f_max = 48000000;
+#else
+ host->cfg.f_max = 375000;
+#endif
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
return -FDT_ERR_NOTFOUND;
}
+#ifndef CONFIG_TEGRA186
host->mmc_id = clock_decode_periph_id(blob, node);
if (host->mmc_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id\n", __func__);
return -FDT_ERR_NOTFOUND;
}
+#endif
/*
* NOTE: mmc->bus_width is determined by mmc.c dynamically.
*removablep = !fdtdec_get_bool(blob, node, "non-removable");
debug("%s: found controller at %p, width = %d, periph_id = %d\n",
- __func__, host->reg, host->width, host->mmc_id);
+ __func__, host->reg, host->width,
+#ifndef CONFIG_TEGRA186
+ host->mmc_id
+#else
+ -1
+#endif
+ );
return 0;
}
const void *blob = gd->fdt_blob;
debug("%s entry\n", __func__);
+ /* See if any Tegra186 MMC controllers are present */
+ count = fdtdec_find_aliases_for_id(blob, "sdhci",
+ COMPAT_NVIDIA_TEGRA186_SDMMC, node_list,
+ CONFIG_SYS_MMC_MAX_DEVICE);
+ debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count);
+ if (process_nodes(blob, node_list, count)) {
+ printf("%s: Error processing T186 mmc node(s)!\n", __func__);
+ return;
+ }
+
/* See if any Tegra210 MMC controllers are present */
count = fdtdec_find_aliases_for_id(blob, "sdhci",
COMPAT_NVIDIA_TEGRA210_SDMMC, node_list,
#define CONFIG_SYS_NS16550_IER 0x00
#endif /* CONFIG_SYS_NS16550_IER */
-#ifdef CONFIG_DM_SERIAL
-
-#ifndef CONFIG_SYS_NS16550_CLK
-#define CONFIG_SYS_NS16550_CLK 0
-#endif
-
static inline void serial_out_shift(void *addr, int shift, int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
#endif
}
+#ifdef CONFIG_DM_SERIAL
+
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK 0
+#endif
+
static void ns16550_writeb(NS16550_t port, int offset, int value)
{
struct ns16550_platdata *plat = port->plat;
(unsigned char *)addr - (unsigned char *)com_port)
#endif
-static inline int calc_divisor(NS16550_t port, int clock, int baudrate)
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
{
const unsigned int mode_x_div = 16;
return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
}
-int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
-{
-#ifdef CONFIG_OMAP1510
- /* If can't cleanly clock 115200 set div to 1 */
- if ((clock == 12000000) && (baudrate == 115200)) {
- port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
- return 1; /* return 1 for base divisor */
- }
- port->osc_12m_sel = 0; /* clear if previsouly set */
-#endif
-
- return calc_divisor(port, clock, baudrate);
-}
-
static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
{
serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
* feasible. The better fix is to move all users of this driver to
* driver model.
*/
- baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
- CONFIG_BAUDRATE);
+ baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE);
serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
serial_dout(&com_port->mcr, UART_MCRVAL);
serial_dout(&com_port->fcr, UART_FCRVAL);
#include "../host/xhci.h"
#ifdef CONFIG_OMAP_USB3PHY1_HOST
-struct usb_dpll_params {
+struct usb3_dpll_params {
u16 m;
u8 n;
u8 freq:3;
u32 mf;
};
-#define NUM_USB_CLKS 6
+struct usb3_dpll_map {
+ unsigned long rate;
+ struct usb3_dpll_params params;
+ struct usb3_dpll_map *dpll_map;
+};
-static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
- {1250, 5, 4, 20, 0}, /* 12 MHz */
- {3125, 20, 4, 20, 0}, /* 16.8 MHz */
- {1172, 8, 4, 20, 65537}, /* 19.2 MHz */
- {1250, 12, 4, 20, 0}, /* 26 MHz */
- {3125, 47, 4, 20, 92843}, /* 38.4 MHz */
- {1000, 7, 4, 10, 0}, /* 20 MHz */
+static struct usb3_dpll_map dpll_map_usb[] = {
+ {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
+ {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
+ {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
+ {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
+ {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
+ {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { }, /* Terminator */
};
+static struct usb3_dpll_params *omap_usb3_get_dpll_params(void)
+{
+ unsigned long rate;
+ struct usb3_dpll_map *dpll_map = dpll_map_usb;
+
+ rate = get_sys_clk_freq();
+
+ for (; dpll_map->rate; dpll_map++) {
+ if (rate == dpll_map->rate)
+ return &dpll_map->params;
+ }
+
+ dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
+
+ return NULL;
+}
+
static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
{
u32 val;
static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
{
- u32 clk_index = get_sys_clk_index();
+ struct usb3_dpll_params *dpll_params;
u32 val;
+ dpll_params = omap_usb3_get_dpll_params();
+ if (!dpll_params)
+ return;
+
val = readl(&phy_regs->pll_config_1);
val &= ~PLL_REGN_MASK;
- val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
+ val |= dpll_params->n << PLL_REGN_SHIFT;
writel(val, &phy_regs->pll_config_1);
val = readl(&phy_regs->pll_config_2);
val &= ~PLL_SELFREQDCO_MASK;
- val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
+ val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
writel(val, &phy_regs->pll_config_2);
val = readl(&phy_regs->pll_config_1);
val &= ~PLL_REGM_MASK;
- val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
+ val |= dpll_params->m << PLL_REGM_SHIFT;
writel(val, &phy_regs->pll_config_1);
val = readl(&phy_regs->pll_config_4);
val &= ~PLL_REGM_F_MASK;
- val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
+ val |= dpll_params->mf << PLL_REGM_F_SHIFT;
writel(val, &phy_regs->pll_config_4);
val = readl(&phy_regs->pll_config_3);
val &= ~PLL_SD_MASK;
- val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
+ val |= dpll_params->sd << PLL_SD_SHIFT;
writel(val, &phy_regs->pll_config_3);
omap_usb_dpll_relock(phy_regs);
--- /dev/null
+/*
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _P2771_0000_H
+#define _P2771_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra186-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY 19200000
+
+#endif
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE (64 * 1024)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
#define CONFIG_SPL_LIBDISK_SUPPORT
#else
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */
+#define CONFIG_SPL_LIBDISK_SUPPORT
#endif
#endif
/* Booting Linux */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
--- /dev/null
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__
+#define __CONFIG_SAMTEC_VINING_FPGA_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_LED
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run selboot"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* I2C EEPROM */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_BUS 0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
+#endif
+
+/*
+ * Status LEDs:
+ * 0 ... Top Green
+ * 1 ... Top Red
+ * 2 ... Bottom Green
+ * 3 ... Bottom Red
+ */
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BIT 48
+#define STATUS_LED_STATE STATUS_LED_OFF
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1 53
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT2 54
+#define STATUS_LED_STATE2 STATUS_LED_OFF
+#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT3 65
+#define STATUS_LED_STATE3 STATUS_LED_OFF
+#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_BOOTP_SEND_HOSTNAME
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_vining_fpga
+
+/*
+ * Active LOW GPIO buttons:
+ * A: GPIO 77 ... the button between USB B and ethernet
+ * B: GPIO 78 ... the button between USB A ports
+ *
+ * The logic:
+ * if button B is not pressed, boot normal Linux system immediatelly
+ * if button B is pressed, wait $bootdelay and boot recovery system
+ */
+#define CONFIG_PREBOOT \
+ "setenv hostname vining-${unit_serial} ; " \
+ "setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; " \
+ "if gpio input 78 ; then " \
+ "setenv bootdelay 10 ; " \
+ "setenv boottype rcvr ; " \
+ "else " \
+ "setenv bootdelay 5 ; " \
+ "setenv boottype norm ; " \
+ "fi"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "consdev=ttyS0\0" \
+ "baudrate=115200\0" \
+ "bootscript=boot.scr\0" \
+ "ubimtdnr=5\0" \
+ "ubimtd=rootfs\0" \
+ "ubipart=ubi0:rootfs\0" \
+ "ubisfcs=1\0" /* Default is flash at CS#1 */ \
+ "netdev=eth0\0" \
+ "hostname=vining_fpga\0" \
+ "kernel_addr_r=0x10000000\0" \
+ "mtdparts_0=ff705000.spi.0:" \
+ "1m(u-boot)," \
+ "64k(env1)," \
+ "64k(env2)," \
+ "256k(samtec1)," \
+ "256k(samtec2)," \
+ "-(rcvrfs)\0" /* Recovery */ \
+ "mtdparts_1=ff705000.spi.1:" \
+ "32m(rootfs)," \
+ "-(userfs)\0" \
+ "update_filename=u-boot-with-spl-dtb.sfp\0" \
+ "update_qspi_offset=0x0\0" \
+ "update_qspi=" /* Update the QSPI firmware */ \
+ "if sf probe ; then " \
+ "if tftp ${update_filename} ; then " \
+ "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
+ "fi ; " \
+ "fi\0" \
+ "fpga_filename=output_file.rbf\0" \
+ "load_fpga=" /* Load FPGA bitstream */ \
+ "if tftp ${fpga_filename} ; then " \
+ "fpga load 0 $loadaddr $filesize ; " \
+ "bridge enable ; " \
+ "fi\0" \
+ "addcons=" \
+ "setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "addip=" \
+ "setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off\0" \
+ "addmisc=" \
+ "setenv bootargs ${bootargs} ${miscargs}\0" \
+ "addmtd=" \
+ "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \
+ "setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
+ "addargs=run addcons addmtd addmisc\0" \
+ "ubiload=" \
+ "ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \
+ "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
+ "netload=" \
+ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
+ "miscargs=nohlt panic=1\0" \
+ "ubiargs=" \
+ "setenv bootargs ubi.mtd=${ubimtdnr} " \
+ "root=${ubipart} rootfstype=ubifs\0" \
+ "nfsargs=" \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
+ "ubi_sfsel=" \
+ "if test \"${boottype}\" = \"rcvr\" ; then " \
+ "setenv ubisfcs 0 ; " \
+ "setenv ubimtd rcvrfs ; " \
+ "setenv ubimtdnr 5 ; " \
+ "setenv mtdparts mtdparts=${mtdparts_0} ; " \
+ "setenv mtdids nor0=ff705000.spi.0 ; " \
+ "setenv ubipart ubi0:rootfs ; " \
+ "else " \
+ "setenv ubisfcs 1 ; " \
+ "setenv ubimtd rootfs ; " \
+ "setenv ubimtdnr 6 ; " \
+ "setenv mtdparts mtdparts=${mtdparts_1} ; " \
+ "setenv mtdids nor0=ff705000.spi.1 ; " \
+ "setenv ubipart ubi0:rootfs ; " \
+ "fi ; " \
+ "sf probe 0:${ubisfcs}\0" \
+ "ubi_ubi=" \
+ "run ubi_sfsel ubiload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "ubi_nfs=" \
+ "run ubiload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_ubi=" \
+ "run netload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_nfs=" \
+ "run netload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "selboot=" /* Select from where to boot. */ \
+ "if test \"${bootmode}\" = \"qspi\" ; then " \
+ "led all off ; " \
+ "if test \"${boottype}\" = \"rcvr\" ; then " \
+ "echo \"Booting recovery system\" ; " \
+ "led 3 on ; " /* Bottom RED */ \
+ "fi ; " \
+ "led 1 on ; " /* Top RED */ \
+ "run ubi_ubi ; " \
+ "else echo \"Unsupported boot mode: \"${bootmode} ; " \
+ "fi\0" \
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define MTDPARTS_DEFAULT \
+ "mtdparts=ff705000.spi.0:" \
+ "1m(u-boot)," \
+ "64k(env1)," \
+ "64k(env2)," \
+ "256k(samtec1)," \
+ "256k(samtec2)," \
+ "-(rcvrfs);" /* Recovery */ \
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+/* Enable DFU to SF and RAM */
+#define CONFIG_DFU_RAM
+#define CONFIG_DFU_SF
+
+/* Support changing the prompt string */
+#define CONFIG_CMDLINE_PS_SUPPORT
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_TEGRA_GPIO
#define CONFIG_CMD_ENTERRCM
/* Defines for SPL */
--- /dev/null
+/*
+ * Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_COMMON_H_
+#define _TEGRA186_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A57 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE 0x82800000 /* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_SYS_TEXT_BASE 0x80080000
+
+/* Generic Interrupt Controller */
+#define CONFIG_GICV2
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x80080000
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x90000000\0" \
+ "pxefile_addr_r=0x90100000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdt_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE 0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
+#define CONFIG_SPL_STACK 0x800ffffc
+
+#endif
#define CONFIG_SYS_MEMTEST_END 0x83f00000
#define CONFIG_CMD_MEMTEST
-#define CONFIG_USE_PRIVATE_LIBGCC
-
#define CONFIG_CMD_MII
#define CONFIG_PHY_GIGE
#include <dt-bindings/gpio/gpio.h>
-#define TEGRA_GPIO_BANK_ID_A 0
-#define TEGRA_GPIO_BANK_ID_B 1
-#define TEGRA_GPIO_BANK_ID_C 2
-#define TEGRA_GPIO_BANK_ID_D 3
-#define TEGRA_GPIO_BANK_ID_E 4
-#define TEGRA_GPIO_BANK_ID_F 5
-#define TEGRA_GPIO_BANK_ID_G 6
-#define TEGRA_GPIO_BANK_ID_H 7
-#define TEGRA_GPIO_BANK_ID_I 8
-#define TEGRA_GPIO_BANK_ID_J 9
-#define TEGRA_GPIO_BANK_ID_K 10
-#define TEGRA_GPIO_BANK_ID_L 11
-#define TEGRA_GPIO_BANK_ID_M 12
-#define TEGRA_GPIO_BANK_ID_N 13
-#define TEGRA_GPIO_BANK_ID_O 14
-#define TEGRA_GPIO_BANK_ID_P 15
-#define TEGRA_GPIO_BANK_ID_Q 16
-#define TEGRA_GPIO_BANK_ID_R 17
-#define TEGRA_GPIO_BANK_ID_S 18
-#define TEGRA_GPIO_BANK_ID_T 19
-#define TEGRA_GPIO_BANK_ID_U 20
-#define TEGRA_GPIO_BANK_ID_V 21
-#define TEGRA_GPIO_BANK_ID_W 22
-#define TEGRA_GPIO_BANK_ID_X 23
-#define TEGRA_GPIO_BANK_ID_Y 24
-#define TEGRA_GPIO_BANK_ID_Z 25
-#define TEGRA_GPIO_BANK_ID_AA 26
-#define TEGRA_GPIO_BANK_ID_BB 27
-#define TEGRA_GPIO_BANK_ID_CC 28
-#define TEGRA_GPIO_BANK_ID_DD 29
-#define TEGRA_GPIO_BANK_ID_EE 30
-#define TEGRA_GPIO_BANK_ID_FF 31
+#define TEGRA_GPIO_PORT_A 0
+#define TEGRA_GPIO_PORT_B 1
+#define TEGRA_GPIO_PORT_C 2
+#define TEGRA_GPIO_PORT_D 3
+#define TEGRA_GPIO_PORT_E 4
+#define TEGRA_GPIO_PORT_F 5
+#define TEGRA_GPIO_PORT_G 6
+#define TEGRA_GPIO_PORT_H 7
+#define TEGRA_GPIO_PORT_I 8
+#define TEGRA_GPIO_PORT_J 9
+#define TEGRA_GPIO_PORT_K 10
+#define TEGRA_GPIO_PORT_L 11
+#define TEGRA_GPIO_PORT_M 12
+#define TEGRA_GPIO_PORT_N 13
+#define TEGRA_GPIO_PORT_O 14
+#define TEGRA_GPIO_PORT_P 15
+#define TEGRA_GPIO_PORT_Q 16
+#define TEGRA_GPIO_PORT_R 17
+#define TEGRA_GPIO_PORT_S 18
+#define TEGRA_GPIO_PORT_T 19
+#define TEGRA_GPIO_PORT_U 20
+#define TEGRA_GPIO_PORT_V 21
+#define TEGRA_GPIO_PORT_W 22
+#define TEGRA_GPIO_PORT_X 23
+#define TEGRA_GPIO_PORT_Y 24
+#define TEGRA_GPIO_PORT_Z 25
+#define TEGRA_GPIO_PORT_AA 26
+#define TEGRA_GPIO_PORT_BB 27
+#define TEGRA_GPIO_PORT_CC 28
+#define TEGRA_GPIO_PORT_DD 29
+#define TEGRA_GPIO_PORT_EE 30
+#define TEGRA_GPIO_PORT_FF 31
-#define TEGRA_GPIO(bank, offset) \
- ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+#define TEGRA_GPIO(port, offset) \
+ ((TEGRA_GPIO_PORT_##port * 8) + offset)
#endif
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This header provides constants for binding nvidia,tegra186-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_MAIN_GPIO_PORT_A 0
+#define TEGRA_MAIN_GPIO_PORT_B 1
+#define TEGRA_MAIN_GPIO_PORT_C 2
+#define TEGRA_MAIN_GPIO_PORT_D 3
+#define TEGRA_MAIN_GPIO_PORT_E 4
+#define TEGRA_MAIN_GPIO_PORT_F 5
+#define TEGRA_MAIN_GPIO_PORT_G 6
+#define TEGRA_MAIN_GPIO_PORT_H 7
+#define TEGRA_MAIN_GPIO_PORT_I 8
+#define TEGRA_MAIN_GPIO_PORT_J 9
+#define TEGRA_MAIN_GPIO_PORT_K 10
+#define TEGRA_MAIN_GPIO_PORT_L 11
+#define TEGRA_MAIN_GPIO_PORT_M 12
+#define TEGRA_MAIN_GPIO_PORT_N 13
+#define TEGRA_MAIN_GPIO_PORT_O 14
+#define TEGRA_MAIN_GPIO_PORT_P 15
+#define TEGRA_MAIN_GPIO_PORT_Q 16
+#define TEGRA_MAIN_GPIO_PORT_R 17
+#define TEGRA_MAIN_GPIO_PORT_T 18
+#define TEGRA_MAIN_GPIO_PORT_X 19
+#define TEGRA_MAIN_GPIO_PORT_Y 20
+#define TEGRA_MAIN_GPIO_PORT_BB 21
+#define TEGRA_MAIN_GPIO_PORT_CC 22
+
+#define TEGRA_MAIN_GPIO(port, offset) \
+ ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_AON_GPIO_PORT_S 0
+#define TEGRA_AON_GPIO_PORT_U 1
+#define TEGRA_AON_GPIO_PORT_V 2
+#define TEGRA_AON_GPIO_PORT_W 3
+#define TEGRA_AON_GPIO_PORT_Z 4
+#define TEGRA_AON_GPIO_PORT_AA 5
+#define TEGRA_AON_GPIO_PORT_EE 6
+#define TEGRA_AON_GPIO_PORT_FF 7
+
+#define TEGRA_AON_GPIO(port, offset) \
+ ((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
+
+#endif
COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */
COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
+ COMPAT_NVIDIA_TEGRA186_SDMMC, /* Tegra186 SDMMC controller */
COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */
COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
config USE_PRIVATE_LIBGCC
bool "Use private libgcc"
depends on HAVE_PRIVATE_LIBGCC
+ default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS)
help
This option allows you to use the built-in libgcc implementation
of U-Boot instead of the one provided by the compiler.
COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+ COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
*outstr++ = ch;
}
-/* Note that size is ignored */
-int snprintf(char *buf, size_t size, const char *fmt, ...)
+int sprintf(char *buf, const char *fmt, ...)
{
va_list va;
int ret;
return ret;
}
+
+/* Note that size is ignored */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+{
+ va_list va;
+ int ret;
+
+ va_start(va, fmt);
+ ret = sprintf(buf, fmt, va);
+ va_end(va);
+
+ return ret;
+}
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