]> git.sur5r.net Git - u-boot/commitdiff
blackfin: convert to use CONFIG_SYS_I2C framework
authorScott Jiang <scott.jiang.linux@gmail.com>
Thu, 13 Nov 2014 07:30:55 +0000 (15:30 +0800)
committerHeiko Schocher <hs@denx.de>
Mon, 17 Nov 2014 07:10:37 +0000 (08:10 +0100)
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
23 files changed:
drivers/i2c/adi_i2c.c
include/configs/bct-brettl2.h
include/configs/bf518f-ezbrd.h
include/configs/bf526-ezbrd.h
include/configs/bf527-ad7160-eval.h
include/configs/bf527-ezkit.h
include/configs/bf527-sdp.h
include/configs/bf537-minotaur.h
include/configs/bf537-pnav.h
include/configs/bf537-srv1.h
include/configs/bf537-stamp.h
include/configs/bf538f-ezkit.h
include/configs/bf548-ezkit.h
include/configs/bf609-ezkit.h
include/configs/bfin_adi_common.h
include/configs/br4.h
include/configs/cm-bf527.h
include/configs/cm-bf537e.h
include/configs/cm-bf537u.h
include/configs/cm-bf548.h
include/configs/pr1.h
include/configs/tcm-bf518.h
include/configs/tcm-bf537.h

index 71077c5a1114f87366bf80ccf865eb94be192919..20495b1d7f8c86f28e84ba12255f6024c02f971c 100644 (file)
@@ -13,6 +13,8 @@
 #include <asm/twi.h>
 #include <asm/io.h>
 
+static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);
+
 /* Every register is 32bit aligned, but only 16bits in size */
 #define ureg(name) u16 name; u16 __pad_##name;
 struct twi_regs {
@@ -36,25 +38,12 @@ struct twi_regs {
 };
 #undef ureg
 
-/* U-Boot I2C framework allows only one active device at a time.  */
 #ifdef TWI_CLKDIV
 #define TWI0_CLKDIV TWI_CLKDIV
-#endif
-static struct twi_regs *twi = (void *)TWI0_CLKDIV;
-
-#ifdef DEBUG
-# define dmemset(s, c, n) memset(s, c, n)
-#else
-# define dmemset(s, c, n)
-#endif
-#define debugi(fmt, args...) \
-       debug( \
-               "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
-               twi->master_stat, twi->fifo_stat, twi->int_stat, \
-               __func__, __LINE__, ## args)
-
-#ifdef CONFIG_TWICLK_KHZ
-# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
+# ifdef CONFIG_SYS_MAX_I2C_BUS
+# undef CONFIG_SYS_MAX_I2C_BUS
+# endif
+#define CONFIG_SYS_MAX_I2C_BUS 1
 #endif
 
 /*
@@ -70,7 +59,7 @@ static struct twi_regs *twi = (void *)TWI0_CLKDIV;
 #define SYS_I2C_DUTY              I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
 /* Note: duty is inverse of speed, so the comparisons below are correct */
 #if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
-# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz"
+# error "The I2C hardware can only operate 20KHz - 400KHz"
 #endif
 
 /* All transfers are described by this data structure */
@@ -92,7 +81,7 @@ struct i2c_msg {
  * wait_for_completion - manage the actual i2c transfer
  *     @msg: the i2c msg
  */
-static int wait_for_completion(struct i2c_msg *msg)
+static int wait_for_completion(struct twi_regs *twi, struct i2c_msg *msg)
 {
        u16 int_stat, ctl;
        ulong timebase = get_timer(0);
@@ -101,7 +90,6 @@ static int wait_for_completion(struct i2c_msg *msg)
                int_stat = readw(&twi->int_stat);
 
                if (int_stat & XMTSERV) {
-                       debugi("processing XMTSERV");
                        writew(XMTSERV, &twi->int_stat);
                        if (msg->alen) {
                                writew(*(msg->abuf++), &twi->xmt_data8);
@@ -119,7 +107,6 @@ static int wait_for_completion(struct i2c_msg *msg)
                        }
                }
                if (int_stat & RCVSERV) {
-                       debugi("processing RCVSERV");
                        writew(RCVSERV, &twi->int_stat);
                        if (msg->len) {
                                *(msg->buf++) = readw(&twi->rcv_data8);
@@ -130,12 +117,10 @@ static int wait_for_completion(struct i2c_msg *msg)
                        }
                }
                if (int_stat & MERR) {
-                       debugi("processing MERR");
                        writew(MERR, &twi->int_stat);
                        return msg->len;
                }
                if (int_stat & MCOMP) {
-                       debugi("processing MCOMP");
                        writew(MCOMP, &twi->int_stat);
                        if (msg->flags & I2C_M_COMBO && msg->len) {
                                ctl = readw(&twi->master_ctl);
@@ -155,16 +140,10 @@ static int wait_for_completion(struct i2c_msg *msg)
        return msg->len;
 }
 
-/**
- * i2c_transfer - setup an i2c transfer
- *     @return: 0 if things worked, non-0 if things failed
- *
- *     Here we just get the i2c stuff all prepped and ready, and then tail off
- *     into wait_for_completion() for all the bits to go.
- */
-static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
-                       int len, u8 flags)
+static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
+                       int alen, uint8_t *buffer, int len, uint8_t flags)
 {
+       struct twi_regs *twi = i2c_get_base(adap);
        int ret;
        u16 ctl;
        uchar addr_buffer[] = {
@@ -180,12 +159,6 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
                .alen  = alen,
        };
 
-       dmemset(buffer, 0xff, len);
-       debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i ",
-               chip, addr, alen, buffer[0], len);
-       debugi("flags=0x%02x[%s] ", flags,
-               (flags & I2C_M_READ ? "rd" : "wr"));
-
        /* wait for things to settle */
        while (readw(&twi->master_stat) & BUSBUSY)
                if (ctrlc())
@@ -201,11 +174,9 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
        /* prime the pump */
        if (msg.alen) {
                len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
-               debugi("first byte=0x%02x", *msg.abuf);
                writew(*(msg.abuf++), &twi->xmt_data8);
                --msg.alen;
        } else if (!(msg.flags & I2C_M_READ) && msg.len) {
-               debugi("first byte=0x%02x", *msg.buf);
                writew(*(msg.buf++), &twi->xmt_data8);
                --msg.len;
        }
@@ -222,8 +193,7 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
        writew(ctl, &twi->master_ctl);
 
        /* process the rest */
-       ret = wait_for_completion(&msg);
-       debugi("ret=%d", ret);
+       ret = wait_for_completion(twi, &msg);
 
        if (ret) {
                ctl = readw(&twi->master_ctl) & ~MEN;
@@ -237,12 +207,9 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
        return ret;
 }
 
-/**
- * i2c_set_bus_speed - set i2c bus speed
- *     @speed: bus speed (in HZ)
- */
-int i2c_set_bus_speed(unsigned int speed)
+static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
 {
+       struct twi_regs *twi = i2c_get_base(adap);
        u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
 
        /* Set TWI interface clock */
@@ -257,28 +224,10 @@ int i2c_set_bus_speed(unsigned int speed)
        return 0;
 }
 
-/**
- * i2c_get_bus_speed - get i2c bus speed
- *     @speed: bus speed (in HZ)
- */
-unsigned int i2c_get_bus_speed(void)
-{
-       u16 clkdiv = readw(&twi->clkdiv) & 0xff;
-       /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
-       return 5000000 / clkdiv;
-}
-
-/**
- * i2c_init - initialize the i2c bus
- *     @speed: bus speed (in HZ)
- *     @slaveaddr: address of device in slave mode (0 - not slave)
- *
- *     Slave mode isn't actually implemented.  It'll stay that way until
- *     we get a real request for it.
- */
-void i2c_init(int speed, int slaveaddr)
+static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 {
-       uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
+       struct twi_regs *twi = i2c_get_base(adap);
+       u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
 
        /* Set TWI internal clock as 10MHz */
        writew(prescale, &twi->control);
@@ -288,100 +237,69 @@ void i2c_init(int speed, int slaveaddr)
 
        /* Enable it */
        writew(TWI_ENA | prescale, &twi->control);
-
-       debugi("CONTROL:0x%04x CLKDIV:0x%04x", readw(&twi->control),
-               readw(&twi->clkdiv));
-
-#if CONFIG_SYS_I2C_SLAVE
-# error I2C slave support not tested/supported
-#endif
 }
 
-/**
- * i2c_probe - test if a chip exists at a given i2c address
- *     @chip: i2c chip addr to search for
- *     @return: 0 if found, non-0 if not found
- */
-int i2c_probe(uchar chip)
+static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+                       uint addr, int alen, uint8_t *buffer, int len)
 {
-       u8 byte;
-       return i2c_read(chip, 0, 0, &byte, 1);
+       return i2c_transfer(adap, chip, addr, alen, buffer,
+                       len, alen ? I2C_M_COMBO : I2C_M_READ);
 }
 
-/**
- * i2c_read - read data from an i2c device
- *     @chip: i2c chip addr
- *     @addr: memory (register) address in the chip
- *     @alen: byte size of address
- *     @buffer: buffer to store data read from chip
- *     @len: how many bytes to read
- *     @return: 0 on success, non-0 on failure
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
+                       uint addr, int alen, uint8_t *buffer, int len)
 {
-       return i2c_transfer(chip, addr, alen, buffer,
-                       len, (alen ? I2C_M_COMBO : I2C_M_READ));
+       return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
 }
 
-/**
- * i2c_write - write data to an i2c device
- *     @chip: i2c chip addr
- *     @addr: memory (register) address in the chip
- *     @alen: byte size of address
- *     @buffer: buffer holding data to write to chip
- *     @len: how many bytes to write
- *     @return: 0 on success, non-0 on failure
- */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 {
-       return i2c_transfer(chip, addr, alen, buffer, len, 0);
+       u8 byte;
+       return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
 }
 
-/**
- * i2c_set_bus_num - change active I2C bus
- *     @bus: bus index, zero based
- *     @returns: 0 on success, non-0 on failure
- */
-int i2c_set_bus_num(unsigned int bus)
+static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
 {
-       switch (bus) {
-#if CONFIG_SYS_MAX_I2C_BUS > 0
-       case 0:
-               twi = (void *)TWI0_CLKDIV;
-               return 0;
+       switch (adap->hwadapnr) {
+#if CONFIG_SYS_MAX_I2C_BUS > 2
+       case 2:
+               return (struct twi_regs *)TWI2_CLKDIV;
 #endif
 #if CONFIG_SYS_MAX_I2C_BUS > 1
        case 1:
-               twi = (void *)TWI1_CLKDIV;
-               return 0;
-#endif
-#if CONFIG_SYS_MAX_I2C_BUS > 2
-       case 2:
-               twi = (void *)TWI2_CLKDIV;
-               return 0;
+               return (struct twi_regs *)TWI1_CLKDIV;
 #endif
-       default: return -1;
+       case 0:
+               return (struct twi_regs *)TWI0_CLKDIV;
+
+       default:
+               printf("wrong hwadapnr: %d\n", adap->hwadapnr);
        }
+
+       return NULL;
 }
 
-/**
- * i2c_get_bus_num - returns index of active I2C bus
- */
-unsigned int i2c_get_bus_num(void)
-{
-       switch ((unsigned long)twi) {
-#if CONFIG_SYS_MAX_I2C_BUS > 0
-       case TWI0_CLKDIV:
-               return 0;
-#endif
+U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
+                        adi_i2c_read, adi_i2c_write,
+                        adi_i2c_setspeed,
+                        CONFIG_SYS_I2C_SPEED,
+                        0,
+                        0)
+
 #if CONFIG_SYS_MAX_I2C_BUS > 1
-       case TWI1_CLKDIV:
-               return 1;
+U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
+                        adi_i2c_read, adi_i2c_write,
+                        adi_i2c_setspeed,
+                        CONFIG_SYS_I2C_SPEED,
+                        0,
+                        1)
 #endif
+
 #if CONFIG_SYS_MAX_I2C_BUS > 2
-       case TWI2_CLKDIV:
-               return 2;
+U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
+                        adi_i2c_read, adi_i2c_write,
+                        adi_i2c_setspeed,
+                        CONFIG_SYS_I2C_SPEED,
+                        0,
+                        2)
 #endif
-       default: return -1;
-       }
-}
index f0b74d82a35171029d475f468d75ae8bb7abfb99..39982ef72cf1c6fc25a6d24c96f178da8d624700 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index 4df51b9895e8ae981e8a308f7b79b886990a0135..50e85ca93c1126eca7094bdec57bceb3e3c9d0f8 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index 55bfbbec663559aaeb6c48bf217e3a48a87d5581..7fc882a133b4e3c4b622dd8031e0dc9b3c0c5bc1 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index 589c7a5d12e0be48d01fbb9c8b04001821213f52..c2958e834e8cfc054aaa9d8343d1cc0ea4d20cd4 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index 0e68952f2aab176e0403b6b2f779075e86a154ec..79e440a0be4780bb05181f735c328508ae7b8dba 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index a3ad7aea7f0a671098836966a4cce421292d5286..b374ab57725e73f97bdf0a30907b453cf0411d8d 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index d94c2df6a170b747625c43beab73c2d00f325faf..6df89af402985004962cbdac8b147c9f4c05900e 100644 (file)
 /*
  * I2C settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 #define CONFIG_SYS_I2C_SPEED           50000
 #define CONFIG_SYS_I2C_SLAVE           0
 
index 6c9a907983d78adf0726a696ab2839a7f6541782..4f2b2cbf296a8fe25e124caa99f2de4fec07b63c 100644 (file)
 /*
  * I2C settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index a6ceffa2884d094d8db8a1ae4b0c46f4964c8293..d01d88f3b47cc673af67f5dd079fe8cad2ff76e1 100644 (file)
 /*
  * I2C settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 #define CONFIG_SYS_I2C_SPEED           50000
 #define CONFIG_SYS_I2C_SLAVE           0
 
index 7ab644f53114ded3668def82bdcbdaa2173694e0..7b5a5a7f71dfb3c4a71e817f49c024cf7e1ab69d 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index 743e193f574b4a469344cb7b8d4a2ce8d7692eb3..e60558e1b62f838b524c663d4253606559ad486c 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index 6b29d0849308aba23532978cb9e2e066fba199f3..e71e6d324cda769a743a4d3b01bef34c956031be 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index f02e15550530a1d3aa8d729c3bb2ddd9e0fdbd5e..878009ff6615a2e4f2e6aa8c4b75ec8d785e2311 100644 (file)
@@ -81,8 +81,8 @@
 #define CONFIG_PHYLIB
 
 /* i2c Settings */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C
 
 /*
  * Flash Settings
index 07ec5f2bd83a351b170988d7709a773193d1bc3d..143d3ddd2d8e699af12dc585ce606fecae20e5ee 100644 (file)
@@ -73,7 +73,7 @@
 # ifdef CONFIG_SPI_FLASH
 #  define CONFIG_CMD_SF
 # endif
-# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+# if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
 #  define CONFIG_CMD_I2C
 #  define CONFIG_SOFT_I2C_READ_REPEATED_START
 # endif
 /*
  * I2C Settings
  */
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
 # ifndef CONFIG_SYS_I2C_SPEED
 #  define CONFIG_SYS_I2C_SPEED 50000
 # endif
index 13e939fac6250f3b2c39d5c92f5cbd3a4c7f6725..48cf184826d979b0e93f796faf999b97ac0db92b 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C
 
 
 /*
index 3668903afc839eb323f8e3b2fbc484f5988c416f..643c8379aad6207877321826ef5fecd74a341206 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index 85f5341d03aeffff61290e8c9f8831453857d6aa..e05956846c92436ae2281605807fc068d9e8b0b8 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index 5dffd1bf1b7db442d9c775e5b147a933df02acb1..1f26457a955abc3ec96c3c2f5814d477fd4924b7 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index 13ea0677780f35e5c9226f6e60844fadbca93f13..72eafc5699b57f5dc578fad441a733f4a66b21e5 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index eb18d6d025607452f80b7654f9a7747c85079d0f..13fb675a5fdc9033123ebb4bb585eb0d98a9590a 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C
 
 
 /*
index e9bff83b4a62885db7048ffb50642c0be32e5ffb..e96a7427e5864c64280e0c3dc2eb38f0645ef484 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*
index caf884726e1e2e60829e782f6d9ae71f68ba6ba0..42129fb7d8419e83ca2eb3883c5e6cd31a60ba39 100644 (file)
 /*
  * I2C Settings
  */
+#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
-#define CONFIG_HARD_I2C                1
 
 
 /*