]> git.sur5r.net Git - u-boot/commitdiff
POST: OCM test added.
authorYuri Tikhonov <yur@emcraft.com>
Thu, 8 May 2008 13:42:47 +0000 (15:42 +0200)
committerWolfgang Denk <wd@denx.de>
Thu, 8 May 2008 19:45:21 +0000 (21:45 +0200)
Added OCM test to POST layer. This version runs before all other tests
but doesn't yet interrupt post sequence on failure.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
include/post.h
post/cpu/ppc4xx/Makefile
post/cpu/ppc4xx/ocm.c [new file with mode: 0644]
post/tests.c

index ee07d2caa2e56edfb7f0eb13a331bfc26ac92c8c..a108c7d7bc934101b5e264e932bd3e7a8b3b5823 100644 (file)
@@ -102,6 +102,7 @@ extern int post_hotkeys_pressed(void);
 #define CFG_POST_BSPEC3                0x00040000
 #define CFG_POST_BSPEC4                0x00080000
 #define CFG_POST_BSPEC5                0x00100000
+#define CFG_POST_OCM           0x00200000
 
 #endif /* CONFIG_POST */
 
index 87ecd7c907458ead56ce5014ce597b31f1b23854..62be9c6aa841e9e0f78a0d30d7da742733773404 100644 (file)
@@ -25,6 +25,6 @@ include $(OBJTREE)/include/autoconf.mk
 LIB    = libpostppc4xx.a
 
 AOBJS-$(CONFIG_HAS_POST)       += cache_4xx.o
-COBJS-$(CONFIG_HAS_POST)       += cache.o denali_ecc.o ether.o fpu.o spr.o uart.o watchdog.o
+COBJS-$(CONFIG_HAS_POST)       += cache.o denali_ecc.o ether.o fpu.o ocm.o spr.o uart.o watchdog.o
 
 include $(TOPDIR)/post/rules.mk
diff --git a/post/cpu/ppc4xx/ocm.c b/post/cpu/ppc4xx/ocm.c
new file mode 100644 (file)
index 0000000..88aa93e
--- /dev/null
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2008 Ilya Yanok, EmCraft Systems, yanok@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+/*
+ * This test attempts to verify on-chip memory (OCM). Result is written
+ * to the scratch register and if test succeed it won't be run till next
+ * power on.
+ */
+
+#include <post.h>
+
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OCM_TEST_PATTERN1      0x55555555
+#define OCM_TEST_PATTERN2      0xAAAAAAAA
+
+#if CONFIG_POST & CFG_POST_OCM
+
+static uint ocm_status_read(void)
+{
+       return in_be32((void *)CFG_OCM_STATUS_ADDR) &
+               CFG_OCM_STATUS_MASK;
+}
+
+static void ocm_status_write(uint value)
+{
+       out_be32((void *)CFG_OCM_STATUS_ADDR, value |
+               (in_be32((void *)CFG_OCM_STATUS_ADDR) &
+                       ~CFG_OCM_STATUS_MASK));
+}
+
+static inline int ocm_test_word(uint value, uint *address)
+{
+       uint read_value;
+
+       *address = value;
+       sync();
+       read_value = *address;
+
+       return (read_value != value);
+}
+
+int ocm_post_test(int flags)
+{
+       uint   old_value;
+       int    ret = 0;
+       uint  *address = (uint*)CFG_OCM_BASE;
+
+       if (ocm_status_read() == CFG_OCM_STATUS_OK)
+               return 0;
+       for (; address < (uint*)(CFG_OCM_BASE + CFG_OCM_SIZE); address++) {
+               old_value = *address;
+               if (ocm_test_word(OCM_TEST_PATTERN1, address) ||
+                               ocm_test_word(OCM_TEST_PATTERN2, address)) {
+                       ret = 1;
+                       *address = old_value;
+                       printf("OCM POST failed at %p!\n", address);
+                       break;
+               }
+               *address = old_value;
+       }
+       ocm_status_write(ret ? CFG_OCM_STATUS_FAIL : CFG_OCM_STATUS_OK);
+       return ret;
+}
+#endif /* CONFIG_POST & CFG_POST_OCM */
index 5db59d64b17f4deb221961615950a93c42c9a343..cdf4c8641943caa5188b3f418aebdf55ab1c24a0 100644 (file)
@@ -29,6 +29,7 @@
 
 #include <post.h>
 
+extern int ocm_post_test (int flags);
 extern int cache_post_test (int flags);
 extern int watchdog_post_test (int flags);
 extern int i2c_post_test (int flags);
@@ -60,6 +61,18 @@ extern void sysmon_reloc (void);
 
 struct post_test post_list[] =
 {
+#if CONFIG_POST & CFG_POST_OCM
+    {
+       "OCM test",
+       "ocm",
+       "This test checks on chip memory (OCM).",
+       POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL,
+       &ocm_post_test,
+       NULL,
+       NULL,
+       CFG_POST_OCM
+    },
+#endif
 #if CONFIG_POST & CFG_POST_CACHE
     {
        "Cache test",