]> git.sur5r.net Git - u-boot/commitdiff
am335x_evm / gumstix pepper: Correct DDR settings
authorTom Rini <trini@ti.com>
Tue, 8 Jul 2014 01:40:16 +0000 (21:40 -0400)
committerTom Rini <trini@ti.com>
Fri, 25 Jul 2014 20:26:08 +0000 (16:26 -0400)
As noted by clang, we have been shifting certain values out of 32bit
range when setting some DDR registers.  Upon further inspection these
had been touching reserved fields (and having no impact).  These came in
from historical bring-up code and can be discarded.  Similarly, we had
been declaring some fields as 0 when they will be initialized that way.
Tested on Beaglebone White.

Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Ash Charles <ash@gumstix.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-By: Ash Charles <ashcharles@gmail.com>
arch/arm/include/asm/arch-am33xx/ddr_defs.h
board/gumstix/pepper/board.c
board/ti/am335x/board.c

index 4d899528f5bc157fc0affd398670c4e33dce969b..97bbfe2e65e887991899889df3fb23e55052a43e 100644 (file)
 #define MT47H128M16RT25E_EMIF_SDCFG            0x41805332
 #define MT47H128M16RT25E_EMIF_SDREF            0x0000081a
 #define MT47H128M16RT25E_RATIO                 0x80
-#define MT47H128M16RT25E_INVERT_CLKOUT         0x00
 #define MT47H128M16RT25E_RD_DQS                        0x12
-#define MT47H128M16RT25E_WR_DQS                        0x00
-#define MT47H128M16RT25E_PHY_WRLVL             0x00
-#define MT47H128M16RT25E_PHY_GATELVL           0x00
 #define MT47H128M16RT25E_PHY_WR_DATA           0x40
 #define MT47H128M16RT25E_PHY_FIFO_WE           0x80
 #define MT47H128M16RT25E_IOCTRL_VALUE          0x18B
index 75aac49fd0eda0746e383bfcb0e891d3e859750b..f644f8188bc9d9b948716da68a8fcfefc44bcb5a 100644 (file)
@@ -34,41 +34,17 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SPL_BUILD
 static const struct ddr_data ddr2_data = {
-       .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
-                         (MT47H128M16RT25E_RD_DQS<<20) |
-                         (MT47H128M16RT25E_RD_DQS<<10) |
-                         (MT47H128M16RT25E_RD_DQS<<0)),
-       .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
-                         (MT47H128M16RT25E_WR_DQS<<20) |
-                         (MT47H128M16RT25E_WR_DQS<<10) |
-                         (MT47H128M16RT25E_WR_DQS<<0)),
-       .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
-                        (MT47H128M16RT25E_PHY_WRLVL<<20) |
-                        (MT47H128M16RT25E_PHY_WRLVL<<10) |
-                        (MT47H128M16RT25E_PHY_WRLVL<<0)),
-       .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
-                        (MT47H128M16RT25E_PHY_GATELVL<<20) |
-                        (MT47H128M16RT25E_PHY_GATELVL<<10) |
-                        (MT47H128M16RT25E_PHY_GATELVL<<0)),
-       .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
-                         (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
-                         (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
-                         (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
-       .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
-                         (MT47H128M16RT25E_PHY_WR_DATA<<20) |
-                         (MT47H128M16RT25E_PHY_WR_DATA<<10) |
-                         (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+       .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+       .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+       .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 };
 
 static const struct cmd_control ddr2_cmd_ctrl_data = {
        .cmd0csratio = MT47H128M16RT25E_RATIO,
-       .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
        .cmd1csratio = MT47H128M16RT25E_RATIO,
-       .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
        .cmd2csratio = MT47H128M16RT25E_RATIO,
-       .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 };
 
 static const struct emif_regs ddr2_emif_reg_data = {
index da780edb89663a175a1c7d122ac45c652be432b3..d81eec90b44b0a9d4802a0c3bb29fe3311d21afc 100644 (file)
@@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 static const struct ddr_data ddr2_data = {
-       .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
-                         (MT47H128M16RT25E_RD_DQS<<20) |
-                         (MT47H128M16RT25E_RD_DQS<<10) |
-                         (MT47H128M16RT25E_RD_DQS<<0)),
-       .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
-                         (MT47H128M16RT25E_WR_DQS<<20) |
-                         (MT47H128M16RT25E_WR_DQS<<10) |
-                         (MT47H128M16RT25E_WR_DQS<<0)),
-       .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
-                        (MT47H128M16RT25E_PHY_WRLVL<<20) |
-                        (MT47H128M16RT25E_PHY_WRLVL<<10) |
-                        (MT47H128M16RT25E_PHY_WRLVL<<0)),
-       .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
-                        (MT47H128M16RT25E_PHY_GATELVL<<20) |
-                        (MT47H128M16RT25E_PHY_GATELVL<<10) |
-                        (MT47H128M16RT25E_PHY_GATELVL<<0)),
-       .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
-                         (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
-                         (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
-                         (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
-       .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
-                         (MT47H128M16RT25E_PHY_WR_DATA<<20) |
-                         (MT47H128M16RT25E_PHY_WR_DATA<<10) |
-                         (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+       .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+       .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+       .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 };
 
 static const struct cmd_control ddr2_cmd_ctrl_data = {
        .cmd0csratio = MT47H128M16RT25E_RATIO,
-       .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
        .cmd1csratio = MT47H128M16RT25E_RATIO,
-       .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
        .cmd2csratio = MT47H128M16RT25E_RATIO,
-       .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 };
 
 static const struct emif_regs ddr2_emif_reg_data = {