#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_RATIO 0x80
-#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
-#define MT47H128M16RT25E_WR_DQS 0x00
-#define MT47H128M16RT25E_PHY_WRLVL 0x00
-#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
#ifdef CONFIG_SPL_BUILD
static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
- (MT47H128M16RT25E_RD_DQS<<20) |
- (MT47H128M16RT25E_RD_DQS<<10) |
- (MT47H128M16RT25E_RD_DQS<<0)),
- .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
- (MT47H128M16RT25E_WR_DQS<<20) |
- (MT47H128M16RT25E_WR_DQS<<10) |
- (MT47H128M16RT25E_WR_DQS<<0)),
- .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
- (MT47H128M16RT25E_PHY_WRLVL<<20) |
- (MT47H128M16RT25E_PHY_WRLVL<<10) |
- (MT47H128M16RT25E_PHY_WRLVL<<0)),
- .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
- (MT47H128M16RT25E_PHY_GATELVL<<20) |
- (MT47H128M16RT25E_PHY_GATELVL<<10) |
- (MT47H128M16RT25E_PHY_GATELVL<<0)),
- .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
- (MT47H128M16RT25E_PHY_WR_DATA<<20) |
- (MT47H128M16RT25E_PHY_WR_DATA<<10) |
- (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
- .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
- (MT47H128M16RT25E_RD_DQS<<20) |
- (MT47H128M16RT25E_RD_DQS<<10) |
- (MT47H128M16RT25E_RD_DQS<<0)),
- .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
- (MT47H128M16RT25E_WR_DQS<<20) |
- (MT47H128M16RT25E_WR_DQS<<10) |
- (MT47H128M16RT25E_WR_DQS<<0)),
- .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
- (MT47H128M16RT25E_PHY_WRLVL<<20) |
- (MT47H128M16RT25E_PHY_WRLVL<<10) |
- (MT47H128M16RT25E_PHY_WRLVL<<0)),
- .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
- (MT47H128M16RT25E_PHY_GATELVL<<20) |
- (MT47H128M16RT25E_PHY_GATELVL<<10) |
- (MT47H128M16RT25E_PHY_GATELVL<<0)),
- .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
- (MT47H128M16RT25E_PHY_WR_DATA<<20) |
- (MT47H128M16RT25E_PHY_WR_DATA<<10) |
- (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
- .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {