]> git.sur5r.net Git - u-boot/commitdiff
Merge git://git.denx.de/u-boot-fsl-qoriq
authorTom Rini <trini@konsulko.com>
Fri, 11 May 2018 11:09:21 +0000 (07:09 -0400)
committerTom Rini <trini@konsulko.com>
Fri, 11 May 2018 11:09:21 +0000 (07:09 -0400)
39 files changed:
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
arch/arm/cpu/armv8/fsl-layerscape/soc.c
arch/arm/cpu/armv8/sec_firmware.c
arch/powerpc/cpu/mpc85xx/release.S
board/freescale/ls1088a/ddr.h
board/freescale/ls1088a/eth_ls1088aqds.c
configs/ls1088aqds_defconfig
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
configs/ls1088aqds_qspi_defconfig
configs/ls1088aqds_sdcard_ifc_defconfig
configs/ls1088aqds_sdcard_qspi_defconfig
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_qspi_defconfig
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_sdcard_qspi_defconfig
doc/uImage.FIT/sec_firmware_ppa.its [new file with mode: 0644]
drivers/mtd/nand/fsl_ifc_nand.c
drivers/net/fsl-mc/dpbp.c
drivers/net/fsl-mc/dpio/dpio.c
drivers/net/fsl-mc/dpmac.c
drivers/net/fsl-mc/dpni.c
drivers/net/fsl-mc/dprc.c
drivers/net/fsl-mc/fsl_dpmng_cmd.h
drivers/net/fsl-mc/mc.c
drivers/net/ldpaa_eth/ldpaa_eth.c
drivers/net/ldpaa_eth/ldpaa_eth.h
drivers/spi/fsl_qspi.c
include/configs/ls1088a_common.h
include/fsl-mc/fsl_dpbp.h
include/fsl-mc/fsl_dpio.h
include/fsl-mc/fsl_dpmac.h
include/fsl-mc/fsl_dpni.h
include/fsl-mc/fsl_dprc.h
include/fsl-mc/fsl_mc_cmd.h
include/fsl-mc/fsl_mc_private.h
include/fsl_ifc.h

index 7edc06d20263a1970d78b7684e07a24f92a02e4e..546de33b72e6e35d33702fe4e989aa5ce61df6f5 100644 (file)
@@ -469,6 +469,14 @@ config SYS_FSL_SDHC_CLK_DIV
        help
          This is the divider that is used to derive SDHC clock from Platform
          clock, in another word SDHC_clk = Platform_clk / this_divider.
+
+config SYS_FSL_QMAN_CLK_DIV
+       int "QMAN clock divider"
+       default 1 if ARCH_LS1043A
+       default 2
+       help
+         This is the divider that is used to derive QMAN clock from Platform
+         clock, in another word QMAN_clk = Platform_clk / this_divider.
 endmenu
 
 config RESV_RAM
index 4afc046eeaf968660ad003626f1add7fe059b3cc..fc9de73bcef4ce3ee58bdb18ead0f2f3113c9c3d 100644 (file)
@@ -414,8 +414,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
                ccsr_sec_t __iomem *sec;
 
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
-               if (fdt_fixup_kaslr(blob))
-                       fdt_fixup_remove_jr(blob);
+               fdt_fixup_remove_jr(blob);
+               fdt_fixup_kaslr(blob);
 #endif
 
                sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
index 8386678c468afdc9caa3561b6eddb2cc5e62d06a..723d7eac5dd2d9ec72a0cfffcce60679f22226a9 100644 (file)
@@ -155,7 +155,9 @@ void get_sys_info(struct sys_info *sys_info)
                                                CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
-       sys_info->freq_qman = sys_info->freq_systembus;
+       sys_info->freq_qman = (sys_info->freq_systembus /
+                               CONFIG_SYS_FSL_PCLK_DIV) /
+                               CONFIG_SYS_FSL_QMAN_CLK_DIV;
 #endif
 }
 
index e9d373e4641fa4863cd33cd5f5225a8521956c61..ef3987ea84818082acd4ec6c897834ca5ad0a127 100644 (file)
@@ -233,39 +233,45 @@ ENTRY(lowlevel_init)
         * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
         *       placeholders.
         */
-#ifdef CONFIG_FSL_TZASC_1
-       ldr     x1, =TZASC_GATE_KEEPER(0)
-       ldr     w0, [x1]                /* Filter 0 Gate Keeper Register */
-       orr     w0, w0, #1 << 0         /* Set open_request for Filter 0 */
-       str     w0, [x1]
 
-       ldr     x1, =TZASC_REGION_ATTRIBUTES_0(0)
-       ldr     w0, [x1]                /* Region-0 Attributes Register */
-       orr     w0, w0, #1 << 31        /* Set Sec global write en, Bit[31] */
-       orr     w0, w0, #1 << 30        /* Set Sec global read en, Bit[30] */
-       str     w0, [x1]
+.macro tzasc_prog, xreg
+
+       mov     x12, TZASC1_BASE
+       mov     x16, #0x10000
+       mul     x14, \xreg, x16
+       add     x14, x14,x12
+       mov     x1, #0x8
+       add     x1, x1, x14
+
+       ldr     w0, [x1]                /* Filter 0 Gate Keeper Register */
+       orr     w0, w0, #1 << 0         /* Set open_request for Filter 0 */
+       str     w0, [x1]
+
+       mov     x1, #0x110
+       add     x1, x1, x14
+
+       ldr     w0, [x1]                /* Region-0 Attributes Register */
+       orr     w0, w0, #1 << 31        /* Set Sec global write en, Bit[31] */
+       orr     w0, w0, #1 << 30        /* Set Sec global read en, Bit[30] */
+       str     w0, [x1]
+
+       mov     x1, #0x114
+       add     x1, x1, x14
+
+       ldr     w0, [x1]                /* Region-0 Access Register */
+       mov     w0, #0xFFFFFFFF         /* Set nsaid_wr_en and nsaid_rd_en */
+       str     w0, [x1]
+.endm
+
+#ifdef CONFIG_FSL_TZASC_1
+       mov     x13, #0
+       tzasc_prog      x13
 
-       ldr     x1, =TZASC_REGION_ID_ACCESS_0(0)
-       ldr     w0, [x1]                /* Region-0 Access Register */
-       mov     w0, #0xFFFFFFFF         /* Set nsaid_wr_en and nsaid_rd_en */
-       str     w0, [x1]
 #endif
 #ifdef CONFIG_FSL_TZASC_2
-       ldr     x1, =TZASC_GATE_KEEPER(1)
-       ldr     w0, [x1]                /* Filter 0 Gate Keeper Register */
-       orr     w0, w0, #1 << 0         /* Set open_request for Filter 0 */
-       str     w0, [x1]
-
-       ldr     x1, =TZASC_REGION_ATTRIBUTES_0(1)
-       ldr     w0, [x1]                /* Region-1 Attributes Register */
-       orr     w0, w0, #1 << 31        /* Set Sec global write en, Bit[31] */
-       orr     w0, w0, #1 << 30        /* Set Sec global read en, Bit[30] */
-       str     w0, [x1]
+       mov     x13, #1
+       tzasc_prog      x13
 
-       ldr     x1, =TZASC_REGION_ID_ACCESS_0(1)
-       ldr     w0, [x1]                /* Region-1 Attributes Register */
-       mov     w0, #0xFFFFFFFF         /* Set nsaid_wr_en and nsaid_rd_en */
-       str     w0, [x1]
 #endif
        isb
        dsb     sy
index 06fdd17604986151bee11b312da051af0c101ca2..bfd663942aa23140741ef8ceadc795bdd4045274 100644 (file)
@@ -517,6 +517,7 @@ static void erratum_a010539(void)
        porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
        out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
                 porsr1);
+       out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
 #endif
 }
 
index 6a04eaca3eb977fa01449d6796842ed41a8411d9..a13c92e246a8a22c0ea6a12e91ee92756acd93b8 100644 (file)
@@ -115,25 +115,48 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
                                            u32 *loadable_l, u32 *loadable_h)
 {
        phys_addr_t sec_firmware_loadable_addr = 0;
-       int conf_node_off, ld_node_off;
+       int conf_node_off, ld_node_off, images;
        char *conf_node_name = NULL;
        const void *data;
        size_t size;
        ulong load;
+       const char *name, *str, *type;
+       int len;
 
        conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
 
        conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
        if (conf_node_off < 0) {
                printf("SEC Firmware: %s: no such config\n", conf_node_name);
-       return -ENOENT;
+               return -ENOENT;
+       }
+
+       /* find the node holding the images information */
+       images = fdt_path_offset(sec_firmware_img, FIT_IMAGES_PATH);
+       if (images < 0) {
+               printf("%s: Cannot find /images node: %d\n", __func__, images);
+               return -1;
+       }
+
+       type = FIT_LOADABLE_PROP;
+
+       name = fdt_getprop(sec_firmware_img, conf_node_off, type, &len);
+       if (!name) {
+               /* Loadables not present */
+               return 0;
        }
 
-       ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
-                                            FIT_LOADABLE_PROP);
-       if (ld_node_off >= 0) {
-               printf("SEC Firmware: '%s' present in config\n",
-                      FIT_LOADABLE_PROP);
+       printf("SEC Firmware: '%s' present in config\n", type);
+
+       for (str = name; str && ((str - name) < len);
+            str = strchr(str, '\0') + 1) {
+               printf("%s: '%s'\n", type, str);
+               ld_node_off = fdt_subnode_offset(sec_firmware_img, images, str);
+               if (ld_node_off < 0) {
+                       printf("cannot find image node '%s': %d\n", str,
+                              ld_node_off);
+                       return -EINVAL;
+               }
 
                /* Verify secure firmware image */
                if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
@@ -163,11 +186,19 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
                memcpy((void *)sec_firmware_loadable_addr, data, size);
                flush_dcache_range(sec_firmware_loadable_addr,
                                   sec_firmware_loadable_addr + size);
-       }
 
-       /* Populate address ptrs for loadable image with loadbale addr */
-       out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
-       out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
+               /* Populate loadable address only for Trusted OS */
+               if (!strcmp(str, "trustedOS@1")) {
+                       /*
+                        * Populate address ptrs for loadable image with
+                        * loadbale addr
+                        */
+                       out_le32(loadable_l, (sec_firmware_loadable_addr &
+                                             WORD_MASK));
+                       out_le32(loadable_h, (sec_firmware_loadable_addr >>
+                                             WORD_SHIFT));
+               }
+       }
 
        return 0;
 }
@@ -317,9 +348,7 @@ unsigned int sec_firmware_support_psci_version(void)
  */
 bool sec_firmware_support_hwrng(void)
 {
-       uint8_t rand[8];
        if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
-               if (!sec_firmware_get_random(rand, 8))
                        return true;
        }
 
@@ -428,8 +457,10 @@ int fdt_fixup_kaslr(void *fdt)
 
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)
        /* Check if random seed generation is  supported */
-       if (sec_firmware_support_hwrng() == false)
+       if (sec_firmware_support_hwrng() == false) {
+               printf("WARNING: SEC firmware not running, no kaslr-seed\n");
                return 0;
+       }
 
        ret = sec_firmware_get_random(rand, 8);
        if (ret < 0) {
index 5d212f35b56c97506e37c3e2ee36c88aa173c554..d37e1ccf1e7fdfae016fb92e9c55be046a2655d0 100644 (file)
        .globl  __secondary_start_page
        .align  12
 __secondary_start_page:
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
+       msync
+       isync
+       mfspr   r3, SPRN_HDBCR0
+       oris    r3, r3, 0x0080
+       mtspr   SPRN_HDBCR0, r3
+#endif
 /* First do some preliminary setup */
        lis     r3, HID0_EMCP@h         /* enable machine check */
 #ifndef CONFIG_E500MC
index 764ed7945b31ded3a77a1aa37afc9a82f4250c32..b35c4ae2dad47ba114a021a7663269f8cb02eaac 100644 (file)
@@ -30,12 +30,12 @@ static const struct board_specific_parameters udimm0[] = {
 #if defined(CONFIG_TARGET_LS1088ARDB)
 
        {2,  1666, 0, 8,     8, 0x090A0B0E, 0x0F10110D,},
-       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  1900, 0, 8,     9, 0x0A0B0C10, 0x1112140E,},
        {2,  2300, 0, 8,     9, 0x0A0C0E11, 0x1214160F,},
        {}
 #elif defined(CONFIG_TARGET_LS1088AQDS)
        {2,  1666, 0, 8,     8, 0x0A0A0C0E, 0x0F10110C,},
-       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  1900, 0, 8,     9, 0x0A0B0C10, 0x1112140E,},
        {2,  2300, 0, 4,     9, 0x0A0C0D11, 0x1214150E,},
        {}
 
index 9907fd2a33fe10e67aae0447dde5d5990920fc6c..40b1a0e63109237f536b3eac4c0a18df12d26698 100644 (file)
@@ -4,12 +4,14 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/fsl_serdes.h>
 #include <hwconfig.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
+#include <phy.h>
 #include <fm_eth.h>
 #include <i2c.h>
 #include <miiphy.h>
index f20dc3e0e516194af4fb79a9201135ccc00ea707..05dc2ac44683fbc37ea53e0280aa086f5821ba07 100644 (file)
@@ -8,9 +8,12 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
index be3e0981d8b57e3eb480281ff03b68ebdd230eb2..20376be2d1f7b5d62ffba237168af8a376900056 100644 (file)
@@ -11,9 +11,12 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
index cea6ca987b94cabca6734000f8be7618ced754d2..cf2b4e3aba8151f75ae4a0a9f8b91d521f36f0ff 100644 (file)
@@ -10,9 +10,12 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
index 76ee1204bc41510ca8762378a24106ebb27fb492..39fa3d716f5399e2a8f9429427d8fd69659f3ac1 100644 (file)
@@ -13,6 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
@@ -21,6 +23,7 @@ CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
index ddb1e04556bffade634cf88b6039ce14a325f0cc..8d854da3dd623db0b28a87cdc4971afdc4445e11 100644 (file)
@@ -15,6 +15,8 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
 CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -23,6 +25,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
index 23e064b9e4622fe1ec6d44ad2efd321da67ea90f..db952897334ce1cfa2af2afae0ea9732b1f77a24 100644 (file)
@@ -11,9 +11,12 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
index b05d50ade6f55c5694ba77ecfc3e0ffcaeb35de5..fbb75df7a31997a5ca5c872d7cf0a1de63badadf 100644 (file)
@@ -10,9 +10,12 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
index 43472ac2a13aea4525320f1b79b5a96099900a8c..17791b07ebbe4c5d1be07db86adc66e36c5169d5 100644 (file)
@@ -16,6 +16,8 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
 CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -26,6 +28,7 @@ CONFIG_SPL_HASH_SUPPORT=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
index 91fae2cd6ad120d873d46ea965d6118f0c63593c..26966aa7a933088a17346dd0fcdb9a0c35e63164 100644 (file)
@@ -15,6 +15,8 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
 CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -23,6 +25,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
diff --git a/doc/uImage.FIT/sec_firmware_ppa.its b/doc/uImage.FIT/sec_firmware_ppa.its
new file mode 100644 (file)
index 0000000..a7acde1
--- /dev/null
@@ -0,0 +1,49 @@
+/dts-v1/;
+
+/*
+ * Example FIT image description file demonstrating the usage
+ * of SEC Firmware and multiple loadable images loaded by the u-boot.
+ * For booting PPA (SEC Firmware), "firmware" is searched and loaded.
+ *
+ * Multiple binaries will be loaded as "loadables" (if present) at their
+ * respective load offsets from firmware image address.
+ */
+
+/{
+       description = "PPA Firmware";
+       #address-cells = <1>;
+       images {
+               firmware@1 {
+                       description = "PPA Firmware: <version>";
+                       data = /incbin/("../obj/monitor.bin");
+                       type = "firmware";
+                       arch = "arm64";
+                       compression = "none";
+               };
+               trustedOS@1 {
+                       description = "Trusted OS";
+                       data = /incbin/("../../tee.bin");
+                       type = "OS";
+                       arch = "arm64";
+                       compression = "none";
+                       load = <0x00200000>;
+               };
+               fuse_scr {
+                       description = "Fuse Script";
+                       data = /incbin/("../../fuse_scr.bin");
+                       type = "firmware";
+                       arch = "arm64";
+                       compression = "none";
+                       load = <0x00180000>;
+               };
+       };
+
+       configurations {
+               default = "config-1";
+               config-1 {
+                       description = "PPA Secure firmware";
+                       firmware = "firmware@1";
+                       loadables = "trustedOS@1", "fuse_scr";
+               };
+       };
+};
index a82913cac13cd6e2e9e720dcc4106a4d0c5d1b25..a47226bd2158106bb4efaa2eac556faad82c60af 100644 (file)
@@ -269,14 +269,9 @@ static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 
 /* returns nonzero if entire page is blank */
 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
-                         u32 *eccstat, unsigned int bufnum)
+                         u32 eccstat, unsigned int bufnum)
 {
-       u32 reg = eccstat[bufnum / 4];
-       int errors;
-
-       errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
-
-       return errors;
+       return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
 }
 
 /*
@@ -290,7 +285,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
        struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
        u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
        u32 time_start;
-       u32 eccstat[8] = {0};
+       u32 eccstat;
        int i;
 
        /* set the chip select for NAND Transaction */
@@ -320,20 +315,17 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
        if (ctrl->eccread) {
                int errors;
                int bufnum = ctrl->page & priv->bufnum_mask;
-               int sector = bufnum * chip->ecc.steps;
-               int sector_end = sector + chip->ecc.steps - 1;
-
-               for (i = sector / 4; i <= sector_end / 4; i++) {
-                       if (i >= ARRAY_SIZE(eccstat)) {
-                               printf("%s: eccstat too small for %d\n",
-                                      __func__, i);
-                               return -EIO;
-                       }
+               int sector_start = bufnum * chip->ecc.steps;
+               int sector_end = sector_start + chip->ecc.steps - 1;
+               u32 *eccstat_regs;
 
-                       eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
-               }
+               eccstat_regs = ifc->ifc_nand.nand_eccstat;
+               eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
+
+               for (i = sector_start; i <= sector_end; i++) {
+                       if ((i != sector_start) && !(i % 4))
+                               eccstat = ifc_in32(&eccstat_regs[i / 4]);
 
-               for (i = sector; i <= sector_end; i++) {
                        errors = check_read_ecc(mtd, ctrl, eccstat, i);
 
                        if (errors == 15) {
@@ -708,6 +700,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
        struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
        u32 nand_fsr;
+       int status;
 
        if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
                return NAND_STATUS_FAIL;
@@ -728,10 +721,10 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
                return NAND_STATUS_FAIL;
 
        nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
+       status = nand_fsr >> 24;
 
        /* Chip sometimes reporting write protect even when it's not */
-       nand_fsr = nand_fsr | NAND_STATUS_WP;
-       return nand_fsr;
+       return status | NAND_STATUS_WP;
 }
 
 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
index 327bee935a1f8d59be5ffc69d94b28b26f0ae14e..c609efb9abcc3ade14d4d74d602b034771ae43bc 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 #include <fsl-mc/fsl_mc_sys.h>
index 0bbb76072818c673c3b5837ab39662b4b34d1841..8884455963de63109cc08acee3a217f50b0d2c86 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 
index 2aadd4ada2bf6c6dbdcfa0eb533e2009c909e006..43a2ff43f8883baec29bfda6c7601b2c29a60de1 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
  */
index 5cf5eebea6e3bbc5b77a138835829dbb373a6abd..443e430695ec579589b37ecdde275f72a9b03716 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 
index 38d19a4063e6d6cbdb812e092644aa31cf6b8a9e..e0a2865ab8f55b2d51125b50674bb517a223707b 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 
index 9e6f27afdc7af9ef5b7b77d407167711bbdfdf33..e18c88da09729daee7acc0b277c39bd49032dfe4 100644 (file)
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+/* Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 #ifndef __FSL_DPMNG_CMD_H
index 58612cfca3d30250dc79fb8be20e82ccec278ac2..982024e31ea1f4cf782d65a6a972f0bf88c9b90b 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2017 NXP Semiconductors
- * Copyright (C) 2014 Freescale Semiconductor
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  */
 #include <common.h>
 #include <errno.h>
index 8688dd44199f3f47a6737b3f42f4e9a41d498200..79facb4a445a9b4c7f04072cbdcf5e3d494db597 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 
index 54cb633e0141ed004561e0d5c5e5fd770baeb9df..ee784a55ee1e6f703e0630d782a891bf529ba9d0 100644 (file)
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 
index 79781b5d4a8e6352b7b0ae3f5ea96a67889f4c8f..368424948478e0691dafbe3e5faa123c7b411537 100644 (file)
@@ -155,6 +155,25 @@ static void qspi_write32(u32 flags, u32 *addr, u32 val)
                out_be32(addr, val) : out_le32(addr, val);
 }
 
+static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
+{
+       u32 val;
+       const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
+                        QSPI_SR_IP_ACC_MASK;
+       unsigned int retry = 5;
+
+       do {
+               val = qspi_read32(priv->flags, &priv->regs->sr);
+
+               if ((~val & mask) == mask)
+                       return 0;
+
+               udelay(1);
+       } while (--retry);
+
+       return -ETIMEDOUT;
+}
+
 /* QSPI support swapping the flash read/write data
  * in hardware for LS102xA, but not for VF610 */
 static inline u32 qspi_endian_xchg(u32 data)
@@ -1017,11 +1036,7 @@ static int fsl_qspi_probe(struct udevice *bus)
        priv->num_chipselect = plat->num_chipselect;
 
        /* make sure controller is not busy anywhere */
-       ret = wait_for_bit_le32(&priv->regs->sr,
-                               QSPI_SR_BUSY_MASK |
-                               QSPI_SR_AHB_ACC_MASK |
-                               QSPI_SR_IP_ACC_MASK,
-                               false, 100, false);
+       ret = is_controller_busy(priv);
 
        if (ret) {
                debug("ERROR : The controller is busy\n");
@@ -1184,11 +1199,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
        priv = dev_get_priv(bus);
 
        /* make sure controller is not busy anywhere */
-       ret = wait_for_bit_le32(&priv->regs->sr,
-                               QSPI_SR_BUSY_MASK |
-                               QSPI_SR_AHB_ACC_MASK |
-                               QSPI_SR_IP_ACC_MASK,
-                               false, 100, false);
+       ret = is_controller_busy(priv);
 
        if (ret) {
                debug("ERROR : The controller is busy\n");
index 0df90161d7552b14095452983b9a70bdc1fb6a60..ea48421bbebc1c7d897fe340e16756a160a45409 100644 (file)
@@ -148,7 +148,6 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE           (512UL * 1024 * 1024)
 #endif
 /* Command line configuration */
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_CACHE
 
 /* Miscellaneous configurable options */
@@ -195,10 +194,6 @@ unsigned long long get_qixis_addr(void);
        "mcinitcmd=fsl_mc start mc 0x580a00000" \
        " 0x580e00000 \0"
 
-#define CONFIG_BOOTARGS                "console=ttyS0,115200 root=/dev/ram0 " \
-                               "earlycon=uart8250,mmio,0x21c0500 " \
-                               "ramdisk_size=0x3000000 default_hugepagesz=2m" \
-                               " hugepagesz=2m hugepages=256"
 #if defined(CONFIG_QSPI_BOOT)
 #define CONFIG_BOOTCOMMAND     "sf probe 0:0;" \
                                "sf read 0x80200000 0xd00000 0x100000;"\
index 8d7c14d97dbfa046255ed750fc77000368481476..2278ac952ea94d50962e72f3f59cb903badb6e62 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 /*!
index c300c94e202b4921cc8a40e7108f4936b2d9584d..7788e1962e6448fb77f17005791712cb6a4dcb70 100644 (file)
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 
index 66cf3bf6a2158fb0d2f5d641baead1cd154f9522..1cea123a316498b860b24494ca7d04194e9a92e4 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
  */
index 309d323acf7185841239e9bd4fc377dfec900bec..96d81d9934917254e021b33bc58d888fb1d03ee3 100644 (file)
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 #ifndef _FSL_DPNI_H
index 779d6f95672d7cf2b884d4e37de8677849cad297..950ecb0756980f3281c4a073fc89f7f410c2df49 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 #ifndef _FSL_DPRC_H
index 179f6698283154d2c12b65db73e6ac5d7e20afc5..591cda9685155094d60604fc11c3f3d7c1a5f3d9 100644 (file)
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+/* Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 #ifndef __FSL_MC_CMD_H
index f4b5a99e15de26be930c290c9d0198bbaa374557..ba0bc379d5b8b3690888868a47a815bb3ab8a75d 100644 (file)
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 
index d051e92ce4c0085ac17443f596ecf8080ffe1144..8120ca0de8652bdd8aad0140811bc0c733985ed3 100644 (file)
@@ -891,8 +891,8 @@ struct fsl_ifc_nand {
        u32 nand_erattr1;
        u32 res19[0x10];
        u32 nand_fsr;
-       u32 res20[0x3];
-       u32 nand_eccstat[6];
+       u32 res20[0x1];
+       u32 nand_eccstat[8];
        u32 res21[0x1c];
        u32 nanndcr;
        u32 res22[0x2];