]> git.sur5r.net Git - u-boot/commitdiff
board/b4qds:Add support of 2 stage NAND boot-loader
authorPrabhakar Kushwaha <prabhakar@freescale.com>
Tue, 8 Apr 2014 13:43:44 +0000 (19:13 +0530)
committerYork Sun <yorksun@freescale.com>
Wed, 23 Apr 2014 00:58:51 +0000 (17:58 -0700)
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
  - Add spl.c which defines board_init_f, board_init_r
  - update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/freescale/b4860qds/Makefile
board/freescale/b4860qds/ddr.c
board/freescale/b4860qds/spl.c [new file with mode: 0644]
board/freescale/b4860qds/tlb.c
boards.cfg
doc/README.b4860qds
include/configs/B4860QDS.h

index e5cc054a01510a66bd699b1a84711d4e99853ac6..0acd2a9aa4a02e3ad2b495ecb80e61610f644aff 100644 (file)
@@ -4,9 +4,14 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-y  += b4860qds.o
-obj-y  += ddr.o
 obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
-obj-$(CONFIG_PCI)      += pci.o
+obj-$(CONFIG_PCI)      += pci.o
+endif
+
+obj-y  += ddr.o
 obj-y  += law.o
 obj-y  += tlb.o
index 187c3b3ebcae5092868c1f72a50c621cab47f96d..2c17156586dfa20ae5542039070845441379d15f 100644 (file)
@@ -179,6 +179,7 @@ phys_size_t initdram(int board_type)
 {
        phys_size_t dram_size;
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
        puts("Initializing....using SPD\n");
 
        dram_size = fsl_ddr_sdram();
@@ -186,7 +187,9 @@ phys_size_t initdram(int board_type)
        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
        dram_size *= 0x100000;
 
-       puts("    DDR: ");
+#else
+       dram_size =  fsl_ddr_sdram_size();
+#endif
        return dram_size;
 }
 
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
new file mode 100644 (file)
index 0000000..3aa5a78
--- /dev/null
@@ -0,0 +1,114 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+       return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+       u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch ((sysclk_conf & 0x0C) >> 2) {
+       case QIXIS_CLK_100:
+               return 100000000;
+       case QIXIS_CLK_125:
+               return 125000000;
+       case QIXIS_CLK_133:
+               return 133333333;
+       }
+       return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+       u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch (ddrclk_conf & 0x03) {
+       case QIXIS_CLK_100:
+               return 100000000;
+       case QIXIS_CLK_125:
+               return 125000000;
+       case QIXIS_CLK_133:
+               return 133333333;
+       }
+       return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+       u32 plat_ratio, sys_clk, uart_clk;
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+       /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+       memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+       /* Update GD pointer */
+       gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+       /* compiler optimization barrier needed for GCC >= 3.4 */
+       __asm__ __volatile__("" : : : "memory");
+
+       console_init_f();
+
+       /* initialize selected port with appropriate baud rate */
+       sys_clk = get_board_sys_clk();
+       plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+       uart_clk = sys_clk * plat_ratio / 2;
+
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                    uart_clk / 16 / CONFIG_BAUDRATE);
+
+       relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       bd_t *bd;
+
+       bd = (bd_t *)(gd + sizeof(gd_t));
+       memset(bd, 0, sizeof(bd_t));
+       gd->bd = bd;
+       bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+       bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+       probecpu();
+       get_clocks();
+       mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+                       CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+       env_init();
+       env_relocate();
+#else
+       /* relocate environment function pointers etc. */
+       nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                           (uchar *)CONFIG_ENV_ADDR);
+       gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+       gd->env_valid = 1;
+#endif
+
+       i2c_init_all();
+
+       puts("\n\n");
+
+       gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+       nand_boot();
+#endif
+}
index 00798a1c190da6ac3350b436e44df26f1468f3fb..7b55b860d088f00a85a3d301dd2bf4cb995552a1 100644 (file)
@@ -62,6 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                      0, 2, BOOKE_PAGESZ_256M, 1),
 
+#ifndef CONFIG_SPL_BUILD
        /* *I*G* - PCI */
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 9, BOOKE_PAGESZ_16M, 1),
 #endif
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
        SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * entry 14 and 15 has been used hard coded, they will be disabled
         * in cpu_init_f, so we use entry 16 for SRIO2.
         */
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_SYS_SRIO1_MEM_PHYS
        /* *I*G* - SRIO1 */
        SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
@@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
                      0, 17, BOOKE_PAGESZ_1M, 1),
 #endif
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 17, BOOKE_PAGESZ_2G, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 03be0a6ba3eb2d38aa3f09c16fee07ce541a5ecc..c01f1917fdfdfbf6749e7480072e85a8d762c140 100644 (file)
@@ -741,11 +741,11 @@ Active  powerpc     mpc85xx        -           -               sbc8548
 Active  powerpc     mpc85xx        -           -               socrates            socrates                             -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           exmeritus       hww1u1a             HWW1U1A                              -                                                                                                                                 Kyle Moffett <Kyle.D.Moffett@boeing.com>
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS                             B4860QDS:PPC_B4420                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_NAND                        B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_NAND                        B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND                                                                      -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_SPIFLASH                    B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS                             B4860QDS:PPC_B4860                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SECURE_BOOT                 B4860QDS:PPC_B4860,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>
-Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_NAND                        B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_NAND                        B4860QDS:PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SPIFLASH                    B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SRIO_PCIE_BOOT              B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       bsc9131rdb          BSC9131RDB_NAND                      BSC9131RDB:BSC9131RDB,NAND                                                                                                        Poonam Aggrwal <poonam.aggrwal@freescale.com>
index 3da77d9f0f83a000e1676cf00d11c553cc4ed046..eada0c7dd89b55d7be39bc500c241dd491e6eaa4 100644 (file)
@@ -328,3 +328,39 @@ The below commands apply to both B4860QDS and B4420QDS.
    On Linux the interfaces are renamed as:
        . eth2 -> fm1-gb2
        . eth3 -> fm1-gb3
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+u-boot(768 KB) from flash to DDR.
+Finally SPL transer control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+ Run time view of SPL framework during  boot :-
+ -----------------------------------------------
+ Area        | Address                         |
+-----------------------------------------------
+ Secure boot | 0xFFFC0000 (32KB)               |
+ headers     |                                 |
+ -----------------------------------------------
+ GD, BD      | 0xFFFC8000 (4KB)                |
+ -----------------------------------------------
+ ENV         | 0xFFFC9000 (8KB)                |
+ -----------------------------------------------
+ HEAP        | 0xFFFCB000 (30KB)               |
+ -----------------------------------------------
+ STACK       | 0xFFFD8000 (22KB)               |
+ -----------------------------------------------
+ U-boot SPL  | 0xFFFD8000 (160KB)              |
+ -----------------------------------------------
+
+NAND Flash memory Map on B4860 and B4420QDS
+------------------------------------------
+ Start          End            Definition                      Size
+0x000000       0x0FFFFF        u-boot                          1MB
+0x140000       0x15FFFF        u-boot env                      128KB
+0x1A0000       0x1BFFFF        FMAN Ucode                      128KB
index b9ec9573db07e6154fe8d5a2304a41538a5ca0a9..0831a98a74fc3ec07e7e3e82309d1f3b388ed74b 100644 (file)
 #define CONFIG_PHYS_64BIT
 
 #ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
+#ifndef CONFIG_NAND
 #define CONFIG_RAMBOOT_TEXT_BASE       CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/b4860qds/b4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/b4860qds/b4_rcw.cfg
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE           0x00201000
+#define CONFIG_SPL_TEXT_BASE           0xFFFD8000
+#define CONFIG_SPL_PAD_TO              0x40000
+#define CONFIG_SPL_MAX_SIZE            0x28000
+#define RESET_VECTOR_OFFSET            0x27FFC
+#define BOOT_PAGE_OFFSET               0x27000
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST     0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 << 10)
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+#endif
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE                        CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET              (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_ENV_OFFSET              (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR                0xffe20000
@@ -164,7 +197,16 @@ unsigned long get_board_ddr_clk(void);
 /*
  *  Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR                CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR                0xFFFC0000
+#define CONFIG_SYS_L3_SIZE             256 << 10
+#define CONFIG_SPL_GD_ADDR             (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_NAND
+#define CONFIG_ENV_ADDR                        (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE   (30 << 10)
+#define CONFIG_SPL_RELOC_STACK         (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE    (22 << 10)
 
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_DCSRBAR             0xf0000000
@@ -193,7 +235,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_SYS_FSL_DDR3
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_FSL_DDR_INTERACTIVE
+#endif
 
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS1    0x51
@@ -381,7 +425,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
 
-#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
 
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
@@ -435,7 +483,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NS16550_COM3        (CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4        (CONFIG_SYS_CCSRBAR+0x11D600)
 #define CONFIG_SERIAL_MULTI            /* Enable both serial ports */
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV   /* determine from environment */
+#endif
 
 
 /* Use the HUSH parser */
@@ -607,7 +657,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FMAN_FW_ADDR        (512 * 1130)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR        (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR        (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing