Merge branch 'master' of git://git.denx.de/u-boot-video

diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 65a344d9cea4519b94ef5bac6a2fa9b39e2dca89..a82a3d89af64a531c7a29af276827f27989b2ff2 100644 (file)
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -319,6 +319,15 @@
                        };
                };
 
+               pwm: pwm@01c21400 {
+                       compatible = "allwinner,sun50i-a64-pwm",
+                                    "allwinner,sun5i-a13-pwm";
+                       reg = <0x01c21400 0x8>;
+                       clocks = <&osc24M>;
+                       #pwm-cells = <3>;
+                       status = "disabled";
+               };
+
                uart0: serial@1c28000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28000 0x400>;

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 3334fb51f02ea2502dbc60ce68a746f972925257..e4fe54d8b8d2101098b6edd2ddb6df203e120e01 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -172,6 +172,7 @@ enum sunxi_gpio_number {
 #define SUN8I_GPD_SDC1         3
 #define SUNXI_GPD_LCD0         2
 #define SUNXI_GPD_LVDS0                3
+#define SUNXI_GPD_PWM          2
 
 #define SUN5I_GPE_SDC2         3
 #define SUN8I_GPE_TWI2         3

diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h
index 47eb433fb6ddfad97c5e2c2d7b2143f6655c31b6..dca283c7a93aacb9b4f33ed558f487312c4b78d4 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/pwm.h
+++ b/arch/arm/include/asm/arch-sunxi/pwm.h
@@ -10,8 +10,15 @@
 #define SUNXI_PWM_CH0_PERIOD           (SUNXI_PWM_BASE + 4)
 
 #define SUNXI_PWM_CTRL_PRESCALE0(x)    ((x) & 0xf)
+#define SUNXI_PWM_CTRL_PRESCALE0_MASK  0xf
 #define SUNXI_PWM_CTRL_ENABLE0         (0x5 << 4)
 #define SUNXI_PWM_CTRL_POLARITY0(x)    ((x) << 5)
+#define SUNXI_PWM_CTRL_CH0_ACT_STA     BIT(5)
+#define SUNXI_PWM_CTRL_CLK_GATE                BIT(6)
+
+#define SUNXI_PWM_CH0_PERIOD_MAX       (0xffff)
+#define SUNXI_PWM_CH0_PERIOD_PRD(x)    ((x & 0xffff) << 16)
+#define SUNXI_PWM_CH0_PERIOD_DUTY(x)   ((x) & 0xffff)
 
 #define SUNXI_PWM_PERIOD_80PCT         0x04af03c0
 
@@ -30,4 +37,9 @@
 #define SUNXI_PWM_MUX                  SUN8I_GPH_PWM
 #endif
 
+struct sunxi_pwm {
+       u32 ctrl;
+       u32 ch0_period;
+};
+
 #endif

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e82755805247b07c787e8d2b05cb6e9a26b88cf2..2984b7976637caad4759149bd4fb19224989b5b1 100644 (file)
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -43,3 +43,10 @@ config PWM_TEGRA
          four channels with a programmable period and duty cycle. Only a
          32KHz clock is supported by the driver but the duty cycle is
          configurable.
+
+config PWM_SUNXI
+       bool "Enable support for the Allwinner Sunxi PWM"
+       depends on DM_PWM
+       help
+         This PWM is found on H3, A64 and other Allwinner SoCs. It supports a
+         programmable period and duty cycle. A 16-bit counter is used.

diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 16739e7fda3c97d296e683930eec87a4f8c80f28..a837c35ed2e3bee56a5e3a1b7754e2c8c0a31a00 100644 (file)
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_PWM_IMX)         += pwm-imx.o pwm-imx-util.o
 obj-$(CONFIG_PWM_ROCKCHIP)     += rk_pwm.o
 obj-$(CONFIG_PWM_SANDBOX)      += sandbox_pwm.o
 obj-$(CONFIG_PWM_TEGRA)                += tegra_pwm.o
+obj-$(CONFIG_PWM_SUNXI)                += sunxi_pwm.o

diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c
new file mode 100644 (file)
index 0000000..3c7dffd
--- /dev/null
+++ b/drivers/pwm/sunxi_pwm.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017-2018 Vasily Khoruzhick <anarsoul@gmail.com>
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <pwm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/gpio.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OSC_24MHZ 24000000
+
+struct sunxi_pwm_priv {
+       struct sunxi_pwm *regs;
+       bool invert;
+       u32 prescaler;
+};
+
+static const u32 prescaler_table[] = {
+       120,    /* 0000 */
+       180,    /* 0001 */
+       240,    /* 0010 */
+       360,    /* 0011 */
+       480,    /* 0100 */
+       0,      /* 0101 */
+       0,      /* 0110 */
+       0,      /* 0111 */
+       12000,  /* 1000 */
+       24000,  /* 1001 */
+       36000,  /* 1010 */
+       48000,  /* 1011 */
+       72000,  /* 1100 */
+       0,      /* 1101 */
+       0,      /* 1110 */
+       1,      /* 1111 */
+};
+
+static int sunxi_pwm_config_pinmux(void)
+{
+#ifdef CONFIG_MACH_SUN50I
+       sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
+#endif
+       return 0;
+}
+
+static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
+                               bool polarity)
+{
+       struct sunxi_pwm_priv *priv = dev_get_priv(dev);
+
+       debug("%s: polarity=%u\n", __func__, polarity);
+       priv->invert = polarity;
+
+       return 0;
+}
+
+static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
+                               uint period_ns, uint duty_ns)
+{
+       struct sunxi_pwm_priv *priv = dev_get_priv(dev);
+       struct sunxi_pwm *regs = priv->regs;
+       int prescaler;
+       u32 v, period = 0, duty;
+       u64 scaled_freq = 0;
+       const u32 nsecs_per_sec = 1000000000U;
+
+       debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
+
+       for (prescaler = 0; prescaler < SUNXI_PWM_CTRL_PRESCALE0_MASK;
+            prescaler++) {
+               if (!prescaler_table[prescaler])
+                       continue;
+               scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
+               period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
+               if (period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX)
+                       break;
+       }
+
+       if (period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
+               debug("%s: failed to find prescaler value\n", __func__);
+               return -EINVAL;
+       }
+
+       duty = lldiv(scaled_freq * duty_ns, nsecs_per_sec);
+
+       if (priv->prescaler != prescaler) {
+               /* Mask clock to update prescaler */
+               v = readl(&regs->ctrl);
+               v &= ~SUNXI_PWM_CTRL_CLK_GATE;
+               writel(v, &regs->ctrl);
+               v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
+               v |= (priv->prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
+               writel(v, &regs->ctrl);
+               v |= SUNXI_PWM_CTRL_CLK_GATE;
+               writel(v, &regs->ctrl);
+               priv->prescaler = prescaler;
+       }
+
+       writel(SUNXI_PWM_CH0_PERIOD_PRD(period) |
+              SUNXI_PWM_CH0_PERIOD_DUTY(duty), &regs->ch0_period);
+
+       debug("%s: prescaler: %d, period: %d, duty: %d\n",
+             __func__, priv->prescaler,
+             period, duty);
+
+       return 0;
+}
+
+static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+       struct sunxi_pwm_priv *priv = dev_get_priv(dev);
+       struct sunxi_pwm *regs = priv->regs;
+       u32 v;
+
+       debug("%s: Enable '%s'\n", __func__, dev->name);
+
+       v = readl(&regs->ctrl);
+       if (!enable) {
+               v &= ~SUNXI_PWM_CTRL_ENABLE0;
+               writel(v, &regs->ctrl);
+               return 0;
+       }
+
+       sunxi_pwm_config_pinmux();
+
+       if (priv->invert)
+               v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
+       else
+               v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
+       v |= SUNXI_PWM_CTRL_ENABLE0;
+       writel(v, &regs->ctrl);
+
+       return 0;
+}
+
+static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
+{
+       struct sunxi_pwm_priv *priv = dev_get_priv(dev);
+
+       priv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev);
+
+       return 0;
+}
+
+static int sunxi_pwm_probe(struct udevice *dev)
+{
+       return 0;
+}
+
+static const struct pwm_ops sunxi_pwm_ops = {
+       .set_invert     = sunxi_pwm_set_invert,
+       .set_config     = sunxi_pwm_set_config,
+       .set_enable     = sunxi_pwm_set_enable,
+};
+
+static const struct udevice_id sunxi_pwm_ids[] = {
+       { .compatible = "allwinner,sun5i-a13-pwm" },
+       { .compatible = "allwinner,sun50i-a64-pwm" },
+       { }
+};
+
+U_BOOT_DRIVER(sunxi_pwm) = {
+       .name   = "sunxi_pwm",
+       .id     = UCLASS_PWM,
+       .of_match = sunxi_pwm_ids,
+       .ops    = &sunxi_pwm_ops,
+       .ofdata_to_platdata     = sunxi_pwm_ofdata_to_platdata,
+       .probe          = sunxi_pwm_probe,
+       .priv_auto_alloc_size   = sizeof(struct sunxi_pwm_priv),
+};

diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index dbad0e2b24031cfbae0df25db50f7c7b84c3907f..229bd63c97c8222b3ddbfbbb1985ddca47140a0b 100644 (file)
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -401,11 +401,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
        /* set up hdmi_fc_invidconf */
        inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
 
-       inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
+       inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
                   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
                   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
 
-       inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
+       inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
                   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
                   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
 

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index c78e33b9473803479cf05afc098266af1e7fed60..9dbea649a0ff709da88a28c7859f9c9b60511f11 100644 (file)
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -303,10 +303,10 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 
        sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
 
-       if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
+       if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
                setbits_le32(&phy->pol, 0x200);
 
-       if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
+       if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
                setbits_le32(&phy->pol, 0x100);
 
        setbits_le32(&phy->ctrl, 0xf << 12);