return !!ibcr.fields.ver;
}
+static inline bool icache_enabled(void)
+{
+ if (!icache_exists())
+ return false;
+
+ return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE);
+}
+
static inline bool dcache_exists(void)
{
union bcr_di_cache dbcr;
return !!dbcr.fields.ver;
}
+static inline bool dcache_enabled(void)
+{
+ if (!dcache_exists())
+ return false;
+
+ return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE);
+}
+
static inline bool slc_exists(void)
{
if (is_isa_arcv2()) {
int icache_status(void)
{
- if (!icache_exists())
- return 0;
-
- if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
- return 0;
- else
- return 1;
+ return icache_enabled();
}
void icache_enable(void)
/* IC supports only invalidation */
static inline void __ic_entire_invalidate(void)
{
- if (!icache_status())
+ if (!icache_enabled())
return;
/* Any write to IC_IVIC register triggers invalidation of entire I$ */
int dcache_status(void)
{
- if (!dcache_exists())
- return 0;
-
- if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
- return 0;
- else
- return 1;
+ return dcache_enabled();
}
void dcache_enable(void)
{
int aux;
- if (!dcache_status())
+ if (!dcache_enabled())
return;
__before_dc_op(cacheop);
static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
const int cacheop)
{
- if (!dcache_status())
+ if (!dcache_enabled())
return;
__before_dc_op(cacheop);