#ifndef __GXBB_H__
#define __GXBB_H__
+#define GXBB_FIRMWARE_MEM_SIZE 0x1000000
+
+#define GXBB_AOBUS_BASE 0xc8100000
#define GXBB_PERIPHS_BASE 0xc8834400
#define GXBB_HIU_BASE 0xc883c000
#define GXBB_ETH_BASE 0xc9410000
+/* Always-On Peripherals registers */
+#define GXBB_AO_ADDR(off) (GXBB_AOBUS_BASE + ((off) << 2))
+
+#define GXBB_AO_SEC_GP_CFG0 GXBB_AO_ADDR(0x90)
+#define GXBB_AO_SEC_GP_CFG3 GXBB_AO_ADDR(0x93)
+#define GXBB_AO_SEC_GP_CFG4 GXBB_AO_ADDR(0x94)
+#define GXBB_AO_SEC_GP_CFG5 GXBB_AO_ADDR(0x95)
+
+#define GXBB_AO_MEM_SIZE_MASK 0xFFFF0000
+#define GXBB_AO_MEM_SIZE_SHIFT 16
+#define GXBB_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
+#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16
+#define GXBB_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
+
/* Peripherals registers */
#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
#include <asm/arch/sm.h>
#include <asm/armv8/mmu.h>
#include <asm/unaligned.h>
+#include <linux/sizes.h>
+#include <efi_loader.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-int dram_init_banksize(void)
+phys_size_t get_effective_memsize(void)
{
- /* Reserve first 16 MiB of RAM for firmware */
- gd->bd->bi_dram[0].start = 0x1000000;
- gd->bd->bi_dram[0].size = 0xf000000;
- /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
- gd->bd->bi_dram[1].start = 0x10000000;
- gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000;
- return 0;
+ /* Size is reported in MiB, convert it in bytes */
+ return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK)
+ >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M;
+}
+
+static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
+{
+ int ret;
+
+ ret = fdt_add_mem_rsv(fdt, start, size);
+ if (ret)
+ printf("Could not reserve zone @ 0x%llx\n", start);
+
+ if (IS_ENABLED(CONFIG_EFI_LOADER)) {
+ efi_add_memory_map(start,
+ ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
+ EFI_RESERVED_MEMORY_TYPE, false);
+ }
+}
+
+void meson_gx_init_reserved_memory(void *fdt)
+{
+ u64 bl31_size, bl31_start;
+ u64 bl32_size, bl32_start;
+ u32 reg;
+
+ /*
+ * Get ARM Trusted Firmware reserved memory zones in :
+ * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
+ * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
+ * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
+ */
+
+ reg = readl(GXBB_AO_SEC_GP_CFG3);
+
+ bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK)
+ >> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
+ bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
+
+ bl31_start = readl(GXBB_AO_SEC_GP_CFG5);
+ bl32_start = readl(GXBB_AO_SEC_GP_CFG4);
+
+ /*
+ * Early Meson GXBB Firmware revisions did not provide the reserved
+ * memory zones in the registers, keep fixed memory zone handling.
+ */
+ if (IS_ENABLED(CONFIG_MESON_GXBB) &&
+ !reg && !bl31_start && !bl32_start) {
+ bl31_start = 0x10000000;
+ bl31_size = 0x200000;
+ }
+
+ /* Add first 16MiB reserved zone */
+ meson_board_add_reserved_memory(fdt, 0, GXBB_FIRMWARE_MEM_SIZE);
+
+ /* Add BL31 reserved zone */
+ if (bl31_start && bl31_size)
+ meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
+
+ /* Add BL32 reserved zone */
+ if (bl32_start && bl32_size)
+ meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
}
void reset_cpu(ulong addr)
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