board/ls1021aqds: Add DDR4 support

LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index ed78c33e0a3ef4ffc19f84dbf16f81218a079ca6..a500b5bc3b6581b9e72a73998d8ee3ded1d55034 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -50,7 +50,11 @@
 #ifdef CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_VERY_BIG_RAM
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#else
 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3
+#endif
 #define CONFIG_SYS_FSL_DDR
 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE         ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
@@ -71,6 +75,7 @@
 #define CONFIG_MAX_CPUS                                2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
 #define CONFIG_NUM_DDR_CONTROLLERS             1
+#define CONFIG_SYS_FSL_DDR_VER                 FSL_DDR_VER_5_0
 #else
 #error SoC not defined
 #endif

diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
index 021d82b74d329171869d4c7cb5fdf121325cc315..ccf45131b8735da2a8081a6de39ddd1e393a7e54 100644 (file)
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -4,3 +4,4 @@ S:      Maintained
 F:     board/freescale/ls1021aqds/
 F:     include/configs/ls1021aqds.h
 F:     configs/ls1021aqds_nor_defconfig
+F:     configs/ls1021aqds_ddr4_nor_defconfig

diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 679c654fb57227f579e1c656afa515fd96099384..5898e337443ed790d64a7d2fee190c9b4f5d28c4 100644 (file)
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -79,7 +79,6 @@ found:
         */
        popts->wrlvl_override = 1;
        popts->wrlvl_sample = 0xf;
-       popts->cswl_override = DDR_CSWL_CS0;
 
        /*
         * Rtt and Rtt_WR override
@@ -89,9 +88,17 @@ found:
        /* Enable ZQ calibration */
        popts->zq_en = 1;
 
+#ifdef CONFIG_SYS_FSL_DDR4
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+                         DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+#else
+       popts->cswl_override = DDR_CSWL_CS0;
+
        /* DHC_EN =1, ODT = 75 Ohm */
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
 }
 
 #ifdef CONFIG_SYS_DDR_RAW_TIMING

diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h
index 16d87cbe82fd7fee9444ec31be11d96b2e5879f7..f819c99dbaaaba313ab3bd21540d33f8219c4b4b 100644 (file)
--- a/board/freescale/ls1021aqds/ddr.h
+++ b/board/freescale/ls1021aqds/ddr.h
@@ -30,6 +30,13 @@ static const struct board_specific_parameters udimm0[] = {
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
         */
+#ifdef CONFIG_SYS_FSL_DDR4
+       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+       {2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
+       {1,  1666, 0, 4,     8, 0x090A0B0B, 0x0C0D0E0C,},
+       {1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+       {1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
        {1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
        {1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
        {1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
@@ -39,6 +46,9 @@ static const struct board_specific_parameters udimm0[] = {
        {2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
        {2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
        {2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+#else
+#error DDR type not defined
+#endif
        {}
 };
 

diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
new file mode 100644 (file)
index 0000000..3c57481
--- /dev/null
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 657e3b6d48d646fe4f7f7d97d8708dba4ff85576..bb4781334537b579bc07b52ab76cba69f79b5ea6 100644 (file)
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -49,10 +49,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DDR_SPD
 #define SPD_EEPROM_ADDRESS             0x51
 #define CONFIG_SYS_SPD_BUS_NUM         0
-#define CONFIG_SYS_DDR_RAW_TIMING
 
 #define CONFIG_FSL_DDR_INTERACTIVE     /* Interactive debugging */
+#ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3            /* Use DDR3 memory */
+#define CONFIG_SYS_DDR_RAW_TIMING
+#endif
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   4