<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
-<?fileVersion 4.0.0?>\r
-\r
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
<storageModule moduleId="org.eclipse.cdt.core.settings">\r
<cconfiguration id="com.tasking.config.arm.abs.debug.1826238485">\r
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<configuration artifactExtension="abs" artifactName="RTOSDemo" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand=""${PRODDIR}/bin/rm" -rf" description="" id="com.tasking.config.arm.abs.debug.1826238485" name="Debug" parent="com.tasking.config.arm.abs.debug">\r
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<toolChain id="com.tasking.arm.abs.debug.30340712" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">\r
- <option id="com.tasking.arm.pluginVersion.2141845622" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.77.0.0" valueType="string"/>\r
+ <option id="com.tasking.arm.pluginVersion.2141845622" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.109.0.0" valueType="string"/>\r
<option id="com.tasking.arm.prodDir.157728853" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>\r
<option id="com.tasking.arm.cpu.1839436230" name="Processor:" superClass="com.tasking.arm.cpu" value="xmc4500x1024" valueType="string"/>\r
<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.1822567351" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>\r
- <builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.tasking.arm.builder.abs.debug.1973824774" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>\r
+ <builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.tasking.arm.builder.abs.debug.1973824774" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="unlimited" superClass="com.tasking.arm.builder.abs.debug"/>\r
<tool id="com.tasking.arm.cc.abs.debug.950672563" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">\r
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<option id="com.tasking.arm.cc.includePaths.181073230" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">\r
</option>\r
<option id="com.tasking.arm.cc.optimize.1219621169" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.0" valueType="enumerated"/>\r
<option id="com.tasking.arm.cc.globalTypeChecking.1886266211" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>\r
+ <option id="com.tasking.arm.cc.definedSymbols.1190877408" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">\r
+ <listOptionValue builtIn="false" value="PART_XMC4500"/>\r
+ </option>\r
<inputType id="com.tasking.arm.cppInputType.1974521058" name="C++" superClass="com.tasking.arm.cppInputType"/>\r
<inputType id="com.tasking.arm.cpp.cInputType.1635312661" name="C" superClass="com.tasking.arm.cpp.cInputType"/>\r
<inputType id="com.tasking.arm.cc.msInputType.1200945921" name="MS" superClass="com.tasking.arm.cc.msInputType"/>\r
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<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
<storageModule moduleId="com.tasking.toolInfo">\r
- <toolInfo>TASKING program builder v4.2r1 Build 063</toolInfo>\r
+ <toolInfo>TASKING program builder v4.4r1 Build 077</toolInfo>\r
+ <toolInfo>TASKING rm v0.0r0 Build 022</toolInfo>\r
</storageModule>\r
</cconfiguration>\r
<cconfiguration id="com.tasking.config.arm.abs.debug.1826238485.654381753">\r
<configuration artifactExtension="abs" artifactName="RTOSDemo" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand=""${PRODDIR}/bin/rm" -rf" description="" id="com.tasking.config.arm.abs.debug.1826238485.654381753" name="Optimised" parent="com.tasking.config.arm.abs.debug">\r
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<toolChain id="com.tasking.arm.abs.debug.88571467" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">\r
- <option id="com.tasking.arm.pluginVersion.2020974908" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.77.0.0" valueType="string"/>\r
+ <option id="com.tasking.arm.pluginVersion.2020974908" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.109.0.0" valueType="string"/>\r
<option id="com.tasking.arm.prodDir.543770190" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>\r
<option id="com.tasking.arm.cpu.407790444" name="Processor:" superClass="com.tasking.arm.cpu" value="xmc4500x1024" valueType="string"/>\r
<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.1538796444" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>\r
- <builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.tasking.arm.builder.abs.debug.362325101" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>\r
+ <builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.tasking.arm.builder.abs.debug.362325101" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="unlimited" superClass="com.tasking.arm.builder.abs.debug"/>\r
<tool id="com.tasking.arm.cc.abs.debug.2020315503" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">\r
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<option id="com.tasking.arm.cc.includePaths.179492897" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">\r
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>\r
</project-mappings>\r
</storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>\r
</cproject>\r
\r
REM Copy the files that define the common demo tasks.\r
copy %COMMON_SOURCE%\dynamic.c Common_Demo_Source\r
- copy %COMMON_SOURCE%\BlockQ.c Common_Demo_Source\r
- copy %COMMON_SOURCE%\death.c Common_Demo_Source\r
copy %COMMON_SOURCE%\blocktim.c Common_Demo_Source\r
- copy %COMMON_SOURCE%\semtest.c Common_Demo_Source\r
- copy %COMMON_SOURCE%\PollQ.c Common_Demo_Source\r
- copy %COMMON_SOURCE%\GenQTest.c Common_Demo_Source\r
copy %COMMON_SOURCE%\recmutex.c Common_Demo_Source\r
copy %COMMON_SOURCE%\sp_flop.c Common_Demo_Source\r
- copy %COMMON_SOURCE%\countsem.c Common_Demo_Source\r
- copy %COMMON_SOURCE%\integer.c Common_Demo_Source\r
+ copy %COMMON_SOURCE%\QueueSet.c Common_Demo_Source\r
+ copy %COMMON_SOURCE%\QueueOverwrite.c Common_Demo_Source\r
+ copy %COMMON_SOURCE%\GenQTest.c Common_Demo_Source\r
\r
REM Copy the common demo file headers.\r
copy %COMMON_INCLUDE%\*.h Common_Demo_Source\include\r
* executed from within the IDE! Once it has been executed, re-open or refresh \r
* the Eclipse project and remove the #error line below.\r
*/\r
-#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.\r
+//#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.\r
\r
#include <stdint.h>\r
extern uint32_t SystemCoreClock;\r
\r
#define configUSE_PREEMPTION 1\r
#define configUSE_IDLE_HOOK 0\r
-#define configUSE_TICK_HOOK 0\r
+#define configUSE_TICK_HOOK 1\r
#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) )\r
#define configMAX_TASK_NAME_LEN ( 10 )\r
#define configUSE_TRACE_FACILITY 1\r
#define configUSE_16_BIT_TICKS 0\r
#define configUSE_APPLICATION_TASK_TAG 0\r
#define configUSE_COUNTING_SEMAPHORES 1\r
#define configGENERATE_RUN_TIME_STATS 0\r
+#define configUSE_QUEUE_SETS 1\r
\r
/* Co-routine definitions. */\r
#define configUSE_CO_ROUTINES 0\r
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
- \r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
/* Normal assert() semantics without relying on the provision of an assert.h\r
header file. */\r
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ) __asm volatile( "NOP" ); }\r
\r
+/* Demo application specific settings. */\r
+#if defined( PART_XMC4500 )\r
+ /* Hardware includes. */\r
+ #include "XMC4500.h"\r
+ #include "System_XMC4500.h"\r
+\r
+ /* Configure pin P3.9 for the LED. */\r
+ #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )\r
+ /* To toggle the single LED */\r
+ #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 )\r
+#elif defined( PART_XMC4400 )\r
+ /* Hardware includes. */\r
+ #include "XMC4400.h"\r
+ #include "System_XMC4200.h"\r
+\r
+ /* Configure pin P5.2 for the LED. */\r
+ #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )\r
+ /* To toggle the single LED */\r
+ #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 )\r
+#elif defined( PART_XMC4200 )\r
+ /* Hardware includes. */\r
+ #include "XMC4200.h"\r
+ #include "System_XMC4200.h"\r
+\r
+ /* Configure pin P2.1 for the LED. */\r
+ #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL\r
+ /* To toggle the single LED */\r
+ #define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 )\r
+#else\r
+ #error Part number not specified in project options\r
+#endif\r
+\r
#endif /* FREERTOS_CONFIG_H */\r
\r
--- /dev/null
+/*\r
+** @(#)cstart.c 1.9 $E%\r
+**\r
+** Copyright 1997-2013 Altium BV *\r
+**\r
+** DESCRIPTION:\r
+**\r
+** The system startup code initializes the processor's registers\r
+** and the application C variables.\r
+**\r
+*/\r
+\r
+#pragma nomisrac\r
+#pragma profiling off /* prevent profiling information on cstart */\r
+#pragma optimize abcefgIJKlopRsUy /* preset optimization level */\r
+#pragma tradeoff 4 /* preset tradeoff level */\r
+#pragma runtime BCMSZ /* disable runtime error checking for cstart */\r
+#pragma warning 750 /* do not warn about unsaved registers */\r
+#pragma section .text=cstart /* use: .text.cstart as the section name */\r
+\r
+#include <stdlib.h>\r
+#include <dbg.h>\r
+\r
+#define VTOR (*(volatile unsigned int *)0xE000ED08)\r
+#define PREF_FCON (*(volatile unsigned int *)0x58002014)\r
+#define SCU_GCU_PEEN (*(volatile unsigned int *)0x5000413C)\r
+#define SCU_GCU_PEFLAG (*(volatile unsigned int *)0x50004150)\r
+\r
+/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock \r
+ tree setup. \r
+ \r
+ This decision routine defined here will always return TRUE.\r
+ \r
+ When overridden by a definition defined in DAVE code engine, this routine\r
+ returns FALSE indicating that the code engine has performed the clock setup\r
+*/ \r
+#pragma weak AllowPLLInitByStartup\r
+uint32_t AllowPLLInitByStartup( void )\r
+{\r
+ return 1;\r
+}\r
+\r
+\r
+\r
+extern unsigned char _lc_ub_stack[];\r
+extern unsigned char _lc_vtor_value[];\r
+\r
+#pragma weak exit\r
+#pragma extern _Exit\r
+#pragma extern main\r
+extern int main( int argc, char *argv[] );\r
+extern void SystemInit( void );\r
+extern void __init( void );\r
+#if __PROF_ENABLE__\r
+extern void __prof_init( void );\r
+#endif\r
+\r
+#ifdef __POSIX__\r
+extern void * _posix_boot_stack_top;\r
+extern int posix_main( void );\r
+#endif\r
+\r
+#ifdef __USE_ARGC_ARGV\r
+#ifndef __ARGCV_BUFSIZE\r
+#define __ARGCV_BUFSIZE 256\r
+#endif\r
+static char argcv[__ARGCV_BUFSIZE];\r
+#endif\r
+\r
+void __interrupt() __frame() Reset_Handler( void )\r
+{\r
+ /* Set flash wait states to 3 */\r
+ PREF_FCON = (PREF_FCON & 0xFFFFFFF0) | 0x00000003;\r
+ SCU_GCU_PEFLAG =0xFFFFFFFF; /* Clear existing parity errors if any */\r
+ SCU_GCU_PEEN = 0; /* Disable parity */\r
+\r
+ /*\r
+ * Anticipate possible ROM/RAM remapping\r
+ * by loading the 'real' program address.\r
+ */\r
+ __remap_pc();\r
+ /*\r
+ * Initialize stack pointer.\r
+ */\r
+ __setsp( _lc_ub_stack );\r
+ /*\r
+ * Call a user function which initializes hardware,\r
+ * such as ROM/RAM re-mapping or MMU configuration.\r
+ */\r
+ SystemInit();\r
+ /*\r
+ * Copy initialized sections from ROM to RAM\r
+ * and clear uninitialized data sections in RAM.\r
+ */\r
+ __init();\r
+ __asm( "_cptable_handled:" ); /* symbol may be used by debugger */\r
+\r
+ /*\r
+ * Load VTOR register with the actual vector table\r
+ * start address\r
+ */\r
+ VTOR = (unsigned int)_lc_vtor_value;\r
+ \r
+#ifdef __POSIX__\r
+ __setsp( _posix_boot_stack_top );\r
+#endif\r
+#if __PROF_ENABLE__\r
+ __prof_init();\r
+#endif\r
+#ifdef __POSIX__\r
+ exit( posix_main() );\r
+#elif defined __USE_ARGC_ARGV\r
+ exit( main( _argcv( argcv, __ARGCV_BUFSIZE ), (char **)argcv ) );\r
+#else\r
+ exit( main( 0, NULL ) );\r
+#endif\r
+ return;\r
+}\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_XMC4200.c\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the Infineon XMC4000 Device Series\r
+ * @version V3.0.1 Alpha\r
+ * @date 26. September 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <system_XMC4200.h>\r
+#include <XMC4200.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL 1\r
+#define SCU_CLOCK_BACK_UP_FACTORY 2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3\r
+\r
+\r
+#define HIB_CLOCK_FOSI 1 \r
+#define HIB_CLOCK_OSCULP 2\r
+\r
+\r
+\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+\r
+\r
+/*--------------------- Watchdog Configuration -------------------------------\r
+//\r
+// <e> Watchdog Configuration\r
+// <o1.0> Disable Watchdog\r
+//\r
+// </e>\r
+*/\r
+#define WDT_SETUP 1\r
+#define WDTENB_nVal 0x00000001\r
+\r
+/*--------------------- CLOCK Configuration -------------------------------\r
+//\r
+// <e> Main Clock Configuration\r
+// <o1.0..1> CPU clock divider\r
+// <0=> fCPU = fSYS \r
+// <1=> fCPU = fSYS / 2\r
+// <o2.0..1> Peripheral Bus clock divider\r
+// <0=> fPB = fCPU\r
+// <1=> fPB = fCPU / 2\r
+// <o3.0..1> CCU Bus clock divider\r
+// <0=> fCCU = fCPU\r
+// <1=> fCCU = fCPU / 2\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCK_SETUP 1\r
+#define SCU_CPUCLKCR_DIV 0x00000000\r
+#define SCU_PBCLKCR_DIV 0x00000000\r
+#define SCU_CCUCLKCR_DIV 0x00000000\r
+/* not avalible in config wizzard*/\r
+/* \r
+* mandatory clock parameters ************************************************** \r
+* \r
+* source for clock generation \r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) \r
+* \r
+**************************************************************************************/ \r
+// Selection of imput lock for PLL \r
+/*************************************************************************************/\r
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP\r
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS 80000000\r
+#define CLOCK_CRYSTAL_FREQUENCY 12000000 \r
+#define CLOCK_BACK_UP 24000000 \r
+ \r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */ \r
+/*************************************************************************************/\r
+#define SCU_OSC_HP_MODE 0xF0\r
+#define SCU_OSCHPWDGDIV 2 \r
+ \r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */ \r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz \r
+/*************************************************************************************/\r
+#define SCU_PLL_K1DIV 1\r
+#define SCU_PLL_K1DIV 1 \r
+#define SCU_PLL_K2DIV 5 \r
+#define SCU_PLL_PDIV 1 \r
+#define SCU_PLL_NDIV 79 \r
+ \r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define SCU_PLL_K1DIV 1 \r
+//#define SCU_PLL_K2DIV 5 \r
+//#define SCU_PLL_PDIV 3 \r
+//#define SCU_PLL_NDIV 79 \r
+/*************************************************************************************/\r
+ \r
+\r
+/*--------------------- USB CLOCK Configuration ---------------------------\r
+//\r
+// <e> USB Clock Configuration\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_USB_CLOCK_SETUP 0\r
+/* not avalible in config wizzard*/\r
+#define SCU_USBPLL_PDIV 0 \r
+#define SCU_USBPLL_NDIV 31 \r
+#define SCU_USBDIV 3 \r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+// <o1.0..3> Flash Wait State\r
+// <0=> 3 WS\r
+// <1=> 4 WS\r
+// <2=> 5 WS \r
+// <3=> 6 WS\r
+// </e>\r
+// \r
+*/\r
+\r
+#define PMU_FLASH 1\r
+#define PMU_FLASH_WS 0x00000000\r
+\r
+\r
+/*--------------------- CLOCKOUT Configuration -------------------------------\r
+//\r
+// <e> Clock OUT Configuration\r
+// <o1.0..1> Clockout Source Selection\r
+// <0=> System Clock\r
+// <2=> Divided value of USB PLL output\r
+// <3=> Divided value of PLL Clock\r
+// <o2.0..4> Clockout divider <1-10><#-1>\r
+// <o3.0..1> Clockout Pin Selection\r
+// <0=> P1.15\r
+// <1=> P0.8\r
+// \r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCKOUT_SETUP 0\r
+#define SCU_CLOCKOUT_SOURCE 0x00000000\r
+#define SCU_CLOCKOUT_DIV 0x00000009\r
+#define SCU_CLOCKOUT_PIN 0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ static functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void);\r
+#endif\r
+\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void);\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the PLL and update the \r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+int temp;\r
+ \r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
+ (3UL << 11*2) ); /* set CP11 Full Access */\r
+#endif\r
+ \r
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+ \r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
+\r
+WDT->CTR &= ~WDTENB_nVal; \r
+\r
+#endif\r
+\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON; \r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+ \r
+/* Setup the clockout */\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;\r
+\r
+if (SCU_CLOCKOUT_PIN) {\r
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+ PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */\r
+ }\r
+else {\r
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/* Setup the System clock */ \r
+#if SCU_CLOCK_SETUP\r
+SystemClockSetup();\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/* Setup the USB PL */ \r
+#if SCU_USB_CLOCK_SETUP\r
+USBClockSetup();\r
+#endif\r
+\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+if (SCU_CLK->SYSCLKCR == 0x00010000)\r
+{\r
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+ /* check if PLL is locked */\r
+ /* read back divider settings */\r
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+ /* the selected clock is the Backup clock fofi */\r
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* the selected clock is the PLL external oscillator */ \r
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ } \r
+ \r
+ \r
+ }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief -\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void)\r
+{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV; \r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+ \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+/* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+\r
+} \r
+\r
+/* Enable OSC_HP if not already on*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use external crystal for PLL clock input */\r
+ /********************************************************************************************************************/\r
+\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
+\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ do \r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+\r
+ }\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use factory trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use automatic trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* check for HIB Domain enabled */\r
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+ /* check for HIB Domain is not in reset state */\r
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fOSI as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ }\r
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fULP as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ /*check OSCUL if running correct*/\r
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+ {\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+ /* select OSCUL clock for RTC*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*enable OSCULP WDG Alarm Enable*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*wait now for clock is stable */\r
+ do\r
+ {\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ }\r
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
+\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ } \r
+ // now OSCULP is running and can be used \r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ }\r
+ }\r
+\r
+ /********************************************************************************************************************/\r
+ /* Setup and look the main PLL */\r
+ /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+ /* Systen is still running from internal clock */\r
+ /* select FOFI as system clock */\r
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/24000000)-1; \r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ /* disconnect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ /* connect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ /* setup time out loop */\r
+ /* Timeout for wait loo ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ \r
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+\r
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+ {\r
+ /* Go back to the Main PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ }\r
+ else return(0);\r
+ \r
+ \r
+ /*********************************************************\r
+ here we need to setup the system clock divider\r
+ *********************************************************/\r
+ \r
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; \r
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+ \r
+\r
+ /* Switch system clock to PLL */\r
+ SCU_CLK->SYSCLKCR |= 0x00010000; \r
+ \r
+ /* we may have to reset OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ \r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /*********************************************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 60MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 60000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/60000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 90MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 90000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/90000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ \r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ }\r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief -\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
+{\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+ \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
+\r
+/* check and if not already running enable OSC_HP */\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ /* check if Main PLL is switched on for OSC WD*/\r
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ }\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
+ \r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ do \r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+ \r
+ }\r
+\r
+\r
+/* Setup USB PLL */\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
+ /* disconnect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+ /* Setup USBDIV settings USB clock */\r
+ SCU_CLK->USBCLKCR = SCU_USBDIV;\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
+ /* connect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
+ \r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
--- /dev/null
+/*\r
+** @(#)cstart.c 1.9 $E%\r
+**\r
+** Copyright 1997-2013 Altium BV *\r
+**\r
+** DESCRIPTION:\r
+**\r
+** The system startup code initializes the processor's registers\r
+** and the application C variables.\r
+**\r
+*/\r
+\r
+#pragma nomisrac\r
+#pragma profiling off /* prevent profiling information on cstart */\r
+#pragma optimize abcefgIJKlopRsUy /* preset optimization level */\r
+#pragma tradeoff 4 /* preset tradeoff level */\r
+#pragma runtime BCMSZ /* disable runtime error checking for cstart */\r
+#pragma warning 750 /* do not warn about unsaved registers */\r
+#pragma section .text=cstart /* use: .text.cstart as the section name */\r
+\r
+#include <stdlib.h>\r
+#include <dbg.h>\r
+\r
+#define VTOR (*(volatile unsigned int *)0xE000ED08)\r
+#define PREF_FCON (*(volatile unsigned int *)0x58002014)\r
+#define SCU_GCU_PEEN (*(volatile unsigned int *)0x5000413C)\r
+#define SCU_GCU_PEFLAG (*(volatile unsigned int *)0x50004150)\r
+\r
+/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock \r
+ tree setup. \r
+ \r
+ This decision routine defined here will always return TRUE.\r
+ \r
+ When overridden by a definition defined in DAVE code engine, this routine\r
+ returns FALSE indicating that the code engine has performed the clock setup\r
+*/ \r
+#pragma weak AllowPLLInitByStartup\r
+uint32_t AllowPLLInitByStartup( void )\r
+{\r
+ return 1;\r
+}\r
+\r
+\r
+\r
+extern unsigned char _lc_ub_stack[];\r
+extern unsigned char _lc_vtor_value[];\r
+\r
+#pragma weak exit\r
+#pragma extern _Exit\r
+#pragma extern main\r
+extern int main( int argc, char *argv[] );\r
+extern void SystemInit( void );\r
+extern void __init( void );\r
+#if __PROF_ENABLE__\r
+extern void __prof_init( void );\r
+#endif\r
+\r
+#ifdef __POSIX__\r
+extern void * _posix_boot_stack_top;\r
+extern int posix_main( void );\r
+#endif\r
+\r
+#ifdef __USE_ARGC_ARGV\r
+#ifndef __ARGCV_BUFSIZE\r
+#define __ARGCV_BUFSIZE 256\r
+#endif\r
+static char argcv[__ARGCV_BUFSIZE];\r
+#endif\r
+\r
+void __interrupt() __frame() Reset_Handler( void )\r
+{\r
+ /* Set flash wait states to 3 */\r
+ PREF_FCON = (PREF_FCON & 0xFFFFFFF0) | 0x00000003;\r
+ SCU_GCU_PEFLAG =0xFFFFFFFF; /* Clear existing parity errors if any */\r
+ SCU_GCU_PEEN = 0; /* Disable parity */\r
+\r
+ /*\r
+ * Anticipate possible ROM/RAM remapping\r
+ * by loading the 'real' program address.\r
+ */\r
+ __remap_pc();\r
+ /*\r
+ * Initialize stack pointer.\r
+ */\r
+ __setsp( _lc_ub_stack );\r
+ /*\r
+ * Call a user function which initializes hardware,\r
+ * such as ROM/RAM re-mapping or MMU configuration.\r
+ */\r
+ SystemInit();\r
+ /*\r
+ * Copy initialized sections from ROM to RAM\r
+ * and clear uninitialized data sections in RAM.\r
+ */\r
+ __init();\r
+ __asm( "_cptable_handled:" ); /* symbol may be used by debugger */\r
+\r
+ /*\r
+ * Load VTOR register with the actual vector table\r
+ * start address\r
+ */\r
+ VTOR = (unsigned int)_lc_vtor_value;\r
+ \r
+#ifdef __POSIX__\r
+ __setsp( _posix_boot_stack_top );\r
+#endif\r
+#if __PROF_ENABLE__\r
+ __prof_init();\r
+#endif\r
+#ifdef __POSIX__\r
+ exit( posix_main() );\r
+#elif defined __USE_ARGC_ARGV\r
+ exit( main( _argcv( argcv, __ARGCV_BUFSIZE ), (char **)argcv ) );\r
+#else\r
+ exit( main( 0, NULL ) );\r
+#endif\r
+ return;\r
+}\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_XMC4400.c\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the Infineon XMC4500 Device Series\r
+ * @version V3.0.1 Alpha\r
+ * @date 17. September 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <system_XMC4400.h>\r
+#include <XMC4400.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL 1\r
+#define SCU_CLOCK_BACK_UP_FACTORY 2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3\r
+\r
+\r
+#define HIB_CLOCK_FOSI 1 \r
+#define HIB_CLOCK_OSCULP 2\r
+\r
+\r
+\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+\r
+\r
+/*--------------------- Watchdog Configuration -------------------------------\r
+//\r
+// <e> Watchdog Configuration\r
+// <o1.0> Disable Watchdog\r
+//\r
+// </e>\r
+*/\r
+#define WDT_SETUP 1\r
+#define WDTENB_nVal 0x00000001\r
+\r
+/*--------------------- CLOCK Configuration -------------------------------\r
+//\r
+// <e> Main Clock Configuration\r
+// <o1.0..1> CPU clock divider\r
+// <0=> fCPU = fSYS \r
+// <1=> fCPU = fSYS / 2\r
+// <o2.0..1> Peripheral Bus clock divider\r
+// <0=> fPB = fCPU\r
+// <1=> fPB = fCPU / 2\r
+// <o3.0..1> CCU Bus clock divider\r
+// <0=> fCCU = fCPU\r
+// <1=> fCCU = fCPU / 2\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCK_SETUP 1\r
+#define SCU_CPUCLKCR_DIV 0x00000000\r
+#define SCU_PBCLKCR_DIV 0x00000000\r
+#define SCU_CCUCLKCR_DIV 0x00000000\r
+/* not avalible in config wizzard*/\r
+/* \r
+* mandatory clock parameters ************************************************** \r
+* \r
+* source for clock generation \r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) \r
+* \r
+**************************************************************************************/ \r
+// Selection of imput lock for PLL \r
+/*************************************************************************************/\r
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP\r
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS 120000000\r
+#define CLOCK_CRYSTAL_FREQUENCY 12000000 \r
+#define CLOCK_BACK_UP 24000000 \r
+ \r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */ \r
+/*************************************************************************************/\r
+#define SCU_OSC_HP_MODE 0xF0\r
+#define SCU_OSCHPWDGDIV 2 \r
+ \r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */ \r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz \r
+/*************************************************************************************/\r
+#define SCU_PLL_K1DIV 1\r
+#define SCU_PLL_K2DIV 3\r
+#define SCU_PLL_PDIV 1\r
+#define SCU_PLL_NDIV 79\r
+ \r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define SCU_PLL_K1DIV 1 \r
+//#define SCU_PLL_K2DIV 3 \r
+//#define SCU_PLL_PDIV 3 \r
+//#define SCU_PLL_NDIV 79 \r
+/*************************************************************************************/\r
+ \r
+\r
+/*--------------------- USB CLOCK Configuration ---------------------------\r
+//\r
+// <e> USB Clock Configuration\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_USB_CLOCK_SETUP 0\r
+/* not avalible in config wizzard*/\r
+#define SCU_USBPLL_PDIV 0 \r
+#define SCU_USBPLL_NDIV 31 \r
+#define SCU_USBDIV 3 \r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+// <o1.0..3> Flash Wait State\r
+// <0=> 3 WS\r
+// <1=> 4 WS\r
+// <2=> 5 WS \r
+// <3=> 6 WS\r
+// </e>\r
+// \r
+*/\r
+\r
+#define PMU_FLASH 1\r
+#define PMU_FLASH_WS 0x00000000\r
+\r
+\r
+/*--------------------- CLOCKOUT Configuration -------------------------------\r
+//\r
+// <e> Clock OUT Configuration\r
+// <o1.0..1> Clockout Source Selection\r
+// <0=> System Clock\r
+// <2=> Divided value of USB PLL output\r
+// <3=> Divided value of PLL Clock\r
+// <o2.0..4> Clockout divider <1-10><#-1>\r
+// <o3.0..1> Clockout Pin Selection\r
+// <0=> P1.15\r
+// <1=> P0.8\r
+// \r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCKOUT_SETUP 0\r
+#define SCU_CLOCKOUT_SOURCE 0x00000000\r
+#define SCU_CLOCKOUT_DIV 0x00000009\r
+#define SCU_CLOCKOUT_PIN 0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ static functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void);\r
+#endif\r
+\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void);\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the PLL and update the \r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+int temp;\r
+ \r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
+ (3UL << 11*2) ); /* set CP11 Full Access */\r
+#endif\r
+ \r
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+ \r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
+\r
+WDT->CTR &= ~WDTENB_nVal; \r
+\r
+#endif\r
+\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON; \r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+ \r
+/* Setup the clockout */\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;\r
+\r
+if (SCU_CLOCKOUT_PIN) {\r
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+ PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */\r
+ }\r
+else {\r
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/* Setup the System clock */ \r
+#if SCU_CLOCK_SETUP\r
+SystemClockSetup();\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/* Setup the USB PL */ \r
+#if SCU_USB_CLOCK_SETUP\r
+USBClockSetup();\r
+#endif\r
+\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+if (SCU_CLK->SYSCLKCR == 0x00010000)\r
+{\r
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+ /* check if PLL is locked */\r
+ /* read back divider settings */\r
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+ /* the selected clock is the Backup clock fofi */\r
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* the selected clock is the PLL external oscillator */ \r
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ } \r
+ \r
+ \r
+ }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief -\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void)\r
+{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV; \r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+ \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+/* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+\r
+} \r
+\r
+/* Enable OSC_HP if not already on*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use external crystal for PLL clock input */\r
+ /********************************************************************************************************************/\r
+\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
+\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ do \r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+\r
+ }\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use factory trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use automatic trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* check for HIB Domain enabled */\r
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+ /* check for HIB Domain is not in reset state */\r
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fOSI as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ }\r
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fULP as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ /*check OSCUL if running correct*/\r
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+ {\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+ /* select OSCUL clock for RTC*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*enable OSCULP WDG Alarm Enable*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*wait now for clock is stable */\r
+ do\r
+ {\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ }\r
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
+\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ } \r
+ // now OSCULP is running and can be used \r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ }\r
+ }\r
+\r
+ /********************************************************************************************************************/\r
+ /* Setup and look the main PLL */\r
+ /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+ /* Systen is still running from internal clock */\r
+ /* select FOFI as system clock */\r
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/24000000)-1; \r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ /* disconnect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ /* connect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ /* setup time out loop */\r
+ /* Timeout for wait loo ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ \r
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+\r
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+ {\r
+ /* Go back to the Main PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ }\r
+ else return(0);\r
+ \r
+ \r
+ /*********************************************************\r
+ here we need to setup the system clock divider\r
+ *********************************************************/\r
+ \r
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; \r
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+ \r
+\r
+ /* Switch system clock to PLL */\r
+ SCU_CLK->SYSCLKCR |= 0x00010000; \r
+ \r
+ /* we may have to reset OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ \r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /*********************************************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 60MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 60000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/60000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 90MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 90000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/90000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ \r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ }\r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief -\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
+{\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+ \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
+\r
+/* check and if not already running enable OSC_HP */\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ /* check if Main PLL is switched on for OSC WD*/\r
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ }\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
+ \r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ do \r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+ \r
+ }\r
+\r
+\r
+/* Setup USB PLL */\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
+ /* disconnect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+ /* Setup USBDIV settings USB clock */\r
+ SCU_CLK->USBCLKCR = SCU_USBDIV;\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
+ /* connect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
+ \r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
/*\r
-** @(#)cstart.c 1.8 $E%\r
+** @(#)cstart.c 1.9 $E%\r
**\r
-** Copyright 1997-2012 Altium BV *\r
+** Copyright 1997-2013 Altium BV *\r
**\r
** DESCRIPTION:\r
**\r
#pragma runtime BCMSZ /* disable runtime error checking for cstart */\r
#pragma warning 750 /* do not warn about unsaved registers */\r
#pragma section .text=cstart /* use: .text.cstart as the section name */\r
-#pragma alias Reset_Handler = _START /* requirement for CMSIS */\r
-#pragma extern Reset_Handler /* required for mil-linking with CMSIS */\r
\r
#include <stdlib.h>\r
#include <dbg.h>\r
\r
#define VTOR (*(volatile unsigned int *)0xE000ED08)\r
-#define PREF_PCON (*(volatile unsigned int *)0x58004000)\r
-#define SCU_GCU_PEEN (*(volatile unsigned int *)0x5000413C)\r
-#define SCU_GCU_PEFLAG (*(volatile unsigned int *)0x50004150)\r
+/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock \r
+ tree setup. \r
+ \r
+ This decision routine defined here will always return TRUE.\r
+ \r
+ When overridden by a definition defined in DAVE code engine, this routine\r
+ returns FALSE indicating that the code engine has performed the clock setup\r
+*/ \r
+#pragma weak AllowPLLInitByStartup\r
+uint32_t AllowPLLInitByStartup( void )\r
+{\r
+ return 1;\r
+}\r
+\r
\r
\r
extern unsigned char _lc_ub_stack[];\r
static char argcv[__ARGCV_BUFSIZE];\r
#endif\r
\r
-void __interrupt() __frame() _START( void )\r
+void __interrupt() __frame() Reset_Handler( void )\r
{\r
- PREF_PCON |= 0x00010000; /* Disable Branch prediction */\r
- SCU_GCU_PEFLAG =0xFFFFFFFF; /* Clear existing parity errors if any */\r
- SCU_GCU_PEEN = 0; /* Disable parity */\r
\r
/*\r
* Anticipate possible ROM/RAM remapping\r
-/******************************************************************************\r
+/**************************************************************************//**\r
* @file system_XMC4500.c\r
- * @brief Device specific initialization for the XMC4500-Series according to CMSIS\r
- * @version V2.2\r
- * @date 20. January 2012\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the Infineon XMC4500 Device Series\r
+ * @version V3.0.1 Alpha\r
+ * @date 17. September 2012\r
*\r
* @note\r
- * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
-\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
*\r
* @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers. \r
- * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
-\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
*\r
* @par\r
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
*\r
- *\r
******************************************************************************/\r
\r
#include "system_XMC4500.h"\r
#include <XMC4500.h>\r
\r
-/*----------------------------------------------------------------------------\r
- Define clocks is located in System_XMC4500.h\r
- *----------------------------------------------------------------------------*/\r
-\r
/*----------------------------------------------------------------------------\r
Clock Variable definitions\r
*----------------------------------------------------------------------------*/\r
/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock = CLOCK_OSC_HP;\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL 1\r
+#define SCU_CLOCK_BACK_UP_FACTORY 2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3\r
+\r
+\r
+#define HIB_CLOCK_FOSI 1 \r
+#define HIB_CLOCK_OSCULP 2\r
+\r
+\r
\r
-/*----------------------------------------------------------------------------\r
- Keil pragma to prevent warnings\r
- *----------------------------------------------------------------------------*/\r
-#if defined(__ARMCC_VERSION)\r
-#pragma diag_suppress 177\r
-#endif\r
\r
/*\r
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
#define SCU_CPUCLKCR_DIV 0x00000000\r
#define SCU_PBCLKCR_DIV 0x00000000\r
#define SCU_CCUCLKCR_DIV 0x00000000\r
-\r
-\r
+/* not avalible in config wizzard*/\r
+/* \r
+* mandatory clock parameters ************************************************** \r
+* \r
+* source for clock generation \r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) \r
+* \r
+**************************************************************************************/ \r
+// Selection of imput lock for PLL \r
+/*************************************************************************************/\r
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP\r
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS 120000000\r
+#define CLOCK_CRYSTAL_FREQUENCY 12000000 \r
+#define CLOCK_BACK_UP 24000000 \r
+ \r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */ \r
+/*************************************************************************************/\r
+#define SCU_OSC_HP_MODE 0xF0\r
+#define SCU_OSCHPWDGDIV 2 \r
+ \r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */ \r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz \r
+/*************************************************************************************/\r
+#define SCU_PLL_K1DIV 1\r
+#define SCU_PLL_K2DIV 3\r
+#define SCU_PLL_PDIV 1\r
+#define SCU_PLL_NDIV 79\r
+ \r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define SCU_PLL_K1DIV 1 \r
+//#define SCU_PLL_K2DIV 3 \r
+//#define SCU_PLL_PDIV 3 \r
+//#define SCU_PLL_NDIV 79 \r
+/*************************************************************************************/\r
\r
/*--------------------- USB CLOCK Configuration ---------------------------\r
//\r
*/\r
\r
#define SCU_USB_CLOCK_SETUP 0\r
+/* not avalible in config wizzard*/\r
+#define SCU_USBPLL_PDIV 0 \r
+#define SCU_USBPLL_NDIV 31 \r
+#define SCU_USBDIV 3 \r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+// <o1.0..3> Flash Wait State\r
+// <0=> 3 WS\r
+// <1=> 4 WS\r
+// <2=> 5 WS \r
+// <3=> 6 WS\r
+// </e>\r
+// \r
+*/\r
+\r
+#define PMU_FLASH 1\r
+#define PMU_FLASH_WS 0x00000000\r
\r
\r
/*--------------------- CLOCKOUT Configuration -------------------------------\r
// <e> Clock OUT Configuration\r
// <o1.0..1> Clockout Source Selection\r
// <0=> System Clock\r
-// <2=> USB Clock\r
+// <2=> Divided value of USB PLL output\r
// <3=> Divided value of PLL Clock\r
-// <o2.0..1> Clockout Pin Selection\r
+// <o2.0..4> Clockout divider <1-10><#-1>\r
+// <o3.0..1> Clockout Pin Selection\r
// <0=> P1.15\r
// <1=> P0.8\r
// \r
// \r
*/\r
\r
-#define SCU_CLOCKOUT_SETUP 0 // recommended to keep disabled\r
-#define SCU_CLOCKOUT_SOURCE 0x00000000\r
-#define SCU_CLOCKOUT_PIN 0x00000000\r
+#define SCU_CLOCKOUT_SETUP 0\r
+#define SCU_CLOCKOUT_SOURCE 0x00000003\r
+#define SCU_CLOCKOUT_DIV 0x00000009\r
+#define SCU_CLOCKOUT_PIN 0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
\r
/*----------------------------------------------------------------------------\r
static functions declarations\r
#endif\r
\r
#if (SCU_USB_CLOCK_SETUP == 1)\r
-static void USBClockSetup(void);\r
+static int USBClockSetup(void);\r
#endif\r
\r
+\r
/**\r
* @brief Setup the microcontroller system.\r
* Initialize the PLL and update the \r
*/\r
void SystemInit(void)\r
{\r
-/* Setup the WDT */\r
-#if (WDT_SETUP == 1)\r
-WDT->CTR &= ~WDTENB_nVal; \r
-#endif\r
-\r
+int temp;\r
+ \r
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
(3UL << 11*2) ); /* set CP11 Full Access */\r
#endif\r
\r
-/* Disable branch prediction - PCON.PBS = 1 */\r
-PREF->PCON |= (PREF_PCON_PBS_Msk);\r
-\r
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+ \r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
\r
+WDT->CTR &= ~WDTENB_nVal; \r
+\r
+#endif\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON; \r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+ \r
/* Setup the clockout */\r
-/* README README README README README README README README README README */\r
-/*\r
- * Please use the CLOCKOUT feature with diligence. Use this only if you know\r
- * what you are doing.\r
- *\r
- * You must be aware that the settings below can potentially be in conflict\r
- * with DAVE code generation engine preferences.\r
- *\r
- * Even worse, the setting below configures the ports as output ports while in\r
- * reality, the board on which this chip is mounted may have a source driving\r
- * the ports.\r
- *\r
- * So use this feature only when you are absolutely sure that the port must \r
- * indeed be configured as an output AND you are NOT linking this startup code\r
- * with code that was generated by DAVE code engine.\r
- */\r
-#if (SCU_CLOCKOUT_SETUP == 1)\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;\r
\r
if (SCU_CLOCKOUT_PIN) {\r
- PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
- PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
- }\r
-else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+ //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */\r
+ }\r
+else {\r
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */\r
+ }\r
+\r
#endif\r
\r
+\r
/* Setup the System clock */ \r
-#if (SCU_CLOCK_SETUP == 1)\r
+#if SCU_CLOCK_SETUP\r
SystemClockSetup();\r
#endif\r
\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
/* Setup the USB PL */ \r
-#if (SCU_USB_CLOCK_SETUP == 1)\r
+#if SCU_USB_CLOCK_SETUP\r
USBClockSetup();\r
#endif\r
\r
+\r
+\r
}\r
\r
\r
*/\r
void SystemCoreClockUpdate(void)\r
{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
\r
/*----------------------------------------------------------------------------\r
Clock Variable definitions\r
*----------------------------------------------------------------------------*/\r
-SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/\r
+if (SCU_CLK->SYSCLKCR == 0x00010000)\r
+{\r
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+ /* check if PLL is locked */\r
+ /* read back divider settings */\r
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+ /* the selected clock is the Backup clock fofi */\r
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* the selected clock is the PLL external oscillator */ \r
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ } \r
+ \r
+ \r
+ }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
\r
}\r
\r
#if (SCU_CLOCK_SETUP == 1)\r
static int SystemClockSetup(void)\r
{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV; \r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+ \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
/* enable PLL first */\r
- SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | \r
- SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
\r
-/* Enable OSC_HP */\r
+}\r
+\r
+/* Enable OSC_HP if not already on*/\r
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
{\r
- /* Enable the OSC_HP*/\r
- SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); \r
- /* Setup OSC WDG devider */\r
- SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); \r
- /* Select external OSC as PLL input */\r
- SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
- /* Restart OSC Watchdog */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
-\r
- do \r
- {\r
- ; /* here a timeout need to be added */\r
- }while(!( (SCU_PLL->PLLSTAT) & \r
- (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |\r
- SCU_PLL_PLLSTAT_PLLSP_Msk)\r
- )\r
- ); \r
-\r
- }\r
-\r
-/* Setup Main PLL */\r
- /* Select FOFI as system clock */\r
- if(SCU_CLK->SYSCLKCR != 0X000000)\r
- SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/\r
+ /********************************************************************************************************************/\r
+ /* Use external crystal for PLL clock input */\r
+ /********************************************************************************************************************/\r
\r
- /* Go to bypass the Main PLL */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
-\r
- /* disconnect OSC_HP to PLL */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
- (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));\r
-\r
- /* we may have to set OSCDISCDIS */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
-\r
- /* connect OSC_HP to PLL */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
-\r
- /* restart PLL Lock detection */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
\r
- /* wait for PLL Lock */\r
- while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ do \r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
\r
- /* Go back to the Main PLL */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
\r
- /*********************************************************\r
- here we need to setup the system clock divider\r
- *********************************************************/\r
+ }\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use factory trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use automatic trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* check for HIB Domain enabled */\r
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+ /* check for HIB Domain is not in reset state */\r
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fOSI as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ }\r
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fULP as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ /*check OSCUL if running correct*/\r
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+ {\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+ /* select OSCUL clock for RTC*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*enable OSCULP WDG Alarm Enable*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*wait now for clock is stable */\r
+ do\r
+ {\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ }\r
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
+\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ } \r
+ // now OSCULP is running and can be used \r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ }\r
+ }\r
\r
- SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
- SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; \r
- SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+ /********************************************************************************************************************/\r
+ /* Setup and look the main PLL */\r
+ /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+ /* Systen is still running from internal clock */\r
+ /* select FOFI as system clock */\r
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/24000000)-1; \r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ /* disconnect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ /* connect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ /* setup time out loop */\r
+ /* Timeout for wait loo ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ \r
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+\r
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+ {\r
+ /* Go back to the Main PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ }\r
+ else return(0);\r
+ \r
+ \r
+ /*********************************************************\r
+ here we need to setup the system clock divider\r
+ *********************************************************/\r
+ \r
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; \r
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+ \r
\r
- /* Switch system clock to PLL */\r
- SCU_CLK->SYSCLKCR |= 0x00010000; \r
- \r
+ /* Switch system clock to PLL */\r
+ SCU_CLK->SYSCLKCR |= 0x00010000; \r
+ \r
+ /* we may have to reset OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ \r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /*********************************************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 60MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 60000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/60000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
/*********************************************************\r
- here the ramp up of the system clock starts\r
- *********************************************************/\r
- /* Delay for next K2 step ~50µs */\r
- /********************************/\r
- /* Set reload register */\r
- SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
- /* Load the SysTick Counter Value */\r
- SysTick->VAL = 0; \r
-\r
- /* Enable SysTick IRQ and SysTick Timer */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_ENABLE_Msk; \r
- \r
- /* wait for ~50µs */\r
- while (SysTick->VAL >= 100); \r
-\r
- /* Stop SysTick Timer */\r
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \r
- /********************************/\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
- (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));\r
-\r
- /* Delay for next K2 step ~50µs */\r
- /********************************/\r
- SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
- /* Load the SysTick Counter Value */\r
- SysTick->VAL = 0;\r
-\r
- /* Enable SysTick IRQ and SysTick Timer */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
- \r
- /* Wait for ~50µs */\r
- while (SysTick->VAL >= 100); \r
-\r
- /* Stop SysTick Timer */\r
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \r
- /********************************/\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
- (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));\r
-\r
- /* Delay for next K2 step ~50µs */\r
- /********************************/\r
- SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
- /* Load the SysTick Counter Value */\r
- SysTick->VAL = 0; \r
-\r
- /* Enable SysTick IRQ and SysTick Timer */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
- \r
- /* Wait for ~50µs */\r
- while (SysTick->VAL >= 100); \r
-\r
- /* Stop SysTick Timer */\r
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \r
- /********************************/\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) | \r
- (PLL_PDIV<<24));\r
-\r
- /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
- SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | \r
- SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; \r
-\r
+ here the ramp up of the system clock starts FSys < 90MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 90000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/90000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ \r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ }\r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
return(1);\r
\r
}\r
* @param None\r
* @retval None\r
*/\r
-#if(SCU_USB_CLOCK_SETUP == 1)\r
-static void USBClockSetup(void)\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
{\r
-/* enable PLL first */\r
- SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | \r
- SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+\r
+ /* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
\r
/* check and if not already running enable OSC_HP */\r
- if(!((SCU_PLL->PLLSTAT) & \r
- (SCU_PLL_PLLSTAT_PLLHV_Msk | \r
- SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))\r
- {\r
- if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
- {\r
- \r
- SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ /* check if Main PLL is switched on for OSC WD*/\r
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ }\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
/* setup OSC WDG devider */\r
- SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); \r
- /* select external OSC as PLL input */\r
- SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
/* restart OSC Watchdog */\r
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
do \r
{\r
- ; /* here a timeout need to be added */\r
- }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | \r
- SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); \r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
\r
- }\r
}\r
\r
\r
/* disconnect OSC_FI to PLL */\r
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
/* Setup devider settings for main PLL */\r
- SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));\r
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+ /* Setup USBDIV settings USB clock */\r
+ SCU_CLK->USBCLKCR = SCU_USBDIV;\r
/* we may have to set OSCDISCDIS */\r
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
/* connect OSC_FI to PLL */\r
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
/* wait for PLL Lock */\r
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
- }\r
+ \r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
+ return(1);\r
+\r
+}\r
#endif\r
+\r
* This file implements the code that is not demo specific, including the\r
* hardware setup and FreeRTOS hook functions.\r
*\r
- * \r
+ *\r
* Additional code:\r
- * \r
+ *\r
* This demo does not contain a non-kernel interrupt service routine that\r
* can be used as an example for application writers to use as a reference.\r
* Therefore, the framework of a dummy (not installed) handler is provided\r
#include "XMC4500.h"\r
#include "System_XMC4500.h"\r
\r
+/* Standard demo includes. */\r
+#include "QueueSet.h"\r
+#include "QueueOverwrite.h"\r
+\r
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
or 0 to run the more comprehensive test and demo application. */\r
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
*/\r
static void prvSetupHardware( void );\r
\r
-/* \r
+/*\r
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
- * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. \r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
*/\r
extern void main_blinky( void );\r
extern void main_full( void );\r
\r
static void prvSetupHardware( void )\r
{\r
-extern void SystemCoreClockUpdate( void );\r
-\r
- /* Ensure SystemCoreClock variable is set. */\r
- SystemCoreClockUpdate();\r
-\r
- /* Configure pin P3.9 for the LED. */\r
- PORT3->IOCR8 = 0x00008000;\r
+ configCONFIGURE_LED();\r
\r
/* Ensure all priority bits are assigned as preemption priority bits. */\r
NVIC_SetPriorityGrouping( 0 );\r
\r
void vApplicationTickHook( void )\r
{\r
- /* This function will be called by each tick interrupt if \r
+ /* This function will be called by each tick interrupt if\r
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
added here, but the tick hook is called from an interrupt context, so\r
code must not attempt to block, and only the interrupt safe FreeRTOS API\r
functions can be used (those that end in FromISR()). */\r
+\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
+ {\r
+ /* Write to a queue that is in use as part of the queue set demo to\r
+ demonstrate using queue sets from an ISR. */\r
+ vQueueSetAccessQueueSetFromISR();\r
+\r
+ /* Test the ISR safe queue overwrite functions. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+ }\r
+ #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */\r
}\r
/*-----------------------------------------------------------*/\r
\r
\r
/* Clear the interrupt if necessary. */\r
Dummy_ClearITPendingBit();\r
- \r
+\r
/* This interrupt does nothing more than demonstrate how to synchronise a\r
task with an interrupt. A semaphore is used for this purpose. Note\r
lHigherPriorityTaskWoken is initialised to zero. */\r
xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
- \r
+\r
/* If there was a task that was blocked on the semaphore, and giving the\r
semaphore caused the task to unblock, and the unblocked task has a priority\r
higher than the current Running state task (the task that this interrupt\r
interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE\r
- internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the \r
+ internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the\r
portEND_SWITCHING_ISR() macro will result in a context switch being pended to\r
- ensure this interrupt returns directly to the unblocked, higher priority, \r
+ ensure this interrupt returns directly to the unblocked, higher priority,\r
task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */\r
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
}\r
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
\r
-/* To toggle the single LED */\r
-#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )\r
-\r
/*-----------------------------------------------------------*/\r
\r
/*\r
*/\r
void main_blinky( void );\r
\r
-/*\r
- * The hardware only has a single LED. Simply toggle it.\r
- */\r
-extern void vMainToggleLED( void );\r
-\r
/*-----------------------------------------------------------*/\r
\r
/* The queue used by both tasks. */\r
is it the expected value? If it is, toggle the LED. */\r
if( ulReceivedValue == 100UL )\r
{\r
- mainTOGGLE_LED();\r
+ configTOGGLE_LED();\r
ulReceivedValue = 0U;\r
}\r
}\r
******************************************************************************\r
*\r
* main_full() creates all the demo application tasks and a software timer, then\r
- * starts the scheduler. The web documentation provides more details of the \r
- * standard demo application tasks, which provide no particular functionality, \r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
* but do provide a good example of how to use the FreeRTOS API.\r
*\r
* In addition to the standard demo tasks, the following tasks and tests are\r
\r
/* Standard demo application includes. */\r
#include "flop.h"\r
-#include "integer.h"\r
-#include "PollQ.h"\r
#include "semtest.h"\r
#include "dynamic.h"\r
-#include "BlockQ.h"\r
#include "blocktim.h"\r
#include "countsem.h"\r
#include "GenQTest.h"\r
#include "recmutex.h"\r
-#include "death.h"\r
+#include "QueueSet.h"\r
+#include "QueueOverwrite.h"\r
\r
/* Hardware includes. */\r
#include "XMC4500.h"\r
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
\r
-/* To toggle the single LED */\r
-#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )\r
-\r
/* A block time of zero simply means "don't block". */\r
#define mainDONT_BLOCK ( 0UL )\r
\r
/* Start all the other standard demo/test tasks. The have not particular\r
functionality, but do demonstrate how to use the FreeRTOS API and test the\r
kernel port. */\r
- vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartQueueSetTasks();\r
+ vStartQueueOverwriteTask( tskIDLE_PRIORITY );\r
vStartDynamicPriorityTasks();\r
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
vCreateBlockTimeTasks();\r
- vStartCountingSemaphoreTasks();\r
vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
vStartRecursiveMutexTasks();\r
- vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
- \r
+\r
/* Create the register check tasks, as described at the top of this\r
file */\r
xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
}\r
\r
- /* The set of tasks created by the following function call have to be \r
- created last as they keep account of the number of tasks they expect to see \r
- running. */\r
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
-\r
/* Start the scheduler. */\r
vTaskStartScheduler();\r
\r
ulErrorFound = pdTRUE;\r
}\r
\r
- if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = pdTRUE;\r
- }\r
-\r
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
{\r
ulErrorFound = pdTRUE;\r
}\r
\r
- if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = pdTRUE;\r
- }\r
-\r
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
{\r
ulErrorFound = pdTRUE;\r
ulErrorFound = pdTRUE;\r
}\r
\r
- if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ if( xAreQueueSetTasksStillRunning() != pdTRUE )\r
{\r
ulErrorFound = pdTRUE;\r
}\r
\r
- if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ if( xIsQueueOverwriteTaskStillRunning() != pdTRUE )\r
{\r
ulErrorFound = pdTRUE;\r
}\r
\r
- if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = pdTRUE;\r
- }\r
- \r
/* Check that the register test 1 task is still running. */\r
if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
{\r
/* Toggle the check LED to give an indication of the system status. If\r
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
everything is ok. A faster toggle indicates an error. */\r
- mainTOGGLE_LED(); \r
- \r
+ configTOGGLE_LED();\r
+\r
/* Have any errors been latch in ulErrorFound? If so, shorten the\r
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
This will result in an increase in the rate at which mainCHECK_LED\r
if( lChangedTimerPeriodAlready == pdFALSE )\r
{\r
lChangedTimerPeriodAlready = pdTRUE;\r
- \r
+\r
/* This call to xTimerChangePeriod() uses a zero block time.\r
Functions called from inside of a timer callback function must\r
*never* attempt to block. */\r
" ldr r1, [r0] \n"\r
" adds r1, r1, #1 \n"\r
" str r1, [r0] \n"\r
+ " \n"\r
+ " movs r0, #0x01 \n" /* Yield to increase test coverage. */\r
+ " ldr r1, =0xe000ed04 \n" /*NVIC_INT_CTRL */\r
+ " lsl r0, r0, #28 \n" /* Shift to PendSV bit */\r
+ " str r0, [r1] \n"\r
+ " dsb \n"\r
" pop { r0-r1 } \n"\r
" \n"\r
" b reg2_loop \n" /* Start again. */\r
projects / freertos / commitdiff