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   1 /**************************************************************************//**\r
   2  * @file     system_XMC4400.c\r
   3  * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
   4  *           for the Infineon XMC4500 Device Series\r
   5  * @version  V3.0.1 Alpha\r
   6  * @date     17. September 2012\r
   7  *\r
   8  * @note\r
   9  * Copyright (C) 2011 ARM Limited. All rights reserved.\r
  10  *\r
  11  * @par\r
  12  * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
  13  * processor based microcontrollers.  This file can be freely distributed \r
  14  * within development tools that are supporting such ARM based processors. \r
  15  *\r
  16  * @par\r
  17  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
  18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
  19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
  20  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
  21  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
  22  *\r
  23  ******************************************************************************/\r
  24 \r
  25 #include <system_XMC4400.h>\r
  26 #include <XMC4400.h>\r
  27 \r
  28 /*----------------------------------------------------------------------------\r
  29   Clock Variable definitions\r
  30  *----------------------------------------------------------------------------*/\r
  31 /*!< System Clock Frequency (Core Clock)*/\r
  32 uint32_t SystemCoreClock;\r
  33 \r
  34 /* clock definitions, do not modify! */\r
  35 #define SCU_CLOCK_CRYSTAL               1\r
  36 #define SCU_CLOCK_BACK_UP_FACTORY                       2\r
  37 #define SCU_CLOCK_BACK_UP_AUTOMATIC             3\r
  38 \r
  39 \r
  40 #define HIB_CLOCK_FOSI                                  1                                \r
  41 #define HIB_CLOCK_OSCULP                                2\r
  42 \r
  43 \r
  44 \r
  45 \r
  46 /*\r
  47 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
  48 */\r
  49 \r
  50 \r
  51 \r
  52 /*--------------------- Watchdog Configuration -------------------------------\r
  53 //\r
  54 // <e> Watchdog Configuration\r
  55 //     <o1.0> Disable Watchdog\r
  56 //\r
  57 // </e>\r
  58 */\r
  59 #define WDT_SETUP               1\r
  60 #define WDTENB_nVal             0x00000001\r
  61 \r
  62 /*--------------------- CLOCK Configuration -------------------------------\r
  63 //\r
  64 // <e> Main Clock Configuration\r
  65 //     <o1.0..1> CPU clock divider\r
  66 //                     <0=> fCPU = fSYS \r
  67 //                     <1=> fCPU = fSYS / 2\r
  68 //     <o2.0..1>  Peripheral Bus clock divider\r
  69 //                     <0=> fPB = fCPU\r
  70 //                     <1=> fPB = fCPU / 2\r
  71 //     <o3.0..1>  CCU Bus clock divider\r
  72 //                     <0=> fCCU = fCPU\r
  73 //                     <1=> fCCU = fCPU / 2\r
  74 //\r
  75 // </e>\r
  76 // \r
  77 */\r
  78 \r
  79 #define SCU_CLOCK_SETUP               1\r
  80 #define SCU_CPUCLKCR_DIV                0x00000000\r
  81 #define SCU_PBCLKCR_DIV             0x00000000\r
  82 #define SCU_CCUCLKCR_DIV                0x00000000\r
  83 /* not avalible in config wizzard*/\r
  84 /*                              \r
  85 * mandatory clock parameters **************************************************                         \r
  86 *                               \r
  87 * source for clock generation                           \r
  88 * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)                         \r
  89 *                               \r
  90 **************************************************************************************/                         \r
  91 // Selection of imput lock for PLL      \r
  92 /*************************************************************************************/\r
  93 #define SCU_PLL_CLOCK_INPUT     SCU_CLOCK_CRYSTAL\r
  94 //#define       SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_FACTORY\r
  95 //#define       SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_AUTOMATIC\r
  96 \r
  97 /*************************************************************************************/\r
  98 // Standby clock selection for Backup clock source trimming\r
  99 /*************************************************************************************/\r
 100 #define SCU_STANDBY_CLOCK  HIB_CLOCK_OSCULP\r
 101 //#define       SCU_STANDBY_CLOCK  HIB_CLOCK_FOSI\r
 102 \r
 103 /*************************************************************************************/\r
 104 // Global clock parameters\r
 105 /*************************************************************************************/\r
 106 #define CLOCK_FSYS                                                      120000000\r
 107 #define CLOCK_CRYSTAL_FREQUENCY 12000000                \r
 108 #define CLOCK_BACK_UP                                           24000000                \r
 109                                 \r
 110 /*************************************************************************************/\r
 111 /* OSC_HP setup parameters */                           \r
 112 /*************************************************************************************/\r
 113 #define SCU_OSC_HP_MODE 0xF0\r
 114 #define SCU_OSCHPWDGDIV 2               \r
 115                                 \r
 116 /*************************************************************************************/\r
 117 /* MAIN PLL setup parameters */                         \r
 118 /*************************************************************************************/\r
 119 //Divider settings for external crystal @ 12 MHz \r
 120 /*************************************************************************************/\r
 121 #define         SCU_PLL_K1DIV   1\r
 122 #define         SCU_PLL_K2DIV   3\r
 123 #define         SCU_PLL_PDIV    1\r
 124 #define         SCU_PLL_NDIV    79\r
 125                                 \r
 126 /*************************************************************************************/\r
 127 //Divider settings for use of backup clock source trimmed\r
 128 /*************************************************************************************/\r
 129 //#define       SCU_PLL_K1DIV   1               \r
 130 //#define       SCU_PLL_K2DIV   3               \r
 131 //#define       SCU_PLL_PDIV    3               \r
 132 //#define       SCU_PLL_NDIV    79              \r
 133 /*************************************************************************************/\r
 134         \r
 135 \r
 136 /*--------------------- USB CLOCK Configuration ---------------------------\r
 137 //\r
 138 // <e> USB Clock Configuration\r
 139 //\r
 140 // </e>\r
 141 // \r
 142 */\r
 143 \r
 144 #define SCU_USB_CLOCK_SETUP              0\r
 145 /* not avalible in config wizzard*/\r
 146 #define         SCU_USBPLL_PDIV 0               \r
 147 #define         SCU_USBPLL_NDIV 31              \r
 148 #define         SCU_USBDIV      3               \r
 149 \r
 150 /*--------------------- Flash Wait State Configuration -------------------------------\r
 151 //\r
 152 // <e> Flash Wait State Configuration\r
 153 //     <o1.0..3>   Flash Wait State\r
 154 //                     <0=> 3 WS\r
 155 //                     <1=> 4 WS\r
 156 //                     <2=> 5 WS     \r
 157 //                                                                               <3=> 6 WS\r
 158 // </e>\r
 159 // \r
 160 */\r
 161 \r
 162 #define PMU_FLASH             1\r
 163 #define PMU_FLASH_WS                                    0x00000000\r
 164 \r
 165 \r
 166 /*--------------------- CLOCKOUT Configuration -------------------------------\r
 167 //\r
 168 // <e> Clock OUT Configuration\r
 169 //     <o1.0..1>   Clockout Source Selection\r
 170 //                     <0=> System Clock\r
 171 //                     <2=> Divided value of USB PLL output\r
 172 //                     <3=> Divided value of PLL Clock\r
 173 //     <o2.0..4>   Clockout divider <1-10><#-1>\r
 174 //     <o3.0..1>   Clockout Pin Selection\r
 175 //                     <0=> P1.15\r
 176 //                     <1=> P0.8\r
 177 //                     \r
 178 //\r
 179 // </e>\r
 180 // \r
 181 */\r
 182 \r
 183 #define SCU_CLOCKOUT_SETUP               0\r
 184 #define SCU_CLOCKOUT_SOURCE             0x00000000\r
 185 #define SCU_CLOCKOUT_DIV                0x00000009\r
 186 #define SCU_CLOCKOUT_PIN                0x00000001\r
 187 \r
 188 /*----------------------------------------------------------------------------\r
 189   Clock Variable definitions\r
 190  *----------------------------------------------------------------------------*/\r
 191 /*!< System Clock Frequency (Core Clock)*/\r
 192 #if SCU_CLOCK_SETUP\r
 193 uint32_t SystemCoreClock = CLOCK_FSYS;\r
 194 #else\r
 195 uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
 196 #endif\r
 197 \r
 198 /*----------------------------------------------------------------------------\r
 199   static functions declarations\r
 200  *----------------------------------------------------------------------------*/\r
 201 #if (SCU_CLOCK_SETUP == 1)\r
 202 static int SystemClockSetup(void);\r
 203 #endif\r
 204 \r
 205 #if (SCU_USB_CLOCK_SETUP == 1)\r
 206 static int USBClockSetup(void);\r
 207 #endif\r
 208 \r
 209 \r
 210 /**\r
 211   * @brief  Setup the microcontroller system.\r
 212   *         Initialize the PLL and update the \r
 213   *         SystemCoreClock variable.\r
 214   * @param  None\r
 215   * @retval None\r
 216   */\r
 217 void SystemInit(void)\r
 218 {\r
 219 int temp;\r
 220         \r
 221 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
 222 SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */\r
 223                (3UL << 11*2)  );               /* set CP11 Full Access */\r
 224 #endif\r
 225         \r
 226 /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
 227 SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
 228         \r
 229 /* Setup the WDT */\r
 230 #if WDT_SETUP\r
 231 \r
 232 WDT->CTR &= ~WDTENB_nVal; \r
 233 \r
 234 #endif\r
 235 \r
 236 \r
 237 /* Setup the Flash Wait State */\r
 238 #if PMU_FLASH\r
 239 temp = FLASH0->FCON; \r
 240 temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
 241 temp |= PMU_FLASH_WS+3;\r
 242 FLASH0->FCON = temp;\r
 243 #endif\r
 244 \r
 245         \r
 246 /* Setup the clockout */\r
 247 #if SCU_CLOCKOUT_SETUP\r
 248 \r
 249 SCU_CLK->EXTCLKCR       |= SCU_CLOCKOUT_SOURCE;\r
 250 /*set PLL div for clkout */\r
 251 SCU_CLK->EXTCLKCR       |= SCU_CLOCKOUT_DIV<<16;\r
 252 \r
 253 if (SCU_CLOCKOUT_PIN) {\r
 254                                                 PORT0->IOCR8 = 0x00000088;   /*P0.8 --> ALT1 select +  HWSEL */\r
 255                                             PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
 256                                             PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk);  /*set to strong driver */\r
 257                                                 }\r
 258 else {\r
 259                 PORT1->IOCR12 = 0x88000000;                    /*P1.15--> ALT1 select */\r
 260             PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk);  /*set to strong driver */\r
 261                 }\r
 262 \r
 263 #endif\r
 264 \r
 265 \r
 266 /* Setup the System clock */ \r
 267 #if SCU_CLOCK_SETUP\r
 268 SystemClockSetup();\r
 269 #endif\r
 270 \r
 271 /*----------------------------------------------------------------------------\r
 272   Clock Variable definitions\r
 273  *----------------------------------------------------------------------------*/\r
 274 SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
 275 \r
 276 \r
 277 /* Setup the USB PL */ \r
 278 #if SCU_USB_CLOCK_SETUP\r
 279 USBClockSetup();\r
 280 #endif\r
 281 \r
 282 \r
 283 \r
 284 }\r
 285 \r
 286 \r
 287 /**\r
 288   * @brief  Update SystemCoreClock according to Clock Register Values\r
 289   * @note   -  \r
 290   * @param  None\r
 291   * @retval None\r
 292   */\r
 293 void SystemCoreClockUpdate(void)\r
 294 {\r
 295 unsigned int PDIV;\r
 296 unsigned int NDIV;\r
 297 unsigned int K2DIV;\r
 298 unsigned int long VCO;\r
 299 \r
 300 \r
 301 /*----------------------------------------------------------------------------\r
 302   Clock Variable definitions\r
 303  *----------------------------------------------------------------------------*/\r
 304 if (SCU_CLK->SYSCLKCR ==  0x00010000)\r
 305 {\r
 306         if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
 307                 /* check if PLL is locked */\r
 308                 /* read back divider settings */\r
 309                  PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
 310                  NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
 311                  K2DIV  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
 312 \r
 313                 if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
 314                 /* the selected clock is the Backup clock fofi */\r
 315                 VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
 316                 SystemCoreClock = VCO/K2DIV;\r
 317                 /* in case the sysclock div is used */\r
 318                 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
 319                 \r
 320                 }\r
 321                 else\r
 322                 {\r
 323                 /* the selected clock is the PLL external oscillator */         \r
 324                 VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
 325                 SystemCoreClock = VCO/K2DIV;\r
 326                 /* in case the sysclock div is used */\r
 327                 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
 328                 } \r
 329         \r
 330         \r
 331         }\r
 332 }\r
 333 else\r
 334 {\r
 335 SystemCoreClock = CLOCK_BACK_UP;\r
 336 }\r
 337 \r
 338 \r
 339 }\r
 340 \r
 341 \r
 342 /**\r
 343   * @brief  -\r
 344   * @note   -  \r
 345   * @param  None\r
 346   * @retval None\r
 347   */\r
 348 #if (SCU_CLOCK_SETUP == 1)\r
 349 static int SystemClockSetup(void)\r
 350 {\r
 351 int temp;\r
 352 unsigned int long VCO;\r
 353 int stepping_K2DIV;     \r
 354 \r
 355 /* this weak function enables DAVE3 clock App usage */  \r
 356 if(AllowPLLInitByStartup()){\r
 357          \r
 358 /* check if PLL is switched on */\r
 359 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
 360 /* enable PLL first */\r
 361   SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
 362 \r
 363 } \r
 364 \r
 365 /* Enable OSC_HP if not already on*/\r
 366   if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
 367   {\r
 368         /********************************************************************************************************************/\r
 369         /*   Use external crystal for PLL clock input                                                                            */\r
 370         /********************************************************************************************************************/\r
 371 \r
 372    if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
 373            SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
 374            /* setup OSC WDG devider */\r
 375            SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
 376            /* select external OSC as PLL input */\r
 377            SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
 378            /* restart OSC Watchdog */\r
 379            SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
 380 \r
 381        /* Timeout for wait loop ~150ms */\r
 382            /********************************/\r
 383            SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 384            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 385            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 386                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
 387            do \r
 388            {\r
 389        ;/* wait for ~150ms  */\r
 390            }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
 391 \r
 392            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 393            if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
 394            return(0);/* Return Error */\r
 395 \r
 396     }\r
 397   }\r
 398   else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
 399         {\r
 400         /********************************************************************************************************************/\r
 401         /*   Use factory trimming Back-up clock for PLL clock input                                                                            */\r
 402         /********************************************************************************************************************/\r
 403                 /* PLL Back up clock selected */\r
 404                 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
 405                         \r
 406         }\r
 407   else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
 408   {\r
 409         /********************************************************************************************************************/\r
 410         /*   Use automatic trimming Back-up clock for PLL clock input                                                                            */\r
 411         /********************************************************************************************************************/\r
 412         /* check for HIB Domain enabled  */\r
 413         if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
 414                 SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
 415 \r
 416    /* check for HIB Domain is not in reset state  */\r
 417         if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
 418             SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
 419 \r
 420                         /* PLL Back up clock selected */\r
 421                 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
 422         \r
 423                 if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
 424                         {\r
 425                         /****************************************************************************************************************/\r
 426                         /*   Use fOSI as source of the standby clock                                                                             */\r
 427                         /****************************************************************************************************************/\r
 428                         SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
 429                         \r
 430                         SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
 431                         for(temp=0;temp<=0xFFFF;temp++);\r
 432 \r
 433                         SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
 434                         }\r
 435                 else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
 436                         {\r
 437                         /****************************************************************************************************************/\r
 438                         /*   Use fULP as source of the standby clock                                                                            */\r
 439                         /****************************************************************************************************************/\r
 440                         /*check OSCUL if running correct*/\r
 441                         if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
 442                                 {\r
 443                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
 444 \r
 445                                         SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
 446                                         /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
 447                                         /* select OSCUL clock for RTC*/\r
 448                                         SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
 449                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
 450                                         /*enable OSCULP WDG Alarm Enable*/\r
 451                                         SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
 452                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
 453                                         /*wait now for clock is stable */\r
 454                                         do\r
 455                                         {\r
 456                                         SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
 457                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
 458                                         for(temp=0;temp<=0xFFFF;temp++);\r
 459                                         }\r
 460                                         while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
 461 \r
 462                                         SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
 463                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
 464                                 }       \r
 465                         // now OSCULP is running and can be used                 \r
 466                         SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
 467                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
 468                         \r
 469                         SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
 470                         /*TRIAL for delay loop*/\r
 471                         for(temp=0;temp<=0xFFFF;temp++);\r
 472                         \r
 473                         SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
 474                         /*TRIAL for delay loop*/\r
 475                         for(temp=0;temp<=0xFFFF;temp++);\r
 476                         \r
 477                         }\r
 478   }\r
 479 \r
 480         /********************************************************************************************************************/\r
 481         /*   Setup and look the main PLL                                                                                    */\r
 482         /********************************************************************************************************************/\r
 483 \r
 484 if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
 485         /* Systen is still running from internal clock */\r
 486                    /* select FOFI as system clock */\r
 487                    if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
 488 \r
 489 \r
 490                          /*calulation for stepping*/\r
 491                          if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 492                          if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
 493                                         VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 494          \r
 495                          stepping_K2DIV = (VCO/24000000)-1;     \r
 496                          /* Go to bypass the Main PLL */\r
 497                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
 498                    /* disconnect OSC_HP to PLL */\r
 499                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
 500                    /* Setup devider settings for main PLL */\r
 501                    SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 502                    /* we may have to set OSCDISCDIS */\r
 503                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
 504                    /* connect OSC_HP to PLL */\r
 505                    SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
 506                    /* restart PLL Lock detection */\r
 507                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
 508                    /* wait for PLL Lock */\r
 509                    /* setup time out loop */\r
 510                /* Timeout for wait loo ~150ms */\r
 511                    /********************************/\r
 512                    SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 513                    SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 514                    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 515                                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
 516                    \r
 517                    while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
 518                SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 519 \r
 520                    if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
 521                                 {\r
 522                                 /* Go back to the Main PLL */\r
 523                                 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
 524                                 }\r
 525                                 else return(0);\r
 526                  \r
 527         \r
 528            /*********************************************************\r
 529            here we need to setup the system clock divider\r
 530            *********************************************************/\r
 531         \r
 532                 SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
 533                 SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;     \r
 534                 SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
 535         \r
 536 \r
 537                 /* Switch system clock to PLL */\r
 538            SCU_CLK->SYSCLKCR |=  0x00010000; \r
 539                                 \r
 540            /* we may have to reset OSCDISCDIS */\r
 541            SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
 542                                 \r
 543                                                                                                                                   \r
 544                  /*********************************************************/\r
 545                  /* Delay for next K2 step ~50µs */\r
 546                  /*********************************************************/\r
 547                  SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 548                  SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 549                  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 550                                                                                  SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 551         \r
 552                  while (SysTick->VAL >= 100);                                                              /* wait for ~50µs  */\r
 553                  SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 554                  /*********************************************************/\r
 555 \r
 556            /*********************************************************\r
 557            here the ramp up of the system clock starts FSys < 60MHz\r
 558            *********************************************************/\r
 559                 if (CLOCK_FSYS > 60000000){\r
 560                          /*calulation for stepping*/\r
 561                          if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 562                          if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
 563                                         VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 564          \r
 565                          stepping_K2DIV = (VCO/60000000)-1;     \r
 566 \r
 567                          /* Setup devider settings for main PLL */\r
 568                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 569                  }\r
 570                  else\r
 571                  {\r
 572                                 /* Setup devider settings for main PLL */\r
 573                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 574                     SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
 575                           return(1);\r
 576                  }\r
 577 \r
 578                  /*********************************************************/\r
 579                  /* Delay for next K2 step ~50µs */\r
 580                  /*********************************************************/\r
 581            SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
 582            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 583            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 584                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 585         \r
 586            while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
 587            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 588            /********************************/\r
 589         \r
 590    /*********************************************************\r
 591            here the ramp up of the system clock starts FSys < 90MHz\r
 592            *********************************************************/\r
 593                 if (CLOCK_FSYS > 90000000){\r
 594                          /*calulation for stepping*/\r
 595                          if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 596                          if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
 597                                         VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 598 \r
 599                          stepping_K2DIV = (VCO/90000000)-1;                     \r
 600 \r
 601                          /* Setup devider settings for main PLL */\r
 602                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 603                  }\r
 604                  else\r
 605                  {\r
 606                                 /* Setup devider settings for main PLL */\r
 607                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 608               SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
 609                                 return(1);\r
 610                  }\r
 611         \r
 612                  /*********************************************************/\r
 613                  /* Delay for next K2 step ~50µs */\r
 614                  /*********************************************************/\r
 615            SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
 616            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 617            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 618                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 619         \r
 620            while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
 621            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 622            /********************************/\r
 623         \r
 624            /* Setup devider settings for main PLL */\r
 625            SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 626         \r
 627            SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
 628         }\r
 629  }/* end this weak function enables DAVE3 clock App usage */    \r
 630    return(1);\r
 631 \r
 632 }\r
 633 #endif\r
 634 \r
 635 /**\r
 636   * @brief  -\r
 637   * @note   -  \r
 638   * @param  None\r
 639   * @retval None\r
 640   */\r
 641 #if (SCU_USB_CLOCK_SETUP == 1)\r
 642 static int USBClockSetup(void)\r
 643 {\r
 644 /* this weak function enables DAVE3 clock App usage */  \r
 645 if(AllowPLLInitByStartup()){\r
 646         \r
 647 /* check if PLL is switched on */\r
 648 if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
 649         /* enable PLL first */\r
 650   SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
 651 }\r
 652 \r
 653 /* check and if not already running enable OSC_HP */\r
 654    if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
 655                  /* check if Main PLL is switched on for OSC WD*/\r
 656                  if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
 657                         /* enable PLL first */\r
 658                         SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
 659                  }\r
 660            SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
 661            /* setup OSC WDG devider */\r
 662            SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
 663            /* restart OSC Watchdog */\r
 664            SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
 665         \r
 666        /* Timeout for wait loop ~150ms */\r
 667            /********************************/\r
 668            SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 669            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 670            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 671                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
 672            do \r
 673            {\r
 674        ;/* wait for ~150ms  */\r
 675            }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
 676 \r
 677            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 678            if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
 679            return(0);/* Return Error */\r
 680         \r
 681   }\r
 682 \r
 683 \r
 684 /* Setup USB PLL */\r
 685    /* Go to bypass the Main PLL */\r
 686    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
 687    /* disconnect OSC_FI to PLL */\r
 688    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
 689    /* Setup devider settings for main PLL */\r
 690    SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
 691    /* Setup USBDIV settings USB clock */\r
 692    SCU_CLK->USBCLKCR = SCU_USBDIV;\r
 693    /* we may have to set OSCDISCDIS */\r
 694    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
 695    /* connect OSC_FI to PLL */\r
 696    SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
 697    /* restart PLL Lock detection */\r
 698    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
 699    /* wait for PLL Lock */\r
 700    while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
 701    \r
 702  }/* end this weak function enables DAVE3 clock App usage */    \r
 703    return(1);\r
 704 \r
 705 }\r
 706 #endif\r
 707 \r