#include <asm/io.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
-const struct stm32_gpio_ctl gpio_ctl_gpout = {
- .mode = STM32_GPIO_MODE_OUT,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_50M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF0
-};
-
-const struct stm32_gpio_ctl gpio_ctl_usart = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_50M,
- .pupd = STM32_GPIO_PUPD_UP,
- .af = STM32_GPIO_USART
-};
-
-static const struct stm32_gpio_dsc usart_gpio[] = {
- {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */
- {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */
-};
-
-int uart_setup_gpio(void)
-{
- int i;
- int rv = 0;
-
- for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
- rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
- if (rv)
- goto out;
- }
-
-out:
- return rv;
-}
-
-const struct stm32_gpio_ctl gpio_ctl_fmc = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_100M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF12
-};
-
-static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
- /* Chip is LQFP144, see DM00077036.pdf for details */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
- {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
-};
-
-static int fmc_setup_gpio(void)
-{
- int rv = 0;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
- rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
- &gpio_ctl_fmc);
- if (rv)
- goto out;
- }
-
-out:
- return rv;
-}
-
int dram_init(void)
{
int rv;
struct udevice *dev;
- rv = fmc_setup_gpio();
- if (rv)
- return rv;
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
if (rv) {
debug("DRAM init failed: %d\n", rv);
int board_early_init_f(void)
{
- int res;
-
- res = uart_setup_gpio();
- if (res)
- return res;
return 0;
}
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * Copyright 2015 ATS Advanced Telematics Systems GmbH
- * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const unsigned long io_base[] = {
- STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
- STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
- STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-#define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15)
-#define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
- x->pupd > 2 || x->speed > 3)
-
-int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
- const struct stm32_gpio_ctl *ctl)
-{
- struct stm32_gpio_regs *gpio_regs;
- u32 i;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
- if (CHECK_CTL(ctl)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
- i = (dsc->pin & 0x07) * 4;
- clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
-
- i = dsc->pin * 2;
-
- clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
- clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
- clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
- clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
-
- rv = 0;
-out:
- return rv;
-}
-
-int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
-{
- struct stm32_gpio_regs *gpio_regs;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
- if (state)
- writel(1 << dsc->pin, &gpio_regs->bsrr);
- else
- writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
-
- rv = 0;
-out:
- return rv;
-}
-
-int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
-{
- struct stm32_gpio_regs *gpio_regs;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
- rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
-out:
- return rv;
-}
-
-/* Common GPIO API */
-
-int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
- return 0;
-}
-
-int gpio_direction_input(unsigned gpio)
-{
- struct stm32_gpio_dsc dsc;
- struct stm32_gpio_ctl ctl;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
- ctl.af = STM32_GPIO_AF0;
- ctl.mode = STM32_GPIO_MODE_IN;
- ctl.otype = STM32_GPIO_OTYPE_PP;
- ctl.pupd = STM32_GPIO_PUPD_NO;
- ctl.speed = STM32_GPIO_SPEED_50M;
-
- return stm32_gpio_config(&dsc, &ctl);
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- struct stm32_gpio_dsc dsc;
- struct stm32_gpio_ctl ctl;
- int res;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
- ctl.af = STM32_GPIO_AF0;
- ctl.mode = STM32_GPIO_MODE_OUT;
- ctl.pupd = STM32_GPIO_PUPD_NO;
- ctl.speed = STM32_GPIO_SPEED_50M;
-
- res = stm32_gpio_config(&dsc, &ctl);
- if (res < 0)
- goto out;
- res = stm32_gpout_set(&dsc, value);
-out:
- return res;
-}
-
-int gpio_get_value(unsigned gpio)
-{
- struct stm32_gpio_dsc dsc;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
-
- return stm32_gpin_get(&dsc);
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
- struct stm32_gpio_dsc dsc;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
-
- return stm32_gpout_set(&dsc, value);
-}
projects / u-boot / commitdiff