ARM: zynq: DT: Add ethernet phy reset information

Added phy reset gpio information for gem0.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index eba7037daba1efec0fa29483371c8e3750ad8055..ee050aa12fafe87794d11c7abc974724fbb2eaab 100644 (file)
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -91,6 +91,8 @@
        phy-handle = <&ethernet_phy>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem0_default>;
+       phy-reset-gpio = <&gpio0 11 0>;
+       phy-reset-active-low;
 
        ethernet_phy: ethernet-phy@7 {
                reg = <7>;