ASH405 board added (PPC405EP based).

diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile
new file mode 100644 (file)
index 0000000..39d2fec
--- /dev/null
+++ b/board/esd/ash405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   = $(BOARD).o flash.o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $^
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
new file mode 100644 (file)
index 0000000..39810c7
--- /dev/null
+++ b/board/esd/ash405/ash405.c
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <cmd_boot.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, int *);
+
+
+int board_pre_init (void)
+{
+       /*
+        * IRQ 0-15  405GP internally generated; active high; level sensitive
+        * IRQ 16    405GP internally generated; active low; level sensitive
+        * IRQ 17-24 RESERVED
+        * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+        * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+        * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+        * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+        * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+        * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+        * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+        */
+       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(uicer, 0x00000000);       /* disable all ints */
+       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+       /*
+        * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+        */
+       mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+       return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+       return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+       volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+       volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+       volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
+       volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
+       unsigned char *dst;
+       ulong len = sizeof(fpgadata);
+       int status;
+       int index;
+       int i;
+
+       dst = malloc(CFG_FPGA_MAX_SIZE);
+       if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+               printf ("GUNZIP ERROR - must RESET board to recover\n");
+               do_reset (NULL, 0, 0, NULL);
+       }
+
+       status = fpga_boot(dst, len);
+       if (status != 0) {
+               printf("\nFPGA: Booting failed ");
+               switch (status) {
+               case ERROR_FPGA_PRG_INIT_LOW:
+                       printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+                       break;
+               case ERROR_FPGA_PRG_INIT_HIGH:
+                       printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+                       break;
+               case ERROR_FPGA_PRG_DONE:
+                       printf("(Timeout: DONE not high after programming FPGA)\n ");
+                       break;
+               }
+
+               /* display infos on fpgaimage */
+               index = 15;
+               for (i=0; i<4; i++) {
+                       len = dst[index];
+                       printf("FPGA: %s\n", &(dst[index+1]));
+                       index += len+3;
+               }
+               putc ('\n');
+               /* delayed reboot */
+               for (i=20; i>0; i--) {
+                       printf("Rebooting in %2d seconds \r",i);
+                       for (index=0;index<1000;index++)
+                               udelay(1000);
+               }
+               putc ('\n');
+               do_reset(NULL, 0, 0, NULL);
+       }
+
+       puts("FPGA:  ");
+
+       /* display infos on fpgaimage */
+       index = 15;
+       for (i=0; i<4; i++) {
+               len = dst[index];
+               printf("%s ", &(dst[index+1]));
+               index += len+3;
+       }
+       putc ('\n');
+
+       free(dst);
+
+       /*
+        * Reset FPGA via FPGA_DATA pin
+        */
+       SET_FPGA(FPGA_PRG | FPGA_CLK);
+       udelay(1000); /* wait 1ms */
+       SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+       udelay(1000); /* wait 1ms */
+
+       /*
+        * Reset external DUARTs
+        */
+       out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+       udelay(10); /* wait 10us */
+       out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+       udelay(1000); /* wait 1ms */
+
+       /*
+        * Set NAND-FLASH GPIO signals to default
+        */
+       out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+       out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+       /*
+        * Enable interrupts in exar duart mcr[3]
+        */
+       *duart0_mcr = 0x08;
+       *duart1_mcr = 0x08;
+       *duart2_mcr = 0x08;
+       *duart3_mcr = 0x08;
+
+       return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+       unsigned char str[64];
+       int i = getenv_r ("serial#", str, sizeof(str));
+
+       puts ("Board: ");
+
+       if (i == -1) {
+               puts ("### No HW ID - assuming ASH405");
+       } else {
+               puts(str);
+       }
+
+       putc ('\n');
+
+       return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+       unsigned long val;
+
+       mtdcr(memcfga, mem_mb0cf);
+       val = mfdcr(memcfgd);
+
+#if 0
+       printf("\nmb0cf=%x\n", val); /* test-only */
+       printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+       return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+       /* TODO: XXX XXX XXX */
+       printf ("test: 16 MB - ok\n");
+
+       return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern void nand_probe(ulong physadr);
+void nand_init(void)
+{
+       printf("Probing at 0x%.8x\n", CFG_NAND_BASE);
+       nand_probe(CFG_NAND_BASE);
+}
+#endif

diff --git a/board/esd/ash405/config.mk b/board/esd/ash405/config.mk
new file mode 100644 (file)
index 0000000..1d743a9
--- /dev/null
+++ b/board/esd/ash405/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ASH405 boards
+#
+
+TEXT_BASE = 0xFFFC0000

diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c
new file mode 100644 (file)
index 0000000..f904aff
--- /dev/null
+++ b/board/esd/ash405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+       unsigned long size_b0;
+       int i;
+        uint pbcr;
+        unsigned long base_b0;
+       int size_val = 0;
+
+       /* Init: no FLASHes known */
+       for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+               flash_info[i].flash_id = FLASH_UNKNOWN;
+       }
+
+       /* Static FLASH Bank configuration here - FIXME XXX */
+
+       size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+       if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+               printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+                       size_b0, size_b0<<20);
+       }
+
+        /* Setup offsets */
+        flash_get_offsets (-size_b0, &flash_info[0]);
+
+        /* Re-do sizing to get full correct info */
+        mtdcr(ebccfga, pb0cr);
+        pbcr = mfdcr(ebccfgd);
+        mtdcr(ebccfga, pb0cr);
+        base_b0 = -size_b0;
+       switch (size_b0) {
+       case 1 << 20:
+               size_val = 0;
+               break;
+       case 2 << 20:
+               size_val = 1;
+               break;
+       case 4 << 20:
+               size_val = 2;
+               break;
+       case 8 << 20:
+               size_val = 3;
+               break;
+       case 16 << 20:
+               size_val = 4;
+               break;
+       }
+       pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+        mtdcr(ebccfgd, pbcr);
+
+        /* Monitor protection ON by default */
+        (void)flash_protect(FLAG_PROTECT_SET,
+                            -CFG_MONITOR_LEN,
+                            0xffffffff,
+                            &flash_info[0]);
+
+        flash_info[0].size = size_b0;
+
+       return (size_b0);
+}

diff --git a/board/esd/ash405/fpgadata.c b/board/esd/ash405/fpgadata.c
new file mode 100644 (file)
index 0000000..b2cba4a
--- /dev/null
+++ b/board/esd/ash405/fpgadata.c
@@ -0,0 +1,2513 @@
+  0x1f,0x8b,0x08,0x08,0xe1,0xe0,0xcd,0x3e,0x00,0x03,0x61,0x73,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x01,0x78,0x54,0xe5,
+  0xb5,0x2f,0x8c,0xaf,0xfd,0xee,0x9d,0xf0,0x66,0xf6,0x24,0xb3,0x49,0x82,0x8d,0x8a,
+  0xb8,0x33,0x09,0x38,0xc4,0x49,0x18,0x26,0x18,0x10,0x43,0xb2,0x49,0x52,0x3b,0x42,
+  0x94,0x94,0x7a,0xce,0xe1,0x9c,0xcf,0xeb,0x1d,0x95,0xd3,0x43,0xcf,0xa5,0x3d,0xd1,
+  0xfa,0x3f,0x1f,0x6d,0xbd,0x3d,0x6f,0x66,0x02,0x0c,0x04,0x64,0x40,0x5a,0xa3,0xa5,
+  0x9e,0x01,0xa2,0x46,0xa5,0xa7,0x43,0x00,0x09,0x82,0xba,0x13,0xd2,0x76,0x80,0x28,
+  0xd1,0x7a,0x5a,0x54,0x8e,0x0e,0x9a,0x7a,0xa2,0xa6,0x1a,0x11,0xdb,0x00,0x11,0xbe,
+  0xb5,0xf6,0x24,0x99,0x3d,0xf4,0xde,0x73,0xcf,0xfd,0xee,0xff,0xfb,0x3f,0xe7,0xff,
+  0x7c,0x97,0x3e,0x7d,0xfa,0xf6,0x9d,0xcd,0x66,0xef,0x77,0xbf,0xef,0x5a,0xbf,0xb5,
+  0xd6,0x6f,0xad,0x05,0x39,0xae,0x91,0xd4,0x7f,0x00,0xa4,0x7b,0x40,0xbb,0xe7,0xbb,
+  0xab,0xe6,0xf9,0x6e,0xfa,0xcf,0x73,0xff,0xb3,0xcf,0x57,0xf1,0x9d,0xfb,0x56,0xc2,
+  0xbd,0xa0,0xfa,0xbf,0x7b,0x93,0xef,0xaf,0x1f,0xbc,0x7f,0xee,0xbc,0x79,0x70,0x1f,
+  0xfe,0x3f,0x9f,0xaf,0x72,0x8e,0xef,0xa6,0x39,0xfe,0x4a,0x58,0x09,0x39,0x73,0x7d,
+  0x0b,0x6f,0xf2,0x2d,0x9c,0x37,0x17,0xfe,0x1a,0xa4,0xca,0x8e,0xcb,0xf8,0xe7,0xd9,
+  0xc7,0xfe,0xec,0x9b,0x3e,0x10,0x12,0x00,0x4c,0xf1,0x49,0x41,0xfa,0x5f,0xd5,0x27,
+  0xe9,0x12,0x88,0xda,0x72,0x1f,0x98,0xf4,0xff,0x61,0xfc,0xf7,0x1c,0x1f,0xe8,0xf6,
+  0xff,0x2f,0xf9,0xc0,0x80,0x26,0x30,0x36,0x41,0xbe,0x0f,0xfe,0xc7,0x7f,0x0c,0x45,
+  0x4c,0x0c,0xff,0x27,0xaf,0xbf,0x7c,0x5c,0xfc,0x77,0xaf,0x4a,0xff,0xa9,0x3d,0x1b,
+  0x9b,0x18,0xb2,0x7f,0xc7,0xfd,0x25,0x03,0x26,0xef,0xff,0xd6,0xbf,0xeb,0xfe,0x7f,
+  0x98,0xb8,0xff,0xff,0xec,0xf5,0x90,0xff,0xef,0xb8,0x1c,0x40,0x99,0x7c,0x9e,0x7c,
+  0x70,0x00,0x13,0x10,0x03,0xcf,0xbf,0x31,0xa8,0xed,0x9b,0xf8,0x8b,0xbd,0x59,0xa7,
+  0xc4,0xbf,0x88,0x9b,0x82,0x79,0x46,0xc1,0x98,0xd1,0x5f,0x57,0x9b,0x70,0x9a,0x05,
+  0xf3,0xe0,0x18,0xdc,0x02,0xae,0xb3,0xf5,0x55,0xd0,0xaf,0x57,0xea,0xce,0xbd,0xb2,
+  0x4f,0x69,0x1e,0xbf,0xde,0x2c,0xfa,0x10,0x54,0xc1,0xce,0xf0,0x88,0x5a,0x6e,0x46,
+  0xa0,0xf6,0xb7,0xae,0x48,0xdd,0x93,0xc9,0x63,0xc2,0xad,0xab,0x5f,0x32,0x85,0x45,
+  0x7a,0xcb,0x80,0x9f,0x65,0xba,0x32,0xb1,0x8a,0xc7,0x61,0x36,0x3c,0x26,0xe9,0xc6,
+  0x35,0x1a,0xeb,0x6f,0x7d,0x44,0xf7,0x26,0x78,0x0b,0x03,0x2d,0xa2,0xe9,0xe6,0x52,
+  0x9f,0x5b,0x51,0x5a,0xf2,0x75,0x07,0xf7,0xbb,0x19,0xe8,0x13,0xf7,0xcf,0xea,0x50,
+  0x36,0x80,0x3b,0x09,0x51,0xe6,0x85,0x9f,0x64,0x95,0x99,0xf5,0x82,0x65,0xb3,0xf6,
+  0xbe,0x5d,0xa6,0x1a,0x77,0x94,0x0a,0x15,0xca,0x46,0x3c,0x71,0x96,0x7e,0x9e,0xaf,
+  0x4f,0x1b,0x12,0xbf,0xd6,0xba,0x86,0xf2,0x16,0xc8,0xc3,0x70,0x0a,0x2a,0x4c,0x67,
+  0xab,0x3a,0x0b,0x8e,0x99,0x0b,0x4d,0x57,0x5c,0x2e,0x95,0x7a,0x85,0x5f,0x6f,0x8c,
+  0xab,0x9a,0x31,0x71,0x7d,0x4c,0xea,0x16,0x97,0x22,0xb7,0x98,0x5b,0xce,0xcb,0x3b,
+  0xb4,0xe1,0xa9,0x8b,0xcc,0x2d,0xaf,0xe3,0x5f,0xfc,0x14,0x6a,0x4d,0xd7,0x88,0xfc,
+  0x07,0xb8,0x64,0xd4,0xc2,0x96,0x11,0x79,0x08,0x82,0xe3,0xd7,0x0f,0x68,0x9d,0xd2,
+  0xc7,0xac,0xc6,0x9c,0x11,0x97,0xbd,0xf0,0xb1,0x51,0xd3,0x97,0xdb,0xf1,0xb5,0xd2,
+  0xc8,0x9b,0xf0,0x43,0xd3,0xe9,0x93,0x4b,0xf1,0xf5,0xfc,0x3e,0x67,0xbc,0xc4,0x37,
+  0xf9,0xfc,0x09,0x49,0xf9,0xea,0x06,0xc3,0x9b,0xcc,0x8d,0x3b,0xaa,0x79,0x1b,0xcc,
+  0xc1,0xcb,0xbe,0xf6,0x1d,0xf8,0x75,0xa4,0xc2,0xe4,0xa3,0xf2,0x4a,0xb1,0x51,0xab,
+  0x1a,0xf1,0x8c,0xc8,0x0f,0xe0,0xee,0x4f,0xfd,0xe9,0x53,0x02,0x7c,0x77,0x9d,0xb7,
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+  0xe9,0x89,0x57,0x26,0xd0,0x0f,0xdf,0x7f,0x59,0xf9,0xe1,0xb5,0xc8,0x0f,0x13,0xfa,
+  0xf8,0x47,0x22,0x3f,0x3c,0x8c,0x7e,0xb8,0xb1,0xae,0xfc,0xf0,0x61,0xe4,0x87,0x5d,
+  0x3e,0xf6,0x6d,0xf3,0x24,0x6a,0xe1,0xdf,0x1a,0x1b,0xeb,0x23,0x6b,0x6d,0x51,0x04,
+  0x63,0x7c,0x84,0x1f,0xca,0xff,0xfd,0x9f,0xab,0xd0,0xff,0xab,0x50,0x14,0xcf,0x3f,
+  0xca,0x0f,0x87,0x43,0x3f,0xdc,0xbb,0x67,0x72,0x65,0x71,0x08,0xfb,0x9f,0xdb,0xd4,
+  0xff,0x8b,0xef,0x3e,0x7a,0x0f,0x96,0x58,0x70,0x7e,0xc3,0xbf,0xa3,0xc9,0xef,0xbe,
+  0x15,0x13,0x13,0x13,0x13,0x13,0x13,0x13,0x13,0x13,0x13,0x93,0xff,0xf7,0xc8,0xb5,
+  0x03,0x33,0x6b,0x07,0x13,0x13,0x13,0x13,0x13,0x13,0x13,0x13,0x13,0x13,0x93,0x47,
+  0x47,0xae,0x1d,0x7a,0xcc,0xda,0xc1,0xc4,0xc4,0xc4,0xc4,0xc4,0xc4,0xc4,0xc4,0xc4,
+  0xc4,0xe4,0xd1,0x91,0x6b,0x07,0x5b,0xae,0x1d,0xfe,0xd7,0x43,0x31,0x31,0x31,0x31,
+  0x31,0x31,0x31,0x31,0x31,0x31,0x31,0xf9,0x2f,0xc6,0xc3,0x47,0x2e,0x93,0xd3,0xff,
+  0xf0,0x88,0xc0,0x4f,0xcd,0xc5,0x3d,0xc2,0xbf,0xf5,0xdf,0x13,0xda,0xaf,0xb5,0x3c,
+  0xd2,0xa4,0xd1,0x36,0xbf,0x38,0xb1,0xb9,0xdf,0xbf,0x01,0x95,0xa7,0xef,0x04,0xf1,
+  0x33,0x01,0x00,

diff --git a/board/esd/ash405/u-boot.lds b/board/esd/ash405/u-boot.lds
new file mode 100644 (file)
index 0000000..0e02841
--- /dev/null
+++ b/board/esd/ash405/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within */
+    /* the sector layout of our flash chips!   XXX FIXME XXX   */
+
+    cpu/ppc4xx/start.o (.text)
+    cpu/ppc4xx/traps.o (.text)
+    cpu/ppc4xx/interrupts.o    (.text)
+    cpu/ppc4xx/serial.o        (.text)
+    cpu/ppc4xx/cpu_init.o      (.text)
+    cpu/ppc4xx/speed.o (.text)
+    cpu/ppc4xx/405gp_enet.o    (.text)
+    common/dlmalloc.o  (.text)
+    lib_generic/crc32.o                (.text)
+    lib_ppc/extable.o  (.text)
+    lib_generic/zlib.o         (.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
new file mode 100644 (file)
index 0000000..398bf76
--- /dev/null
+++ b/include/configs/ASH405.h
@@ -0,0 +1,381 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP           1       /* This is a PPC405 CPU         */
+#define CONFIG_4xx             1       /* ...member of PPC4xx family   */
+#define CONFIG_ASH405          1       /* ...on a ASH405 board         */
+
+#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ     33333334 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE                9600
+#define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_RAMBOOTCOMMAND                                                  \
+       "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "     \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
+       "bootm ffc00000 ffca0000"
+#define CONFIG_NFSBOOTCOMMAND                                                  \
+       "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
+       "bootm ffc00000"
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
+#define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
+
+#define CONFIG_MII             1       /* MII PHY management           */
+#define        CONFIG_PHY_ADDR         0       /* PHY address                  */
+
+#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_DHCP    | \
+                               CFG_CMD_IRQ     | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_NAND    | \
+                               CFG_CMD_DATE    | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_EEPROM  )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_WATCHDOG                        /* watchdog disabled            */
+
+#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR   0xF0000500 /* RTC Base Address         */
+
+#define        CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                   /* undef to save memory         */
+#define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
+
+#undef CFG_HUSH_PARSER                 /* use "hush" command parser    */
+#ifdef CFG_HUSH_PARSER
+#define        CFG_PROMPT_HUSH_PS2     "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
+#else
+#define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS    16              /* max number of command args   */
+#define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START      0x0400000       /* memtest works on     */
+#define CFG_MEMTEST_END                0x0C00000       /* 4 ... 12 MB in DRAM  */
+
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+#undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+         57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR  0x100000        /* default load address */
+#define CFG_EXTBDINFO  1               /* To use extended board_into (bd_t) */
+
+#define        CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_HOST        PCI_HOST_HOST   /* select pci host function     */
+#undef  CONFIG_PCI_PNP                 /* do pci plug-and-play         */
+                                        /* resource configuration       */
+
+#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_FLASH_BASE         0xFFFC0000
+#define CFG_MONITOR_BASE       CFG_FLASH_BASE
+#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN         (256 * 1024)    /* Reserve 256 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     256     /* max number of sectors on one chip    */
+
+#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
+#define CFG_FLASH_WRITE_TOUT   1000    /* Timeout for Flash Write (in ms)      */
+
+#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
+#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
+#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
+#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
+#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+                                   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR    0xF0000500              /* NVRAM base address   */
+#define CFG_NVRAM_SIZE         242                     /* NVRAM size           */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CFG_I2C_SPEED          400000  /* I2C speed and slave address */
+#define CFG_I2C_SLAVE          0x7F
+
+#define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT28WC08             */
+#define CFG_I2C_EEPROM_ADDR_LEN        1       /* Bytes of address             */
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW   0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
+                                       /* 16 byte page write mode using*/
+                                       /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE                16384   /* For IBM 405 CPUs, older 405 ppc's    */
+                                        /* have only 8kB, 16kB is save here     */
+#define CFG_CACHELINE_SIZE     32      /* ...                  */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM     0xFFC00000      /* FLASH bank #0        */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
+#define CFG_EBC_PB0AP           0x92015480
+//#define CFG_EBC_PB0AP           0x08055880  /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
+#define CFG_EBC_PB1AP           0x92015480
+#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
+#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
+#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+#define CAN_BA          0xF0000000          /* CAN Base Address                 */
+#define DUART0_BA       0xF0000400          /* DUART Base Address               */
+#define DUART1_BA       0xF0000408          /* DUART Base Address               */
+#define DUART2_BA       0xF0000410          /* DUART Base Address               */
+#define DUART3_BA       0xF0000418          /* DUART Base Address               */
+#define RTC_BA          0xF0000500          /* RTC Base Address                 */
+#define CFG_NAND_BASE   0xF4000000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR      0xF8000000
+#define CFG_OCM_DATA_SIZE      0x1000
+#define CFG_INIT_RAM_ADDR      CFG_OCM_DATA_ADDR /* inside of SDRAM            */
+#define CFG_INIT_RAM_END       CFG_OCM_DATA_SIZE /* End of used area in RAM    */
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH          0x40000550
+#define CFG_GPIO0_OSRL          0x00000110
+#define CFG_GPIO0_ISR1H         0x00000000
+#define CFG_GPIO0_ISR1L         0x15555445
+#define CFG_GPIO0_TSRH          0x00000000
+#define CFG_GPIO0_TSRL          0x00000000
+#define CFG_GPIO0_TCR           0xF7FE0014
+
+#define CFG_DUART_RST           (0x80000000 >> 14)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#endif
+
+#endif /* __CONFIG_H */