mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define

Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index dabcad0d222fe9399fda8ad614ee10f71f9c7a1f..7b4852416b68f74bb3f385b9d8c3e38d5ffe672b 100644 (file)
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -331,6 +331,7 @@
 #define AR933X_PLL_CPU_CONFIG_REG                      0x00
 #define AR933X_PLL_CLK_CTRL_REG                                0x08
 #define AR933X_PLL_DITHER_FRAC_REG                     0x10
+#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG            0x24
 
 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT               10
 #define AR933X_PLL_CPU_CONFIG_NINT_MASK                        0x3f

diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index a5ee14156cc90dd7c98170efcd066b37ec0d2831..073a179bafe7023f4a06aeb5f44ae20b05666cb0 100644 (file)
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -89,7 +89,7 @@ static int eth_init_ar933x(void)
        mdelay(10);
 
        /* Get Atheros S26 PHY out of reset. */
-       clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+       clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
                        0x1f, 0x10);
        mdelay(10);