powerpc/85xx: Read board switch settings on p1_p2_rdb

PCA9557 is parallel I/O expansion device on I2C bus which stores various
board switch settings like NOR Flash-Bank selection, SD Data width.

On board:
switch SW5[6] is to select width for eSDHC
        ON  - 4-bit [Enable eSPI]
        OFF - 8-bit [Disable eSPI]

switch SW4[8] is to select NOR Flash Bank for Booting
        OFF - Primary Bank
        ON  - Secondary Bank

Read board switch settings on p1_p2_rdb and configure corresponding
eSDHC width.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 806d90e6e48a67799dd65995c591e224c735a079..9f57a21925ff5ca4e2b22011d04c7b0a683d1707 100644 (file)
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -35,6 +35,7 @@
 #include <vsc7385.h>
 #include <netdev.h>
 #include <rtc.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -142,6 +143,30 @@ int board_early_init_r(void)
 {
        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
        const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       unsigned int orig_bus = i2c_get_bus_num();
+       u8 i2c_data;
+
+       i2c_set_bus_num(1);
+       if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
+               1, &i2c_data, sizeof(i2c_data)) == 0) {
+               if (i2c_data & 0x2)
+                       puts("NOR Flash Bank : Secondary\n");
+               else
+                       puts("NOR Flash Bank : Primary\n");
+
+               if (i2c_data & 0x1) {
+                       setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+                       puts("SD/MMC : 8-bit Mode\n");
+                       puts("eSPI : Disabled\n");
+               } else {
+                       puts("SD/MMC : 4-bit Mode\n");
+                       puts("eSPI : Enabled\n");
+               }
+       } else {
+               puts("Failed reading I2C Chip 0x18 on bus 1\n");
+       }
+       i2c_set_bus_num(orig_bus);
 
        /*
         * Remap Boot flash region to caching-inhibited

diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 53ec56f211e128c3d1b61391c37a6368a212757d..6f2088edd1a9098121fb434dfd17dd68f94e6143 100644 (file)
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -362,6 +362,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_SYS_EEPROM_BUS_NUM      1
 
+#define CONFIG_SYS_I2C_PCA9557_ADDR    0x18
+
 #define CONFIG_RTC_DS1337
 #define CONFIG_SYS_RTC_DS1337_NOOSC
 #define CONFIG_SYS_I2C_RTC_ADDR                0x68