Map SRAM on NC650 board

diff --git a/CHANGELOG b/CHANGELOG
index 83344c711c23f084472deea6f64d06daf82bcfc4..e5b77f825cec407a9f2d1c14134641cef8ad1a9a 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Map SRAM on NC650 board
+
 * Work around for Ethernet problems on Xaeniax board
 
 * Patch by TsiChung Liew, 23 Sep 2004:

diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 8f52014a44ac9948d882a5fbc9824d23b2ce336c..c62d879206cad4b8c463ae675722791d64ef866e 100644 (file)
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -334,6 +334,21 @@
 #define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 
+/*
+ * BR5 and OR5 (SRAM)
+ */
+#define CFG_SRAM_BASE          0x60000000
+#define CFG_SRAM_SIZE          0x00080000
+
+#define CFG_OR_TIMING_SRAM     (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+                                OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
+
+#define CFG_BR5_PRELIM  ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR5_PRELIM  (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
+
+
+
+
 /*
  * 4096 Rows from SDRAM example configuration
  * 1000 factor s -> ms