COBJS += sys_info.o
COBJS += timer.o
+COBJS-$(CONFIG_SDRC) += sdrc.o
+
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
all: $(obj).depend $(LIB)
extern omap3_sysinfo sysinfo;
-extern u32 is_mem_sdr(void);
-
/******************************************************************************
* Routine: delay
* Description: spinning delay to use before udelay works
per_clocks_enable();
if (!in_sdram)
- sdrc_init();
+ mem_init();
}
/******************************************************************************
writel(WD_UNLOCK2, &wd2_base->wspr);
}
-/******************************************************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- *****************************************************************************/
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
-
- /*
- * If a second bank of DDR is attached to CS1 this is
- * where it can be started. Early init code will init
- * memory on CS0.
- */
- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
- do_sdrc_init(CS1, NOT_EARLY);
- make_cs1_contiguous();
-
- size1 = get_sdr_cs_size(CS1);
- }
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
-
- return 0;
-}
-
/******************************************************************************
* Dummy function to handle errors for EABI incompatibility
*****************************************************************************/
#endif
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- * command line mem=xyz use all memory with out discontinuous support
- * compiled in. Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
- u32 size, a_add_low, a_add_high;
-
- size = get_sdr_cs_size(CS0);
- size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
- a_add_high = (size & 3) << 8; /* set up low field */
- a_add_low = (size & 0x3C) >> 2; /* set up high field */
- writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
/********************************************************
* mem_ok() - test used to see if timings are correct
* for a part. Helps in guessing which part
return 1;
}
-/********************************************************
- * sdrc_init() - init the sdrc chip selects CS0 and CS1
- * - early init routines, called from flash or
- * SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
- /* only init up first bank here */
- do_sdrc_init(CS0, EARLY_INIT);
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- * -code sets up SDRAM basic SDRC timings for CS0
- * -optimal settings can be placed here, or redone after i2c
- * inspection of board info
- *
- * - code called once in C-Stack only context for CS0 and a possible 2nd
- * time depending on memory configuration from stack+global context
- **************************************************************************/
-
-void do_sdrc_init(u32 cs, u32 early)
-{
- struct sdrc_actim *sdrc_actim_base;
-
- if(cs)
- sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
- else
- sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
- if (early) {
- /* reset sdrc controller */
- writel(SOFTRESET, &sdrc_base->sysconfig);
- wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
- 12000000);
- writel(0, &sdrc_base->sysconfig);
-
- /* setup sdrc to ball mux */
- writel(SDRC_SHARING, &sdrc_base->sharing);
-
- /* Disable Power Down of CKE cuz of 1 CKE on combo part */
- writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
- &sdrc_base->power);
-
- writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
- sdelay(0x20000);
- }
-
- writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
- RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
- DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
- writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
- writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
- writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
-
- writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
- writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
- /*
- * CAS latency 3, Write Burst = Read Burst, Serial Mode,
- * Burst length = 4
- */
- writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
-
- if (!mem_ok(cs))
- writel(0, &sdrc_base->cs[cs].mcfg);
-}
-
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
--- /dev/null
+/*
+ * Functions related to OMAP3 SDRC.
+ *
+ * This file has been created after exctracting and consolidating
+ * the SDRC related content from mem.c and board.c, also created
+ * generic init function (mem_init).
+ *
+ * Copyright (C) 2004-2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Original implementation by (mem.c, board.c) :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ * Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+
+extern omap3_sysinfo sysinfo;
+
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+
+/*
+ * is_mem_sdr -
+ * - Return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+ if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
+ return 1;
+ return 0;
+}
+
+/*
+ * make_cs1_contiguous -
+ * - For es2 and above remap cs1 behind cs0 to allow command line
+ * mem=xyz use all memory with out discontinuous support compiled in.
+ * Could do it at the ATAG, but there really is two banks...
+ * - Called as part of 2nd phase DDR init.
+ */
+void make_cs1_contiguous(void)
+{
+ u32 size, a_add_low, a_add_high;
+
+ size = get_sdr_cs_size(CS0);
+ size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
+ a_add_high = (size & 3) << 8; /* set up low field */
+ a_add_low = (size & 0x3C) >> 2; /* set up high field */
+ writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
+
+}
+
+
+/*
+ * get_sdr_cs_size -
+ * - Get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+ u32 size;
+
+ /* get ram size field */
+ size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
+ size &= 0x3FF; /* remove unwanted bits */
+ size <<= 21; /* multiply by 2 MiB to find size in MB */
+ return size;
+}
+
+/*
+ * get_sdr_cs_offset -
+ * - Get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+ u32 offset;
+
+ if (!cs)
+ return 0;
+
+ offset = readl(&sdrc_base->cs_cfg);
+ offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+
+ return offset;
+}
+
+/*
+ * do_sdrc_init -
+ * - Initialize the SDRAM for use.
+ * - Sets up SDRC timings for CS0
+ * - code called once in C-Stack only context for CS0 and a possible 2nd
+ * time depending on memory configuration from stack+global context
+ */
+void do_sdrc_init(u32 cs, u32 early)
+{
+ struct sdrc_actim *sdrc_actim_base;
+
+ if (cs)
+ sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+ else
+ sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+
+ if (early) {
+ /* reset sdrc controller */
+ writel(SOFTRESET, &sdrc_base->sysconfig);
+ wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
+ 12000000);
+ writel(0, &sdrc_base->sysconfig);
+
+ /* setup sdrc to ball mux */
+ writel(SDRC_SHARING, &sdrc_base->sharing);
+
+ /* Disable Power Down of CKE cuz of 1 CKE on combo part */
+ writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
+ &sdrc_base->power);
+
+ writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
+ sdelay(0x20000);
+ }
+
+ writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
+ RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
+ DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
+ writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
+ writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
+ writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
+
+ writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+ writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+ /*
+ * CAS latency 3, Write Burst = Read Burst, Serial Mode,
+ * Burst length = 4
+ */
+ writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
+
+ if (!mem_ok(cs))
+ writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+/*
+ * dram_init -
+ * - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned int size0 = 0, size1 = 0;
+
+ size0 = get_sdr_cs_size(CS0);
+ /*
+ * If a second bank of DDR is attached to CS1 this is
+ * where it can be started. Early init code will init
+ * memory on CS0.
+ */
+ if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+ do_sdrc_init(CS1, NOT_EARLY);
+ make_cs1_contiguous();
+
+ size1 = get_sdr_cs_size(CS1);
+ }
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = size0;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+ gd->bd->bi_dram[1].size = size1;
+
+ return 0;
+}
+
+/*
+ * mem_init -
+ * - Init the sdrc chip,
+ * - Selects CS0 and CS1,
+ */
+void mem_init(void)
+{
+ /* only init up first bank here */
+ do_sdrc_init(CS0, EARLY_INIT);
+}
#include <i2c.h>
extern omap3_sysinfo sysinfo;
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
static char *rev_s[CPU_3XX_MAX_REV] = {
"1.0",
}
}
-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
- if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
- return 1;
- return 0;
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 cs)
-{
- u32 size;
-
- /* get ram size field */
- size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
- size &= 0x3FF; /* remove unwanted bits */
- size <<= 21; /* multiply by 2 MiB to find size in MB */
- return size;
-}
-
-/***********************************************************************
- * get_sdr_cs_offset() - get offset of cs from cs0 start
- ************************************************************************/
-u32 get_sdr_cs_offset(u32 cs)
-{
- u32 offset;
-
- if (!cs)
- return 0;
-
- offset = readl(&sdrc_base->cs_cfg);
- offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
-
- return offset;
-}
-
/***************************************************************************
* get_gpmc0_base() - Return current address hardware will be
* fetching from. The below effectively gives what is correct, its a bit
u8 res4[0xC];
struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
};
+
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
#define PISMO1_ONEN_BASE ONENAND_MAP
#define DBG_MPDB_BASE DEBUG_BASE
+#ifndef __ASSEMBLY__
+
+/* Function prototypes */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif /* __ASSEMBLY__ */
+
#endif /* endif _MEM_H_ */
u32 is_gpmc_muxed(void);
u32 get_gpmc0_type(void);
u32 get_gpmc0_width(void);
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
u32 is_running_in_sdram(void);
u32 is_running_in_sram(void);
u32 is_running_in_flash(void);
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_EVM 1 /* working with EVM */
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_OVERO 1 /* working with overo */
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
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