}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
(uint)pci
);
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
struct pci_region *r = hose->regions;
if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
- r += fsl_pci_setup_inbound_windows(r);
-
pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BUS,
(uint)pci
);
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BUS,
(uint)pci
);
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BUS,
pci_arb ? "arbiter" : "external-arbiter"
);
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
pci_arb ? "arbiter" : "external-arbiter"
);
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BUS,
}
printf ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
if (pci->pme_msg_det)
pci->pme_msg_det = 0xffffffff;
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
if (pci->pme_msg_det)
pci->pme_msg_det = 0xffffffff;
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BUS,
pci_agent ? "Agent" : "Host",
(uint)pci);
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
}
printf("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BUS,
}
printf("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BUS,
}
printf("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
pci_arb ? "arbiter" : "external-arbiter"
);
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
}
printf ("\n");
- /* inbound */
- pci_set_region(r++,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
}
debug("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BUS,
struct pci_controller *hose = &pci2_hose;
struct pci_region *r = hose->regions;
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BUS,
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region (r++,
CONFIG_SYS_PCI1_MEM_BASE,
}
puts ("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region (r++,
CONFIG_SYS_PCIE1_MEM_BASE,
host ? "host" : "agent",
pci_arb ? "arbiter" : "external-arbiter");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
}
printf("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
}
printf("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
}
printf("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
#endif
-int fsl_pci_setup_inbound_windows(struct pci_region *r)
+static int fsl_pci_setup_inbound_windows(struct pci_region *r)
{
struct pci_region *rgn_base = r;
u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
int bridge;
int inbound = 0;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+ struct pci_region *reg = hose->regions + hose->region_count;
pci_dev_t dev = PCI_BDF(busno,0,0);
/* Initialize ATMU registers based on hose regions and flags */
pci_setup_indirect(hose, cfg_addr, cfg_data);
+ /* inbound */
+ reg += fsl_pci_setup_inbound_windows(reg);
+
+ hose->region_count = reg - hose->regions;
+
for (r=0; r<hose->region_count; r++) {
u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */
#ifndef __FSL_PCI_H_
#define __FSL_PCI_H_
-int fsl_pci_setup_inbound_windows(struct pci_region *r);
void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
void fsl_pci_config_unlock(struct pci_controller *hose);
void ft_fsl_pci_setup(void *blob, const char *pci_alias,