/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
/*
* Memory Controller Using
*
- * CS0 - Flash memory (0x40000000)
- * CS1 - SDRAM (0x00000000}
- * CS2 -
+ * CS0 - Flash memory (0x40000000)
+ * CS1 - FLASH memory (0x????????)
+ * CS2 - SDRAM (0x00000000)
* CS3 -
* CS4 -
* CS5 -
udelay (1000);
/*
- * Check Bank 0 Memory Size for re-configuration
+ * Check Bank 2 Memory Size for re-configuration
*
* try 8 column mode
*/
#if defined(CONFIG_R360MPI)
{
extern void r360_i2c_lcd_write (uchar data0, uchar data1);
+ unsigned long bgi, ctr;
+ char *p;
+
+ if ((p = getenv("lcdbgi")) != NULL) {
+ bgi = simple_strtoul (p, 0, 10) & 0xFFF;
+ } else {
+ bgi = 0xFFF;
+ }
+
+ if ((p = getenv("lcdctr")) != NULL) {
+ ctr = simple_strtoul (p, 0, 10) & 0xFFF;
+ } else {
+ ctr=0x7FF;
+ }
r360_i2c_lcd_write(0x10, 0x01);
r360_i2c_lcd_write(0x20, 0x01);
- r360_i2c_lcd_write(0x3F, 0xFF);
- r360_i2c_lcd_write(0x47, 0xFF);
+ r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
+ r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
}
#endif /* CONFIG_R360MPI */
#ifdef CONFIG_RBC823
This group will contain those tests that do not take much
time and can be run on the regular basis (e.g. CPU test)
- 3) Tests running on power-fail booting only
+ 3) Tests running on in special "slow test more" only
This group will contain POST tests that consume much time
- and cannot be run regularly (e.g. I2C test)
+ and cannot be run regularly (e.g. strong memory test, I2C test)
4) Manually executed tests
This group will contain those tests that can be run manually.
If necessary, some tests may belong to several groups simultaneously.
-For example, SDRAM test may run on both noarmal and power-fail
-booting. On normal booting, SDRAM test may perform a fast superficial
-memory test only, while running on power-fail booting it may perform
-a full memory check-up.
+For example, SDRAM test may run in both normal and "slow test" mode.
+In normal mode, SDRAM test may perform a fast superficial memory test
+only, while running in slow test mode it may perform a full memory
+check-up.
Also, all tests will be discriminated by the moment they run at.
Specifically, the following groups will be singled out:
The following flags will be defined:
-#define POST_ROM 0x01 /* test runs in ROM */
-#define POST_RAM 0x02 /* test runs in RAM */
-#define POST_POWERON 0x04 /* test runs on power-on booting */
-#define POST_NORMAL 0x08 /* test runs on normal booting */
-#define POST_SHUTDOWN 0x10 /* test runs on power-fail booting */
-#define POST_MANUAL 0x20 /* test can be executed manually */
-#define POST_REBOOT 0x80 /* test may cause rebooting */
+#define POST_POWERON 0x01 /* test runs on power-on booting */
+#define POST_NORMAL 0x02 /* test runs on normal booting */
+#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */
+#define POST_POWERTEST 0x08 /* test runs after watchdog reset */
+#define POST_ROM 0x100 /* test runs in ROM */
+#define POST_RAM 0x200 /* test runs in RAM */
+#define POST_MANUAL 0x400 /* test can be executed manually */
+#define POST_REBOOT 0x800 /* test may cause rebooting */
+#define POST_PREREL 0x1000 /* test runs before relocation */
The POST layer will export the following interface routines:
will be called on power-fail booting after running all POST
tests.
+ o) int post_hotkeys_pressed(gd_t *gd)
+
+ This routine will scan the keyboard to detect if a magic key
+ combination has been pressed, or otherwise detect if the
+ power-on long-running tests shall be executed or not ("normal"
+ versus "slow" test mode).
+
The list of available POST tests be kept in the post_tests array
filled at U-Boot build time. The format of entry in this array will
be as follows:
2.2.3.4. SPI test
TBD
-
-2.3. Design notes
-
-Currently it is unknown how we will power off the board after running
-all power-fail POST tests. This point needs further clarification.
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#define CONFIG_BOOTDELAY 0 /* immediate boot */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#if 0
-#ifdef CONFIG_LCD
-# undef CONFIG_STATUS_LED /* disturbs display */
-#else
-# define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#endif /* CONFIG_LCD */
-#endif
-
#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
CFG_CMD_DATE | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
+ CFG_CMD_JFFS2 | \
CFG_CMD_PCMCIA | \
CFG_CMD_BSP )
/*
* Miscellaneous configurable options
*/
+#define CFG_DEVICE_NULLDEV 1 /* we need the null device */
+#define CFG_CONSOLE_IS_IN_ENV 1 /* must set console from env */
+
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/* JFFS2 stuff */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+#define CFG_JFFS2_FIRST_SECTOR 24
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#ifndef __VERSION_H__
#define __VERSION_H__
-#define U_BOOT_VERSION "U-Boot 0.4.3"
+#define U_BOOT_VERSION "U-Boot 0.4.4"
#endif /* __VERSION_H__ */
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