]> git.sur5r.net Git - u-boot/commitdiff
Merge branch 'fixes' into cleanups
authorHaavard Skinnemoen <haavard.skinnemoen@atmel.com>
Wed, 17 Dec 2008 15:53:07 +0000 (16:53 +0100)
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>
Wed, 17 Dec 2008 15:53:07 +0000 (16:53 +0100)
Conflicts:

board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h

17 files changed:
1  2 
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
board/mimc/mimc200/mimc200.c
board/miromico/hammerhead/hammerhead.c
cpu/at32ap/at32ap700x/clk.c
cpu/at32ap/cpu.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
lib_avr32/board.c

index 480d5255fde49c4b4742d22e95c3c02439d918e7,fa1a2aa7c12d69cd2d2b88b0b1e437c1a27c2192..004d8daa900b2c8ba630623461b0e3d67cdb7b7b
@@@ -26,7 -26,7 +26,8 @@@
  #include <asm/arch/clk.h>
  #include <asm/arch/gpio.h>
  #include <asm/arch/hmatrix.h>
 +#include <asm/arch/portmux.h>
+ #include <netdev.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
@@@ -92,11 -92,8 +93,9 @@@ int board_early_init_r(void
  {
        gd->bd->bi_phy_id[0] = 0x01;
        gd->bd->bi_phy_id[1] = 0x03;
 +      return 0;
  }
  
- extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
  #ifdef CONFIG_CMD_NET
  int board_eth_init(bd_t *bi)
  {
index 7be39931e5e20e2462b726c6d40d494535e31d2d,94523b5a3b52f9d37e6fc1e1727e761e41342af0..c36cb5717be4fc303b1edc3e4798f9e5f1c25cc9
@@@ -24,8 -24,9 +24,9 @@@
  #include <asm/io.h>
  #include <asm/sdram.h>
  #include <asm/arch/clk.h>
 -#include <asm/arch/gpio.h>
  #include <asm/arch/hmatrix.h>
 +#include <asm/arch/portmux.h>
+ #include <netdev.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
@@@ -114,11 -115,8 +115,9 @@@ int board_early_init_r(void
  {
        gd->bd->bi_phy_id[0] = 0x10;
        gd->bd->bi_phy_id[1] = 0x11;
 +      return 0;
  }
  
- extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
  #ifdef CONFIG_CMD_NET
  int board_eth_init(bd_t *bi)
  {
Simple merge
index 7fd078125424d1b029d188733f29f1a522bae57c,d3875f449dbd7d522e74d004d5785b900f356dee..8b3e22cd9ece1ee1d3e21706b2ec52a611706c58
   * MA 02111-1307 USA
   */
  
 -#include "../cpu/at32ap/at32ap700x/sm.h"
 -
  #include <common.h>
+ #include <netdev.h>
  
  #include <asm/io.h>
  #include <asm/sdram.h>
Simple merge
Simple merge
index 21545a3c1855cdb546db3172007734418407d674,7817572270c1245095d12b81c62e0f0330d0ac61..d83e93b74f6eb06642ac89790cbd6b40f33510c3
  #define __ASM_AVR32_ARCH_CLK_H__
  
  #include <asm/arch/chip-features.h>
 +#include <asm/arch/portmux.h>
  
  #ifdef CONFIG_PLL
- #define PLL0_RATE     ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
 -#define MAIN_CLK_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) * CONFIG_SYS_PLL0_MUL)
++#define PLL0_RATE     ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV)     \
++                              * CONFIG_SYS_PLL0_MUL)
 +#define MAIN_CLK_RATE PLL0_RATE
  #else
- #define MAIN_CLK_RATE (CFG_OSC0_HZ)
 -#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
++#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
  #endif
  
  static inline unsigned long get_cpu_clk_rate(void)
@@@ -84,101 -82,9 +85,101 @@@ static inline unsigned long get_spi_clk
  #endif
  
  extern void clk_init(void);
 -extern void gclk_init(void) __attribute__((weak));
  
  /* Board code may need the SDRAM base clock as a compile-time constant */
- #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
+ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
  
-               parent_rate = CFG_OSC0_HZ;
 +/* Generic clock control */
 +enum gclk_parent {
 +      GCLK_PARENT_OSC0 = 0,
 +      GCLK_PARENT_OSC1 = 1,
 +      GCLK_PARENT_PLL0 = 2,
 +      GCLK_PARENT_PLL1 = 3,
 +};
 +
 +/* Some generic clocks have specific roles */
 +#define GCLK_DAC_SAMPLE_CLK   6
 +#define GCLK_LCDC_PIXCLK      7
 +
 +extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
 +              unsigned long rate, unsigned long parent_rate);
 +
 +/**
 + * gclk_set_rate - configure and enable a generic clock
 + * @id: Which GCLK[id] to enable
 + * @parent: Parent clock feeding the GCLK
 + * @rate: Target rate of the GCLK in Hz
 + *
 + * Returns the actual GCLK rate in Hz, after rounding to the nearest
 + * supported rate.
 + *
 + * All three parameters are usually constant, hence the inline.
 + */
 +static inline unsigned long gclk_set_rate(unsigned int id,
 +              enum gclk_parent parent, unsigned long rate)
 +{
 +      unsigned long parent_rate;
 +
 +      if (id > 7)
 +              return 0;
 +
 +      switch (parent) {
 +      case GCLK_PARENT_OSC0:
- #ifdef CFG_OSC1_HZ
++              parent_rate = CONFIG_SYS_OSC0_HZ;
 +              break;
-               parent_rate = CFG_OSC1_HZ;
++#ifdef CONFIG_SYS_OSC1_HZ
 +      case GCLK_PARENT_OSC1:
++              parent_rate = CONFIG_SYS_OSC1_HZ;
 +              break;
 +#endif
 +#ifdef PLL0_RATE
 +      case GCLK_PARENT_PLL0:
 +              parent_rate = PLL0_RATE;
 +              break;
 +#endif
 +#ifdef PLL1_RATE
 +      case GCLK_PARENT_PLL1:
 +              parent_rate = PLL1_RATE;
 +              break;
 +#endif
 +      default:
 +              parent_rate = 0;
 +              break;
 +      }
 +
 +      return __gclk_set_rate(id, parent, rate, parent_rate);
 +}
 +
 +/**
 + * gclk_enable_output - enable output on a GCLK pin
 + * @id: Which GCLK[id] pin to enable
 + * @drive_strength: Drive strength of external GCLK pin, if applicable
 + */
 +static inline void gclk_enable_output(unsigned int id,
 +              unsigned long drive_strength)
 +{
 +      switch (id) {
 +      case 0:
 +              portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
 +                              PORTMUX_FUNC_A, drive_strength);
 +              break;
 +      case 1:
 +              portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
 +                              PORTMUX_FUNC_A, drive_strength);
 +              break;
 +      case 2:
 +              portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
 +                              PORTMUX_FUNC_A, drive_strength);
 +              break;
 +      case 3:
 +              portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
 +                              PORTMUX_FUNC_A, drive_strength);
 +              break;
 +      case 4:
 +              portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
 +                              PORTMUX_FUNC_A, drive_strength);
 +              break;
 +      }
 +}
 +
  #endif /* __ASM_AVR32_ARCH_CLK_H__ */
index 323b096ab1635f78f4a0e43cba59299a4c0c1f1e,9e97624765c51ceb29505ec5e82570a7ef9c4e2f..c998952fbf35f1260ef3904344e1e4750be235d5
  
  #define CONFIG_ATMEL_USART            1
  #define CONFIG_MACB                   1
 -#define CONFIG_PIO2                   1
 +#define CONFIG_PORTMUX_PIO            1
- #define CFG_NR_PIOS                   5
- #define CFG_HSDRAMC                   1
+ #define CONFIG_SYS_NR_PIOS                    5
+ #define CONFIG_SYS_HSDRAMC                    1
  #define CONFIG_MMC                    1
  #define CONFIG_ATMEL_MCI              1
  #define CONFIG_ATMEL_SPI              1
index 85cedb2fb299de7d8c323050d736c46959e6f146,2870adef0f651e19b76eef1df3bd9f386cbbaf43..2284277da238641494914465820767b639b8a218
  
  #define CONFIG_ATMEL_USART            1
  #define CONFIG_MACB                   1
 -#define CONFIG_PIO2                   1
 +#define CONFIG_PORTMUX_PIO            1
- #define CFG_NR_PIOS                   5
- #define CFG_HSDRAMC                   1
+ #define CONFIG_SYS_NR_PIOS                    5
+ #define CONFIG_SYS_HSDRAMC                    1
  #define CONFIG_MMC                    1
  #define CONFIG_ATMEL_MCI              1
  
index 9aa0692c0d27084be04ccda5b95b55ca4e0e64a3,1e80dc856e98dd2d3a86888cbcaefc0e5895ef53..2ef255274f4c2748e9f1cf92fe74bd4e33def124
  #undef CONFIG_CMD_XIMG
  
  #define CONFIG_ATMEL_USART            1
 -#define CONFIG_PIO2                   1
 +#define CONFIG_PORTMUX_PIO            1
- #define CFG_HSDRAMC                   1
+ #define CONFIG_SYS_HSDRAMC                    1
  #define CONFIG_MMC                    1
  #define CONFIG_ATMEL_MCI              1
  
index d8ce339c2a56a16b0855824babafbe51c6fcd81b,0e4f4103b212207f215c03ed77afeeaa2ca34a52..195be82095f496f7cf0975f3d113952a43abfe13
  #undef CONFIG_CMD_XIMG
  
  #define CONFIG_ATMEL_USART            1
 -#define CONFIG_PIO2                   1
 +#define CONFIG_PORTMUX_PIO            1
- #define CFG_HSDRAMC                   1
+ #define CONFIG_SYS_HSDRAMC                    1
  #define CONFIG_MMC                    1
  #define CONFIG_ATMEL_MCI              1
  
index d4b2f12aa80f6eae5ab38c3ff207ade62cf46235,c53459664b0f7353374900f4048878f0d6177a20..8cfa31269ba7787b71ac6def3d814b8ffaf006c1
  
  #define CONFIG_ATMEL_USART            1
  #define CONFIG_MACB                   1
 -#define CONFIG_PIO2                   1
 +#define CONFIG_PORTMUX_PIO            1
- #define CFG_NR_PIOS                   5
- #define CFG_HSDRAMC                   1
+ #define CONFIG_SYS_NR_PIOS                    5
+ #define CONFIG_SYS_HSDRAMC                    1
  #define CONFIG_MMC                    1
  #define CONFIG_ATMEL_MCI              1
  
index 3c9420cf91a1ee25946cdc43c2a8f6d5bc8daf67,3cef4196df47cc8eda148e799e9138d6617eba62..21802df1d213490c268039512d8723d5e0112285
  
  #define CONFIG_ATMEL_USART            1
  #define CONFIG_MACB                   1
 -#define CONFIG_PIO2                   1
 +#define CONFIG_PORTMUX_PIO            1
- #define CFG_NR_PIOS                   5
- #define CFG_HSDRAMC                   1
+ #define CONFIG_SYS_NR_PIOS                    5
+ #define CONFIG_SYS_HSDRAMC                    1
  #define CONFIG_MMC                    1
  #define CONFIG_ATMEL_MCI              1
  
index fca4111867c78ff7392404b83f52bcfee92e3414,317a3d7dd78c552ff2d9577f89ddec98d77fcdfd..0c70af574259119c5f3e1e7716e3e16a20f79a08
  
  #define CONFIG_ATMEL_USART            1
  #define CONFIG_MACB                   1
 -#define CONFIG_PIO2                   1
 +#define CONFIG_PORTMUX_PIO            1
- #define CFG_NR_PIOS                   5
- #define CFG_HSDRAMC                   1
+ #define CONFIG_SYS_NR_PIOS                    5
+ #define CONFIG_SYS_HSDRAMC                    1
  #define CONFIG_MMC                    1
  #define CONFIG_ATMEL_MCI              1
  
index 0506b93c75d1ac0c5594a7dbec5d2005e08aeb58,312fdc9e4d1b1ac92f6672620dd4f85bfdd2324d..2eb9ebc29074920b08d590dcb2a57e098899e72c
  
  #define CONFIG_ATMEL_USART            1
  #define CONFIG_MACB                   1
 -#define CONFIG_PIO2                   1
 +#define CONFIG_PORTMUX_PIO            1
- #define CFG_NR_PIOS                   5
- #define CFG_HSDRAMC                   1
+ #define CONFIG_SYS_NR_PIOS                    5
+ #define CONFIG_SYS_HSDRAMC                    1
  #define CONFIG_MMC                    1
  #define CONFIG_ATMEL_MCI              1
  
index 4ed6c966306722b1ba35c3382e09e23de876a26a,2a98bd41f6d44ac488a7912a8bdcd17d81b79ace..959375a48f173354c641cb6be89eec78793acfbf
@@@ -281,10 -273,8 +282,10 @@@ void board_init_r(gd_t *new_gd, ulong d
        bd = gd->bd;
  
        gd->flags |= GD_FLG_RELOC;
-       gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
+       gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
  
 +      board_early_init_r();
 +
        monitor_flash_len = _edata - _text;
  
        /*