]> git.sur5r.net Git - u-boot/commitdiff
ARM: at91: sama5d2: add macro & field definitions
authorWenyou Yang <wenyou.yang@atmel.com>
Fri, 26 Feb 2016 09:20:25 +0000 (17:20 +0800)
committerAndreas Bießmann <andreas@biessmann.org>
Tue, 24 May 2016 06:08:35 +0000 (08:08 +0200)
They will be used on SAMA5D2 PTC board.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
arch/arm/mach-at91/include/mach/sama5_sfr.h
arch/arm/mach-at91/include/mach/sama5d2.h

index b040256ba490ea028129db3258a5ed1699ba8794..b805a2c93495e80e2a20a3a262dbc64d6471b6ba 100644 (file)
@@ -32,6 +32,30 @@ struct atmel_sfr {
 #define ATMEL_SFR_DDRCFG_FDQIEN                0x00010000
 #define ATMEL_SFR_DDRCFG_FDQSIEN       0x00020000
 
+/* Bit field in EBICFG */
+#define AT91_SFR_EBICFG_DRIVE0         (0x3 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_LOW             (0x0 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_MEDIUM          (0x2 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_HIGH            (0x3 << 0)
+#define AT91_SFR_EBICFG_PULL0          (0x3 << 2)
+#define AT91_SFR_EBICFG_PULL0_UP               (0x0 << 2)
+#define AT91_SFR_EBICFG_PULL0_NONE             (0x1 << 2)
+#define AT91_SFR_EBICFG_PULL0_DOWN             (0x3 << 2)
+#define AT91_SFR_EBICFG_SCH0           (0x1 << 4)
+#define AT91_SFR_EBICFG_SCH0_OFF               (0x0 << 4)
+#define AT91_SFR_EBICFG_SCH0_ON                        (0x1 << 4)
+#define AT91_SFR_EBICFG_DRIVE1         (0x3 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_LOW             (0x0 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_MEDIUM          (0x2 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_HIGH            (0x3 << 8)
+#define AT91_SFR_EBICFG_PULL1          (0x3 << 10)
+#define AT91_SFR_EBICFG_PULL1_UP               (0x0 << 10)
+#define AT91_SFR_EBICFG_PULL1_NONE             (0x1 << 10)
+#define AT91_SFR_EBICFG_PULL1_DOWN             (0x3 << 10)
+#define AT91_SFR_EBICFG_SCH1           (0x1 << 12)
+#define AT91_SFR_EBICFG_SCH1_OFF               (0x0 << 12)
+#define AT91_SFR_EBICFG_SCH1_ON                        (0x1 << 12)
+
 /* Bit field in AICREDIR */
 #define ATMEL_SFR_AICREDIR_NSAIC       0x00000001
 
index dd5a2a7523d8a61bed53314b8afe29f9cc6c2976..25c85411e5a1e3c7ce3ee9dc6def14d3b1358f9e 100644 (file)
 /*
  * Address Memory Space
  */
+#define ATMEL_BASE_CS0                 0x10000000
 #define ATMEL_BASE_DDRCS               0x20000000
+#define ATMEL_BASE_CS1                 0x60000000
+#define ATMEL_BASE_CS2                 0x70000000
+#define ATMEL_BASE_CS3                 0x80000000
 #define ATMEL_BASE_QSPI0_AES_MEM       0x90000000
 #define ATMEL_BASE_QSPI1_AES_MEM       0x98000000
 #define ATMEL_BASE_SDMMC0              0xa0000000
  */
 #define ATMEL_BASE_PMECC       (ATMEL_BASE_HSMC + 0x70)
 #define ATMEL_BASE_PMERRLOC    (ATMEL_BASE_HSMC + 0x500)
+#define ATMEL_BASE_SMC         (ATMEL_BASE_HSMC + 0x700)
 
 #define ATMEL_BASE_PIOB                (ATMEL_BASE_PIOA + 0x40)
 #define ATMEL_BASE_PIOC                (ATMEL_BASE_PIOB + 0x40)