the queue empty. */\r
#define mainQUEUE_LENGTH ( 1 )\r
\r
-/* The LED is used to show the demo status. */\r
+/* The LED is used to show the demo status. (not connected on Rev A hardware) */\r
#define mainTOGGLE_LED() HAL_GPIO_TogglePin( GPIOF, GPIO_PIN_10 )\r
\r
/*-----------------------------------------------------------*/\r
******************************************************************************\r
* @file stm32f746xx.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 28-April-2015\r
* @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.\r
*\r
* This file contains:\r
#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)\r
#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)\r
#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)\r
-#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000010)\r
-#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000020)\r
+#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000010)\r
+#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000020)\r
#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)\r
#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)\r
#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)\r
#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)\r
#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)\r
#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)\r
-#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x40000000)\r
-#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x80000000)\r
+#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x40000000)\r
+#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x80000000)\r
\r
/******************* Bits definition for FLASH_OPTCR1 register ***************/\r
#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)\r
/* USB_OTG */\r
/* */\r
/******************************************************************************/\r
-/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/\r
+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/\r
#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */\r
#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */\r
#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */\r
#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */\r
#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */\r
\r
-/******************** Bit definition forUSB_OTG_HCFG register ********************/\r
-\r
+/******************** Bit definition for USB_OTG_HCFG register ********************/\r
#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */\r
#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */\r
\r
-/******************** Bit definition forUSB_OTG_DCFG register ********************/\r
-\r
+/******************** Bit definition for USB_OTG_DCFG register ********************/\r
#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */\r
#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
\r
-/******************** Bit definition forUSB_OTG_PCGCR register ********************/\r
+/******************** Bit definition for USB_OTG_PCGCR register ********************/\r
#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */\r
#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */\r
#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */\r
\r
-/******************** Bit definition forUSB_OTG_GOTGINT register ********************/\r
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/\r
#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */\r
#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */\r
#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */\r
#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */\r
#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */\r
\r
-/******************** Bit definition forUSB_OTG_DCTL register ********************/\r
+/******************** Bit definition for USB_OTG_DCTL register ********************/\r
#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */\r
#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */\r
#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */\r
#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */\r
#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */\r
\r
-/******************** Bit definition forUSB_OTG_HFIR register ********************/\r
+/******************** Bit definition for USB_OTG_HFIR register ********************/\r
#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */\r
\r
-/******************** Bit definition forUSB_OTG_HFNUM register ********************/\r
+/******************** Bit definition for USB_OTG_HFNUM register ********************/\r
#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */\r
#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */\r
\r
-/******************** Bit definition forUSB_OTG_DSTS register ********************/\r
+/******************** Bit definition for USB_OTG_DSTS register ********************/\r
#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */\r
\r
#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */\r
#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */\r
#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */\r
\r
-/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/\r
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/\r
#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */\r
#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */\r
#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */\r
#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */\r
\r
-/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/\r
-\r
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/\r
#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */\r
#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */\r
#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */\r
\r
-/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/\r
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/\r
#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */\r
#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */\r
#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */\r
#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */\r
#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/\r
#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */\r
#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */\r
#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/\r
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/\r
#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */\r
#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */\r
#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
\r
-/******************** Bit definition forUSB_OTG_HAINT register ********************/\r
+/******************** Bit definition for USB_OTG_HAINT register ********************/\r
#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/\r
#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */\r
#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */\r
#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_GINTSTS register ********************/\r
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/\r
#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */\r
#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */\r
#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */\r
#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */\r
#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */\r
\r
-/******************** Bit definition forUSB_OTG_GINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/\r
#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */\r
#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */\r
#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */\r
#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */\r
#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_DAINT register ********************/\r
+/******************** Bit definition for USB_OTG_DAINT register ********************/\r
#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */\r
#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */\r
\r
-/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/\r
#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */\r
\r
/******************** Bit definition for USB_OTG_GRXSTSP register ********************/\r
#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */\r
#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */\r
\r
-/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/\r
#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */\r
#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */\r
\r
#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
\r
-/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/\r
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/\r
#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */\r
\r
-/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/\r
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/\r
#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */\r
\r
/******************** Bit definition for OTG register ********************/\r
#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */\r
#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */\r
\r
-/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/\r
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/\r
#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */\r
\r
-/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/\r
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/\r
#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */\r
\r
#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */\r
#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
\r
-/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/\r
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/\r
#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */\r
#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */\r
\r
#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */\r
#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/\r
#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */\r
\r
-/******************** Bit definition forUSB_OTG_DEACHINT register ********************/\r
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/\r
#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */\r
#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */\r
\r
-/******************** Bit definition forUSB_OTG_GCCFG register ********************/\r
-#define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001) /*!< Data contact detection (DCD) status */\r
-#define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002) /*!< Primary detection (PD) status */\r
-#define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004) /*!< Secondary detection (SD) status */\r
-#define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008) /*!< DM pull-up detection status */\r
+/******************** Bit definition for USB_OTG_GCCFG register ********************/\r
#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */\r
-#define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000) /*!< Battery charging detector (BCD) enable */\r
-#define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000) /*!< Data contact detection (DCD) mode enable*/\r
-#define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000) /*!< Primary detection (PD) mode enable*/\r
-#define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000) /*!< Secondary detection (SD) mode enable */\r
#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */\r
\r
-/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/\r
+/******************** Bit definition for USB_OTG_GPWRDN) register ********************/\r
#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */\r
#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */\r
\r
-/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/\r
#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */\r
#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */\r
\r
-/******************** Bit definition forUSB_OTG_CID register ********************/\r
+/******************** Bit definition for USB_OTG_CID register ********************/\r
#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */\r
\r
/******************** Bit definition for USB_OTG_GLPMCFG register ********************/\r
#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */\r
#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/\r
#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */\r
#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_HPRT register ********************/\r
+/******************** Bit definition for USB_OTG_HPRT register ********************/\r
#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */\r
#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */\r
#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */\r
#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/\r
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/\r
#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */\r
#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */\r
#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/\r
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/\r
#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */\r
#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/\r
#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */\r
#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */\r
#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */\r
#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */\r
#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */\r
\r
-/******************** Bit definition forUSB_OTG_HCCHAR register ********************/\r
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/\r
#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */\r
\r
#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */\r
#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */\r
#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */\r
\r
-/******************** Bit definition forUSB_OTG_HCSPLT register ********************/\r
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/\r
\r
#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */\r
#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */\r
#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */\r
\r
-/******************** Bit definition forUSB_OTG_HCINT register ********************/\r
+/******************** Bit definition for USB_OTG_HCINT register ********************/\r
#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */\r
#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */\r
#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */\r
#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */\r
#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPINT register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/\r
#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */\r
#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */\r
#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */\r
#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */\r
#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */\r
\r
-/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/\r
#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */\r
#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */\r
#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */\r
#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */\r
-/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/\r
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/\r
#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */\r
#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */\r
#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/\r
#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */\r
\r
-/******************** Bit definition forUSB_OTG_HCDMA register ********************/\r
+/******************** Bit definition for USB_OTG_HCDMA register ********************/\r
#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */\r
\r
-/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/\r
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/\r
#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/\r
#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */\r
#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/\r
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/\r
#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */\r
#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */\r
#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */\r
#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */\r
#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPINT register ********************/\r
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/\r
#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */\r
#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */\r
#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */\r
#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */\r
#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/\r
-\r
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/\r
#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
\r
******************************************************************************\r
* @file stm32f756xx.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 28-April-2015\r
* @brief CMSIS STM32F756xx Device Peripheral Access Layer Header File.\r
*\r
* This file contains:\r
#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)\r
#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)\r
#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)\r
-#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000010)\r
-#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000020)\r
+#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000010)\r
+#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000020)\r
#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)\r
#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)\r
#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)\r
#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)\r
#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)\r
#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)\r
-#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x40000000)\r
-#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x80000000)\r
+#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x40000000)\r
+#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x80000000)\r
\r
/******************* Bits definition for FLASH_OPTCR1 register ***************/\r
#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)\r
#define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)\r
\r
-\r
-\r
/******************************************************************************/\r
/* */\r
/* Flexible Memory Controller */\r
/* USB_OTG */\r
/* */\r
/******************************************************************************/\r
-/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/\r
+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/\r
#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */\r
#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */\r
#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */\r
#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */\r
#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */\r
\r
-/******************** Bit definition forUSB_OTG_HCFG register ********************/\r
-\r
+/******************** Bit definition for USB_OTG_HCFG register ********************/\r
#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */\r
#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */\r
\r
-/******************** Bit definition forUSB_OTG_DCFG register ********************/\r
-\r
+/******************** Bit definition for USB_OTG_DCFG register ********************/\r
#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */\r
#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
\r
-/******************** Bit definition forUSB_OTG_PCGCR register ********************/\r
+/******************** Bit definition for USB_OTG_PCGCR register ********************/\r
#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */\r
#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */\r
#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */\r
\r
-/******************** Bit definition forUSB_OTG_GOTGINT register ********************/\r
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/\r
#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */\r
#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */\r
#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */\r
#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */\r
#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */\r
\r
-/******************** Bit definition forUSB_OTG_DCTL register ********************/\r
+/******************** Bit definition for USB_OTG_DCTL register ********************/\r
#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */\r
#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */\r
#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */\r
#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */\r
#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */\r
\r
-/******************** Bit definition forUSB_OTG_HFIR register ********************/\r
+/******************** Bit definition for USB_OTG_HFIR register ********************/\r
#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */\r
\r
-/******************** Bit definition forUSB_OTG_HFNUM register ********************/\r
+/******************** Bit definition for USB_OTG_HFNUM register ********************/\r
#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */\r
#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */\r
\r
-/******************** Bit definition forUSB_OTG_DSTS register ********************/\r
+/******************** Bit definition for USB_OTG_DSTS register ********************/\r
#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */\r
\r
#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */\r
#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */\r
#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */\r
\r
-/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/\r
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/\r
#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */\r
#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */\r
#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */\r
#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */\r
\r
-/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/\r
-\r
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/\r
#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */\r
#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */\r
#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */\r
\r
-/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/\r
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/\r
#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */\r
#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */\r
#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */\r
#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */\r
#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/\r
#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */\r
#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */\r
#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/\r
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/\r
#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */\r
#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */\r
#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
\r
-/******************** Bit definition forUSB_OTG_HAINT register ********************/\r
+/******************** Bit definition for USB_OTG_HAINT register ********************/\r
#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/\r
#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */\r
#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */\r
#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_GINTSTS register ********************/\r
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/\r
#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */\r
#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */\r
#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */\r
#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */\r
#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */\r
\r
-/******************** Bit definition forUSB_OTG_GINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/\r
#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */\r
#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */\r
#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */\r
#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */\r
#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_DAINT register ********************/\r
+/******************** Bit definition for USB_OTG_DAINT register ********************/\r
#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */\r
#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */\r
\r
-/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/\r
#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */\r
\r
/******************** Bit definition for USB_OTG_GRXSTSP register ********************/\r
#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */\r
#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */\r
\r
-/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/\r
#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */\r
#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */\r
\r
#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
\r
-/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/\r
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/\r
#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */\r
\r
-/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/\r
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/\r
#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */\r
\r
/******************** Bit definition for OTG register ********************/\r
#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */\r
#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */\r
\r
-/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/\r
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/\r
#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */\r
\r
-/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/\r
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/\r
#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */\r
\r
#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */\r
#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
\r
-/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/\r
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/\r
#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */\r
#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */\r
\r
#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */\r
#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/\r
#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */\r
\r
-/******************** Bit definition forUSB_OTG_DEACHINT register ********************/\r
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/\r
#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */\r
#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */\r
\r
-/******************** Bit definition forUSB_OTG_GCCFG register ********************/\r
-#define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001) /*!< Data contact detection (DCD) status */\r
-#define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002) /*!< Primary detection (PD) status */\r
-#define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004) /*!< Secondary detection (SD) status */\r
-#define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008) /*!< DM pull-up detection status */\r
+/******************** Bit definition for USB_OTG_GCCFG register ********************/\r
#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */\r
-#define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000) /*!< Battery charging detector (BCD) enable */\r
-#define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000) /*!< Data contact detection (DCD) mode enable*/\r
-#define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000) /*!< Primary detection (PD) mode enable*/\r
-#define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000) /*!< Secondary detection (SD) mode enable */\r
#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */\r
\r
-/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/\r
+/******************** Bit definition for USB_OTG_GPWRDN) register ********************/\r
#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */\r
#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */\r
\r
-/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/\r
#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */\r
#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */\r
\r
-/******************** Bit definition forUSB_OTG_CID register ********************/\r
+/******************** Bit definition for USB_OTG_CID register ********************/\r
#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */\r
\r
/******************** Bit definition for USB_OTG_GLPMCFG register ********************/\r
#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */\r
#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/\r
#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */\r
#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_HPRT register ********************/\r
+/******************** Bit definition for USB_OTG_HPRT register ********************/\r
#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */\r
#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */\r
#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */\r
#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/\r
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/\r
#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */\r
#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */\r
#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */\r
\r
-/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/\r
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/\r
#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */\r
#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/\r
#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */\r
#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */\r
#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */\r
#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */\r
#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */\r
\r
-/******************** Bit definition forUSB_OTG_HCCHAR register ********************/\r
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/\r
#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */\r
\r
#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */\r
#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */\r
#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */\r
\r
-/******************** Bit definition forUSB_OTG_HCSPLT register ********************/\r
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/\r
\r
#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */\r
#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */\r
#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */\r
\r
-/******************** Bit definition forUSB_OTG_HCINT register ********************/\r
+/******************** Bit definition for USB_OTG_HCINT register ********************/\r
#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */\r
#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */\r
#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */\r
#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */\r
#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPINT register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/\r
#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */\r
#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */\r
#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */\r
#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */\r
#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */\r
\r
-/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/\r
+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/\r
#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */\r
#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */\r
#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */\r
#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */\r
-/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/\r
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/\r
#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */\r
#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */\r
#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/\r
#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */\r
\r
-/******************** Bit definition forUSB_OTG_HCDMA register ********************/\r
+/******************** Bit definition for USB_OTG_HCDMA register ********************/\r
#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */\r
\r
-/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/\r
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/\r
#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */\r
\r
-/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/\r
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/\r
#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */\r
#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/\r
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/\r
#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */\r
#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */\r
#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */\r
#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */\r
#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPINT register ********************/\r
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/\r
#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */\r
#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */\r
#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */\r
#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */\r
#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */\r
\r
-/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/\r
-\r
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/\r
#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
\r
******************************************************************************\r
* @file stm32f7xx.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 28-April-2015\r
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File. \r
* \r
* The file is the unique include file that the application programmer\r
/* Uncomment the line below according to the target STM32 device used in your\r
application \r
*/\r
-#if !defined (STM32F756xx) && !defined (STM32F746xx)\r
- /* #define STM32F756xx */ /*!< STM32F756VI, STM32F756VG, STM32F756ZG, STM32F756ZI, STM32F756IG, STM32F756II,\r
- STM32F756BG, STM32F756BI, STM32F756NI, STM32F756NG Devices */\r
- /* #define STM32F746xx */ /*!< STM32F746VI, STM32F746VG, STM32F746ZG, STM32F746ZI, STM32F746IG, STM32F746II,\r
- STM32F746BG, STM32F746BI, STM32F746NI, STM32F746NG Devices */\r
+#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx)\r
+ /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,\r
+ STM32F756NG Devices */\r
+ /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,\r
+ STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */\r
+ /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */\r
#endif\r
\r
/* Tip: To avoid modifying this file each time you need to switch between these\r
#endif /* USE_HAL_DRIVER */\r
\r
/**\r
- * @brief CMSIS Device version number V1.0.0RC1\r
+ * @brief CMSIS Device version number V1.0.0\r
*/\r
#define __STM32F7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
#define __STM32F7xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */\r
#define __STM32F7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
-#define __STM32F7xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */ \r
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
#define __STM32F7xx_CMSIS_DEVICE_VERSION ((__STM32F7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\\r
|(__STM32F7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\\r
|(__STM32F7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\\r
#include "stm32f756xx.h"\r
#elif defined(STM32F746xx)\r
#include "stm32f746xx.h"\r
+#elif defined(STM32F745xx)\r
+ #include "stm32f745xx.h"\r
#else\r
#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"\r
#endif\r
/**\r
******************************************************************************\r
- * @file system_stm32f4xx.h\r
+ * @file system_stm32f7xx.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 28-April-2015\r
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. \r
****************************************************************************** \r
* @attention\r
/* ----------------------------------------------------------------------\r
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
*\r
-* $Date: 31. July 2014\r
-* $Revision: V1.4.4\r
+* $Date: 19. March 2015\r
+* $Revision: V.1.4.5\r
*\r
* Project: CMSIS DSP Library\r
* Title: arm_common_tables.h\r
/* ----------------------------------------------------------------------\r
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
*\r
-* $Date: 31. July 2014\r
-* $Revision: V1.4.4\r
+* $Date: 19. March 2015\r
+* $Revision: V.1.4.5\r
*\r
* Project: CMSIS DSP Library\r
* Title: arm_const_structs.h\r
/* ----------------------------------------------------------------------\r
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r
*\r
-* $Date: 12. March 2014\r
-* $Revision: V1.4.4\r
+* $Date: 19. March 2015\r
+* $Revision: V.1.4.5\r
*\r
* Project: CMSIS DSP Library\r
* Title: arm_math.h\r
* ------------\r
*\r
* The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)\r
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)\r
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)\r
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)\r
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)\r
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)\r
* - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r
* - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r
* - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r
* - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r
* - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r
* - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r
- * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)\r
- * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)\r
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)\r
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)\r
*\r
* The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
* Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
- * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
- * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or\r
+ * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or\r
* ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r
*\r
* Examples\r
* Toolchain Support\r
* ------------\r
*\r
- * The library has been developed and tested with MDK-ARM version 4.60.\r
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0\r
* The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
*\r
* Building the Library\r
* ------------\r
*\r
* The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
- * - arm_cortexM_math.uvproj\r
+ * - arm_cortexM_math.uvprojx\r
*\r
*\r
- * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r
*\r
* Pre-processor Macros\r
* ------------\r
* - ARM_MATH_CMx:\r
*\r
* Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
- * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.\r
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\r
+ * ARM_MATH_CM7 for building the library on cortex-M7.\r
*\r
* - __FPU_PRESENT:\r
*\r
* Copyright Notice\r
* ------------\r
*\r
- * Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r
*/\r
\r
\r
* @brief definition to read/write two 16 bit values.\r
*/\r
#if defined __CC_ARM\r
-#define __SIMD32_TYPE int32_t __packed\r
-#define CMSIS_UNUSED __attribute__((unused))\r
+ #define __SIMD32_TYPE int32_t __packed\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
#elif defined __ICCARM__\r
-#define CMSIS_UNUSED\r
-#define __SIMD32_TYPE int32_t __packed\r
+ #define __SIMD32_TYPE int32_t __packed\r
+ #define CMSIS_UNUSED\r
#elif defined __GNUC__\r
-#define __SIMD32_TYPE int32_t\r
-#define CMSIS_UNUSED __attribute__((unused))\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
#elif defined __CSMC__ /* Cosmic */\r
-#define CMSIS_UNUSED\r
-#define __SIMD32_TYPE int32_t\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED\r
+#elif defined __TASKING__\r
+ #define __SIMD32_TYPE __unaligned int32_t\r
+ #define CMSIS_UNUSED\r
#else\r
-#error Unknown compiler\r
+ #error Unknown compiler\r
#endif\r
\r
#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
}\r
\r
\r
-#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )\r
-#define __CLZ __clz\r
-#endif\r
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )\r
+//#define __CLZ __clz\r
+//#endif\r
\r
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )\r
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0\r
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )\r
\r
static __INLINE uint32_t __CLZ(\r
q31_t data);\r
float32_t in,\r
float32_t * pOut)\r
{\r
- if(in > 0)\r
+ if(in >= 0.0f)\r
{\r
\r
// #if __FPU_USED\r
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
\r
+#elif defined(__TASKING__) // TASKING\r
+\r
+#define LOW_OPTIMIZATION_ENTER\r
+#define LOW_OPTIMIZATION_EXIT\r
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
#endif\r
\r
\r
/**************************************************************************//**\r
* @file core_cm0.h\r
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
- * @version V4.00\r
- * @date 22. August 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
{\r
struct\r
{\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} APSR_Type;\r
\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31 /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29 /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28 /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
\r
/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
*/\r
uint32_t w; /*!< Type used for word access */\r
} IPSR_Type;\r
\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
*/\r
struct\r
{\r
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} xPSR_Type;\r
\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Control Registers (CONTROL).\r
*/\r
{\r
struct\r
{\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
} b; /*!< Structure used for bit access */\r
uint32_t w; /*!< Type used for word access */\r
} CONTROL_Type;\r
\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
/*@} end of group CMSIS_CORE */\r
\r
\r
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
\r
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
/* SCB Application Interrupt and Reset Control Register Definitions */\r
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
\r
/*@} end of group CMSIS_SysTick */\r
\r
\r
/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
\r
\r
/** \brief Enable External Interrupt\r
*/\r
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+ NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+ NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+ return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+ NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+ NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
- if(IRQn < 0) {\r
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ if((int32_t)(IRQn) < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
else {\r
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
}\r
\r
\r
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
- if(IRQn < 0) {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ if((int32_t)(IRQn) < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
else {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
}\r
\r
\r
{\r
__DSB(); /* Ensure all outstanding memory accesses included\r
buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
SCB_AIRCR_SYSRESETREQ_Msk);\r
__DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
+ while(1) { __NOP(); } /* wait until reset */\r
}\r
\r
/*@} end of CMSIS_Core_NVICFunctions */\r
*/\r
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */\r
\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
}\r
\r
#endif\r
/**************************************************************************//**\r
* @file core_cm0plus.h\r
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
- * @version V4.00\r
- * @date 22. August 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
{\r
struct\r
{\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} APSR_Type;\r
\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31 /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29 /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28 /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
\r
/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
*/\r
uint32_t w; /*!< Type used for word access */\r
} IPSR_Type;\r
\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
*/\r
struct\r
{\r
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} xPSR_Type;\r
\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Control Registers (CONTROL).\r
*/\r
{\r
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
} b; /*!< Structure used for bit access */\r
uint32_t w; /*!< Type used for word access */\r
} CONTROL_Type;\r
\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
/*@} end of group CMSIS_CORE */\r
\r
\r
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
\r
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
#if (__VTOR_PRESENT == 1)\r
/* SCB Interrupt Control State Register Definitions */\r
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
\r
/*@} end of group CMSIS_SysTick */\r
\r
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
\r
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
\r
/* MPU Control Register */\r
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
\r
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
\r
/* MPU Region Number Register */\r
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
\r
/* MPU Region Base Address Register */\r
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */\r
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
\r
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
\r
/* MPU Region Attribute and Size Register */\r
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
\r
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
\r
/*@} end of group CMSIS_MPU */\r
#endif\r
\r
/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
\r
\r
/** \brief Enable External Interrupt\r
*/\r
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+ NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+ NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+ return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+ NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+ NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
- if(IRQn < 0) {\r
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ if((int32_t)(IRQn) < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
else {\r
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
}\r
\r
\r
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
- if(IRQn < 0) {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ if((int32_t)(IRQn) < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
else {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
}\r
\r
\r
{\r
__DSB(); /* Ensure all outstanding memory accesses included\r
buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
SCB_AIRCR_SYSRESETREQ_Msk);\r
__DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
+ while(1) { __NOP(); } /* wait until reset */\r
}\r
\r
/*@} end of CMSIS_Core_NVICFunctions */\r
*/\r
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */\r
\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
}\r
\r
#endif\r
/**************************************************************************//**\r
* @file core_cm3.h\r
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V4.00\r
- * @date 22. August 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
{\r
struct\r
{\r
-#if (__CORTEX_M != 0x04)\r
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} APSR_Type;\r
\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31 /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29 /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28 /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
\r
/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
*/\r
uint32_t w; /*!< Type used for word access */\r
} IPSR_Type;\r
\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
*/\r
struct\r
{\r
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
uint32_t w; /*!< Type used for word access */\r
} xPSR_Type;\r
\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Control Registers (CONTROL).\r
*/\r
{\r
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
} b; /*!< Structure used for bit access */\r
uint32_t w; /*!< Type used for word access */\r
} CONTROL_Type;\r
\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
/*@} end of group CMSIS_CORE */\r
\r
\r
\r
/* Software Triggered Interrupt Register Definitions */\r
#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
\r
/*@} end of group CMSIS_NVIC */\r
\r
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
\r
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
/* SCB Vector Table Offset Register Definitions */\r
#if (__CM3_REV < 0x0201) /* core r2p1 */\r
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
\r
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
\r
/* SCB System Control Register Definitions */\r
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
\r
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
\r
/* SCB System Handler Control and State Register Definitions */\r
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
\r
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
\r
/* SCB Configurable Fault Status Registers Definitions */\r
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
\r
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
\r
/* SCB Hard Fault Status Registers Definitions */\r
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
\r
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
\r
/*@} end of group CMSIS_SCB */\r
\r
\r
/* Interrupt Controller Type Register Definitions */\r
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
\r
/* Auxiliary Control Register Definitions */\r
\r
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
\r
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
\r
/*@} end of group CMSIS_SCnotSCB */\r
\r
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
\r
/*@} end of group CMSIS_SysTick */\r
\r
\r
/* ITM Trace Privilege Register Definitions */\r
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
\r
/* ITM Trace Control Register Definitions */\r
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
\r
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
\r
/* ITM Integration Write Register Definitions */\r
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
\r
/* ITM Integration Read Register Definitions */\r
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
\r
/* ITM Integration Mode Control Register Definitions */\r
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
\r
/* ITM Lock Status Register Definitions */\r
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
\r
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
\r
/*@}*/ /* end of group CMSIS_ITM */\r
\r
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
\r
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
\r
/* DWT CPI Count Register Definitions */\r
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
\r
/* DWT Exception Overhead Count Register Definitions */\r
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
\r
/* DWT Sleep Count Register Definitions */\r
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
\r
/* DWT LSU Count Register Definitions */\r
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
\r
/* DWT Folded-instruction Count Register Definitions */\r
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
\r
/* DWT Comparator Mask Register Definitions */\r
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
\r
/* DWT Comparator Function Register Definitions */\r
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
\r
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
\r
/*@}*/ /* end of group CMSIS_DWT */\r
\r
\r
/* TPI Asynchronous Clock Prescaler Register Definitions */\r
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
\r
/* TPI Selected Pin Protocol Register Definitions */\r
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
\r
/* TPI Formatter and Flush Status Register Definitions */\r
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
\r
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
\r
/* TPI Formatter and Flush Control Register Definitions */\r
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
\r
/* TPI TRIGGER Register Definitions */\r
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
\r
/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
\r
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
\r
/* TPI ITATBCTR2 Register Definitions */\r
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
\r
/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
\r
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
\r
/* TPI ITATBCTR0 Register Definitions */\r
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
\r
/* TPI Integration Mode Control Register Definitions */\r
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
\r
/* TPI DEVID Register Definitions */\r
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
\r
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
\r
/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
/*@}*/ /* end of group CMSIS_TPI */\r
\r
\r
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
\r
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
\r
/* MPU Control Register */\r
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
\r
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
\r
/* MPU Region Number Register */\r
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
\r
/* MPU Region Base Address Register */\r
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
\r
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
\r
/* MPU Region Attribute and Size Register */\r
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
\r
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
\r
/*@} end of group CMSIS_MPU */\r
#endif\r
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
\r
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
\r
/* Debug Core Register Selector Register */\r
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
\r
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
\r
/* Debug Exception and Monitor Control Register */\r
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
\r
/*@} end of group CMSIS_CoreDebug */\r
\r
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
{\r
uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
\r
reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */\r
SCB->AIRCR = reg_value;\r
}\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ if((int32_t)IRQn < 0) {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
}\r
\r
\r
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ if((int32_t)IRQn < 0) {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
);\r
}\r
\r
*/\r
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SystemReset(void)\r
{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1) { __NOP(); } /* wait until reset */\r
}\r
\r
/*@} end of CMSIS_Core_NVICFunctions */\r
*/\r
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */\r
\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
}\r
\r
#endif\r
*/\r
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
{\r
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
{\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }\r
+ ITM->PORT[0].u8 = (uint8_t)ch;\r
}\r
return (ch);\r
}\r
/**************************************************************************//**\r
* @file core_cm4.h\r
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
- * @version V4.00\r
- * @date 22. August 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
{\r
struct\r
{\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} APSR_Type;\r
\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31 /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29 /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28 /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16 /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
\r
/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
*/\r
uint32_t w; /*!< Type used for word access */\r
} IPSR_Type;\r
\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
*/\r
struct\r
{\r
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
uint32_t w; /*!< Type used for word access */\r
} xPSR_Type;\r
\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Control Registers (CONTROL).\r
*/\r
uint32_t w; /*!< Type used for word access */\r
} CONTROL_Type;\r
\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
/*@} end of group CMSIS_CORE */\r
\r
\r
\r
/* Software Triggered Interrupt Register Definitions */\r
#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
\r
/*@} end of group CMSIS_NVIC */\r
\r
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
\r
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
/* SCB Vector Table Offset Register Definitions */\r
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
\r
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
\r
/* SCB System Control Register Definitions */\r
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
\r
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
\r
/* SCB System Handler Control and State Register Definitions */\r
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
\r
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
\r
/* SCB Configurable Fault Status Registers Definitions */\r
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
\r
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
\r
/* SCB Hard Fault Status Registers Definitions */\r
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
\r
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
\r
/*@} end of group CMSIS_SCB */\r
\r
\r
/* Interrupt Controller Type Register Definitions */\r
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
\r
/* Auxiliary Control Register Definitions */\r
#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */\r
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
\r
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
\r
/*@} end of group CMSIS_SCnotSCB */\r
\r
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
\r
/*@} end of group CMSIS_SysTick */\r
\r
\r
/* ITM Trace Privilege Register Definitions */\r
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
\r
/* ITM Trace Control Register Definitions */\r
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
\r
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
\r
/* ITM Integration Write Register Definitions */\r
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
\r
/* ITM Integration Read Register Definitions */\r
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
\r
/* ITM Integration Mode Control Register Definitions */\r
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
\r
/* ITM Lock Status Register Definitions */\r
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
\r
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
\r
/*@}*/ /* end of group CMSIS_ITM */\r
\r
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
\r
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
\r
/* DWT CPI Count Register Definitions */\r
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
\r
/* DWT Exception Overhead Count Register Definitions */\r
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
\r
/* DWT Sleep Count Register Definitions */\r
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
\r
/* DWT LSU Count Register Definitions */\r
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
\r
/* DWT Folded-instruction Count Register Definitions */\r
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
\r
/* DWT Comparator Mask Register Definitions */\r
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
\r
/* DWT Comparator Function Register Definitions */\r
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
\r
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
\r
/*@}*/ /* end of group CMSIS_DWT */\r
\r
\r
/* TPI Asynchronous Clock Prescaler Register Definitions */\r
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
\r
/* TPI Selected Pin Protocol Register Definitions */\r
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
\r
/* TPI Formatter and Flush Status Register Definitions */\r
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
\r
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
\r
/* TPI Formatter and Flush Control Register Definitions */\r
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
\r
/* TPI TRIGGER Register Definitions */\r
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
\r
/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
\r
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
\r
/* TPI ITATBCTR2 Register Definitions */\r
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
\r
/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
\r
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
\r
/* TPI ITATBCTR0 Register Definitions */\r
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
\r
/* TPI Integration Mode Control Register Definitions */\r
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
\r
/* TPI DEVID Register Definitions */\r
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
\r
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
\r
/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
/*@}*/ /* end of group CMSIS_TPI */\r
\r
\r
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
\r
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
\r
/* MPU Control Register */\r
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
\r
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
\r
/* MPU Region Number Register */\r
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
\r
/* MPU Region Base Address Register */\r
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
\r
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
\r
/* MPU Region Attribute and Size Register */\r
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
\r
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
\r
/*@} end of group CMSIS_MPU */\r
#endif\r
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
\r
#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
\r
/* Floating-Point Context Address Register */\r
#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
\r
#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
\r
/* Media and FP Feature Register 1 */\r
#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
\r
#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
\r
/*@} end of group CMSIS_FPU */\r
#endif\r
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
\r
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
\r
/* Debug Core Register Selector Register */\r
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
\r
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
\r
/* Debug Exception and Monitor Control Register */\r
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
\r
/*@} end of group CMSIS_CoreDebug */\r
\r
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
{\r
uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
\r
reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */\r
SCB->AIRCR = reg_value;\r
}\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
{\r
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ if((int32_t)IRQn < 0) {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
}\r
\r
\r
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ if((int32_t)IRQn < 0) {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
);\r
}\r
\r
*/\r
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SystemReset(void)\r
{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1) { __NOP(); } /* wait until reset */\r
}\r
\r
/*@} end of CMSIS_Core_NVICFunctions */\r
*/\r
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */\r
\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
}\r
\r
#endif\r
*/\r
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
{\r
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
{\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }\r
+ ITM->PORT[0].u8 = (uint8_t)ch;\r
}\r
return (ch);\r
}\r
/**************************************************************************//**\r
* @file core_cm7.h\r
* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
- * @version V4.00\r
- * @date 01. September 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
{\r
struct\r
{\r
-#if (__CORTEX_M != 0x07)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} APSR_Type;\r
\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31 /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29 /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28 /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16 /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
\r
/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
*/\r
uint32_t w; /*!< Type used for word access */\r
} IPSR_Type;\r
\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
*/\r
struct\r
{\r
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x07)\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
uint32_t w; /*!< Type used for word access */\r
} xPSR_Type;\r
\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Control Registers (CONTROL).\r
*/\r
uint32_t w; /*!< Type used for word access */\r
} CONTROL_Type;\r
\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
/*@} end of group CMSIS_CORE */\r
\r
\r
\r
/* Software Triggered Interrupt Register Definitions */\r
#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
\r
/*@} end of group CMSIS_NVIC */\r
\r
__O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
uint32_t RESERVED6[1];\r
__O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
- __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
__O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
__O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
__O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
\r
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
/* SCB Vector Table Offset Register Definitions */\r
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
\r
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
\r
/* SCB System Control Register Definitions */\r
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
\r
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
\r
/* SCB System Handler Control and State Register Definitions */\r
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
\r
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
\r
/* SCB Configurable Fault Status Registers Definitions */\r
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
\r
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
\r
/* SCB Hard Fault Status Registers Definitions */\r
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
\r
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
\r
/* Cache Level ID register */\r
#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */\r
#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
\r
#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */\r
-#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
\r
/* Cache Size ID Register */\r
#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */\r
#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
\r
#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */\r
-#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
\r
/* Cache Size Selection Register */\r
-#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */\r
-#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+#define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
\r
#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */\r
-#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
\r
/* SCB Software Triggered Interrupt Register */\r
#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */\r
-#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
\r
/* Instruction Tightly-Coupled Memory Control Register*/\r
#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */\r
#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
\r
#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */\r
-#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
\r
#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */\r
-#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
\r
#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */\r
-#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
\r
/* Data Tightly-Coupled Memory Control Registers */\r
#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */\r
#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
\r
#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */\r
-#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
\r
/* AHBP Control Register */\r
#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */\r
#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
\r
#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */\r
-#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
\r
/* L1 Cache Control Register */\r
#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */\r
#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
\r
#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */\r
-#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
\r
/* AHBS control register */\r
#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */\r
#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
\r
#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/\r
-#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
\r
/* Auxiliary Bus Fault Status Register */\r
#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/\r
#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
\r
#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/\r
-#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
\r
/*@} end of group CMSIS_SCB */\r
\r
\r
/* Interrupt Controller Type Register Definitions */\r
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
\r
/* Auxiliary Control Register Definitions */\r
#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */\r
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
\r
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
\r
/*@} end of group CMSIS_SCnotSCB */\r
\r
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
\r
/*@} end of group CMSIS_SysTick */\r
\r
\r
/* ITM Trace Privilege Register Definitions */\r
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
\r
/* ITM Trace Control Register Definitions */\r
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
\r
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
\r
/* ITM Integration Write Register Definitions */\r
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
\r
/* ITM Integration Read Register Definitions */\r
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
\r
/* ITM Integration Mode Control Register Definitions */\r
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
\r
/* ITM Lock Status Register Definitions */\r
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
\r
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
\r
/*@}*/ /* end of group CMSIS_ITM */\r
\r
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
\r
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
\r
/* DWT CPI Count Register Definitions */\r
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
\r
/* DWT Exception Overhead Count Register Definitions */\r
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
\r
/* DWT Sleep Count Register Definitions */\r
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
\r
/* DWT LSU Count Register Definitions */\r
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
\r
/* DWT Folded-instruction Count Register Definitions */\r
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
\r
/* DWT Comparator Mask Register Definitions */\r
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
\r
/* DWT Comparator Function Register Definitions */\r
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
\r
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
\r
/*@}*/ /* end of group CMSIS_DWT */\r
\r
\r
/* TPI Asynchronous Clock Prescaler Register Definitions */\r
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
\r
/* TPI Selected Pin Protocol Register Definitions */\r
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
\r
/* TPI Formatter and Flush Status Register Definitions */\r
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
\r
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
\r
/* TPI Formatter and Flush Control Register Definitions */\r
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
\r
/* TPI TRIGGER Register Definitions */\r
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
\r
/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
\r
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
\r
/* TPI ITATBCTR2 Register Definitions */\r
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
\r
/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
\r
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
\r
/* TPI ITATBCTR0 Register Definitions */\r
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
\r
/* TPI Integration Mode Control Register Definitions */\r
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
\r
/* TPI DEVID Register Definitions */\r
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
\r
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
\r
/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
/*@}*/ /* end of group CMSIS_TPI */\r
\r
\r
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
\r
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
\r
/* MPU Control Register */\r
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
\r
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
\r
/* MPU Region Number Register */\r
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
\r
/* MPU Region Base Address Register */\r
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
\r
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
\r
/* MPU Region Attribute and Size Register */\r
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
\r
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
\r
/*@} end of group CMSIS_MPU */\r
#endif\r
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
\r
#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
\r
/* Floating-Point Context Address Register */\r
#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
\r
#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
\r
/* Media and FP Feature Register 1 */\r
#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
\r
#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
\r
/* Media and FP Feature Register 2 */\r
\r
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
\r
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
\r
/* Debug Core Register Selector Register */\r
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
\r
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
\r
/* Debug Exception and Monitor Control Register */\r
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
\r
/*@} end of group CMSIS_CoreDebug */\r
\r
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
{\r
uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
\r
reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */\r
SCB->AIRCR = reg_value;\r
}\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
{\r
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
- if(IRQn < 0) {\r
- SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ if((int32_t)IRQn < 0) {\r
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
}\r
\r
\r
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ if((int32_t)IRQn < 0) {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
);\r
}\r
\r
*/\r
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SystemReset(void)\r
{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1) { __NOP(); } /* wait until reset */\r
}\r
\r
/*@} end of CMSIS_Core_NVICFunctions */\r
\r
\r
+/* ########################## FPU functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \fn uint32_t SCB_GetFPUType(void)\r
+ \brief get FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = SCB->MVFR0;\r
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {\r
+ return 2UL; // Double + Single precision FPU\r
+ } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {\r
+ return 1UL; // Single precision FPU\r
+ } else {\r
+ return 0UL; // No FPU\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
/* ########################## Cache functions #################################### */\r
/** \ingroup CMSIS_Core_FunctionInterface\r
\defgroup CMSIS_Core_CacheFunctions Cache Functions\r
/* Cache Size ID Register Macros */\r
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
-#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos )\r
+#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )\r
\r
\r
/** \brief Enable I-Cache\r
\r
The function turns on I-Cache\r
*/\r
-__STATIC_INLINE void SCB_EnableICache(void)\r
+__STATIC_INLINE void SCB_EnableICache (void)\r
{\r
#if (__ICACHE_PRESENT == 1)\r
__DSB();\r
__ISB();\r
- SCB->ICIALLU = 0; // invalidate I-Cache\r
- SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache\r
+ SCB->ICIALLU = 0UL; // invalidate I-Cache\r
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache\r
__DSB();\r
__ISB();\r
#endif\r
\r
The function turns off I-Cache\r
*/\r
-__STATIC_INLINE void SCB_DisableICache(void)\r
+__STATIC_INLINE void SCB_DisableICache (void)\r
{\r
#if (__ICACHE_PRESENT == 1)\r
__DSB();\r
__ISB();\r
- SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache\r
- SCB->ICIALLU = 0; // invalidate I-Cache\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache\r
+ SCB->ICIALLU = 0UL; // invalidate I-Cache\r
__DSB();\r
__ISB();\r
#endif\r
\r
The function invalidates I-Cache\r
*/\r
-__STATIC_INLINE void SCB_InvalidateICache(void)\r
+__STATIC_INLINE void SCB_InvalidateICache (void)\r
{\r
#if (__ICACHE_PRESENT == 1)\r
__DSB();\r
__ISB();\r
- SCB->ICIALLU = 0;\r
+ SCB->ICIALLU = 0UL;\r
__DSB();\r
__ISB();\r
#endif\r
\r
The function turns on D-Cache\r
*/\r
-__STATIC_INLINE void SCB_EnableDCache(void)\r
+__STATIC_INLINE void SCB_EnableDCache (void)\r
{\r
#if (__DCACHE_PRESENT == 1)\r
uint32_t ccsidr, sshift, wshift, sw;\r
uint32_t sets, ways;\r
\r
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache\r
ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);\r
\r
__DSB();\r
\r
- do { // invalidate D-Cache\r
- int32_t tmpways = ways;\r
+ do { // invalidate D-Cache\r
+ uint32_t tmpways = ways;\r
do {\r
sw = ((tmpways << wshift) | (sets << sshift));\r
SCB->DCISW = sw;\r
} while(sets--);\r
__DSB();\r
\r
- SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache\r
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache\r
\r
__DSB();\r
__ISB();\r
\r
The function turns off D-Cache\r
*/\r
-__STATIC_INLINE void SCB_DisableDCache(void)\r
+__STATIC_INLINE void SCB_DisableDCache (void)\r
{\r
#if (__DCACHE_PRESENT == 1)\r
uint32_t ccsidr, sshift, wshift, sw;\r
uint32_t sets, ways;\r
\r
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache\r
ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);\r
\r
__DSB();\r
\r
- SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache\r
\r
do { // clean & invalidate D-Cache\r
- int32_t tmpways = ways;\r
+ uint32_t tmpways = ways;\r
do {\r
sw = ((tmpways << wshift) | (sets << sshift));\r
SCB->DCCISW = sw;\r
\r
__DSB();\r
__ISB();\r
- #endif\r
+ #endif\r
}\r
\r
\r
\r
The function invalidates D-Cache\r
*/\r
-__STATIC_INLINE void SCB_InvalidateDCache(void)\r
+__STATIC_INLINE void SCB_InvalidateDCache (void)\r
{\r
#if (__DCACHE_PRESENT == 1)\r
uint32_t ccsidr, sshift, wshift, sw;\r
uint32_t sets, ways;\r
\r
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache\r
ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);\r
\r
__DSB();\r
\r
do { // invalidate D-Cache\r
- int32_t tmpways = ways;\r
+ uint32_t tmpways = ways;\r
do {\r
sw = ((tmpways << wshift) | (sets << sshift));\r
SCB->DCISW = sw;\r
\r
__DSB();\r
__ISB();\r
- #endif\r
+ #endif\r
}\r
\r
\r
\r
The function cleans D-Cache\r
*/\r
-__STATIC_INLINE void SCB_CleanDCache(void)\r
+__STATIC_INLINE void SCB_CleanDCache (void)\r
{\r
#if (__DCACHE_PRESENT == 1)\r
uint32_t ccsidr, sshift, wshift, sw;\r
uint32_t sets, ways;\r
\r
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache\r
ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);\r
\r
__DSB();\r
\r
do { // clean D-Cache\r
- int32_t tmpways = ways;\r
+ uint32_t tmpways = ways;\r
do {\r
sw = ((tmpways << wshift) | (sets << sshift));\r
SCB->DCCSW = sw;\r
\r
__DSB();\r
__ISB();\r
- #endif\r
+ #endif\r
}\r
\r
\r
\r
The function cleans and Invalidates D-Cache\r
*/\r
-__STATIC_INLINE void SCB_CleanInvalidateDCache(void)\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
{\r
#if (__DCACHE_PRESENT == 1)\r
uint32_t ccsidr, sshift, wshift, sw;\r
uint32_t sets, ways;\r
\r
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache\r
ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);\r
\r
__DSB();\r
\r
do { // clean & invalidate D-Cache\r
- int32_t tmpways = ways;\r
+ uint32_t tmpways = ways;\r
do {\r
sw = ((tmpways << wshift) | (sets << sshift));\r
SCB->DCCISW = sw;\r
\r
__DSB();\r
__ISB();\r
- #endif\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)\r
+ \brief D-Cache Invalidate by address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t)addr;\r
+ uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCIMVAC = op_addr;\r
+ op_addr += linesize;\r
+ op_size -= (int32_t)linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)\r
+ \brief D-Cache Clean by address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCMVAC = op_addr;\r
+ op_addr += linesize;\r
+ op_size -= (int32_t)linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)\r
+ \brief D-Cache Clean and Invalidate by address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCIMVAC = op_addr;\r
+ op_addr += linesize;\r
+ op_size -= (int32_t)linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */\r
\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
}\r
\r
#endif\r
*/\r
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
{\r
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
{\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }\r
+ ITM->PORT[0].u8 = (uint8_t)ch;\r
}\r
return (ch);\r
}\r
/**************************************************************************//**\r
* @file core_cmFunc.h\r
* @brief CMSIS Cortex-M Core Function Access Header File\r
- * @version V4.00\r
- * @date 28. August 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
}\r
\r
\r
+/** \brief Set Base Priority with condition\r
+\r
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePriMax __ASM("basepri_max");\r
+ __regBasePriMax = (basePri & 0xff);\r
+}\r
+\r
+\r
/** \brief Get Fault Mask\r
\r
This function returns the current value of the Fault Mask register.\r
{\r
uint32_t result;\r
\r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
return(result);\r
}\r
\r
}\r
\r
\r
+/** \brief Set Base Priority with condition\r
+\r
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
/** \brief Get Fault Mask\r
\r
This function returns the current value of the Fault Mask register.\r
/**************************************************************************//**\r
* @file core_cmInstr.h\r
* @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V4.00\r
- * @date 28. August 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
so that all instructions following the ISB are fetched from cache or\r
memory, after the instruction has been completed.\r
*/\r
-#define __ISB() __isb(0xF)\r
-\r
+#define __ISB() do {\\r
+ __schedule_barrier();\\r
+ __isb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0)\r
\r
/** \brief Data Synchronization Barrier\r
\r
This function acts as a special kind of Data Memory Barrier.\r
It completes when all explicit memory accesses before this instruction complete.\r
*/\r
-#define __DSB() __dsb(0xF)\r
-\r
+#define __DSB() do {\\r
+ __schedule_barrier();\\r
+ __dsb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0)\r
\r
/** \brief Data Memory Barrier\r
\r
This function ensures the apparent order of the explicit memory operations before\r
and after the instruction, without ensuring their completion.\r
*/\r
-#define __DMB() __dmb(0xF)\r
-\r
+#define __DMB() do {\\r
+ __schedule_barrier();\\r
+ __dmb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0)\r
\r
/** \brief Reverse byte order (32 bit)\r
\r
#define __BKPT(value) __breakpoint(value)\r
\r
\r
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)\r
-\r
/** \brief Reverse bit order of value\r
\r
This function reverses the bit order of the given value.\r
\param [in] value Value to reverse\r
\return Reversed value\r
*/\r
-#define __RBIT __rbit\r
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)\r
+ #define __RBIT __rbit\r
+#else\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end\r
+\r
+ result = value; // r will be reversed bits of v; first get LSB of v\r
+ for (value >>= 1; value; value >>= 1)\r
+ {\r
+ result <<= 1;\r
+ result |= value & 1;\r
+ s--;\r
+ }\r
+ result <<= s; // shift when v's highest bits are zero\r
+ return(result);\r
+}\r
+#endif\r
+\r
\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+\r
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)\r
\r
/** \brief LDR Exclusive (8 bit)\r
\r
#define __USAT __usat\r
\r
\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __clz\r
-\r
-\r
/** \brief Rotate Right with Extend (32 bit)\r
\r
- This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.\r
+ This function moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
\r
\param [in] value Value to rotate\r
\return Rotated value\r
\r
No Operation does nothing. This instruction can be used for code alignment purposes.\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
{\r
__ASM volatile ("nop");\r
}\r
Wait For Interrupt is a hint instruction that suspends execution\r
until one of a number of events occurs.\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
{\r
__ASM volatile ("wfi");\r
}\r
Wait For Event is a hint instruction that permits the processor to enter\r
a low-power state until one of a number of events occurs.\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
{\r
__ASM volatile ("wfe");\r
}\r
\r
Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
{\r
__ASM volatile ("sev");\r
}\r
so that all instructions following the ISB are fetched from cache or\r
memory, after the instruction has been completed.\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
{\r
- __ASM volatile ("isb");\r
+ __ASM volatile ("isb 0xF":::"memory");\r
}\r
\r
\r
This function acts as a special kind of Data Memory Barrier.\r
It completes when all explicit memory accesses before this instruction complete.\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
{\r
- __ASM volatile ("dsb");\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
}\r
\r
\r
This function ensures the apparent order of the explicit memory operations before\r
and after the instruction, without ensuring their completion.\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
{\r
- __ASM volatile ("dmb");\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
}\r
\r
\r
\param [in] value Value to reverse\r
\return Reversed value\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
{\r
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
return __builtin_bswap32(value);\r
\param [in] value Value to reverse\r
\return Reversed value\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
{\r
uint32_t result;\r
\r
\param [in] value Value to reverse\r
\return Reversed value\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
{\r
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
return (short)__builtin_bswap16(value);\r
\param [in] value Number of Bits to rotate\r
\return Rotated value\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
{\r
- return (op1 >> op2) | (op1 << (32 - op2)); \r
+ return (op1 >> op2) | (op1 << (32 - op2));\r
}\r
\r
\r
#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
\r
\r
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)\r
-\r
/** \brief Reverse bit order of value\r
\r
This function reverses the bit order of the given value.\r
\param [in] value Value to reverse\r
\return Reversed value\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
{\r
uint32_t result;\r
\r
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)\r
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
+#else\r
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end\r
+\r
+ result = value; // r will be reversed bits of v; first get LSB of v\r
+ for (value >>= 1; value; value >>= 1)\r
+ {\r
+ result <<= 1;\r
+ result |= value & 1;\r
+ s--;\r
+ }\r
+ result <<= s; // shift when v's highest bits are zero\r
+#endif\r
+ return(result);\r
}\r
\r
\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __builtin_clz\r
+\r
+\r
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)\r
+\r
/** \brief LDR Exclusive (8 bit)\r
\r
This function executes a exclusive LDR instruction for 8 bit value.\r
\param [in] ptr Pointer to data\r
\return value of type uint8_t at (*ptr)\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
{\r
uint32_t result;\r
\r
\param [in] ptr Pointer to data\r
\return value of type uint16_t at (*ptr)\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
{\r
uint32_t result;\r
\r
\param [in] ptr Pointer to data\r
\return value of type uint32_t at (*ptr)\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
{\r
uint32_t result;\r
\r
\return 0 Function succeeded\r
\return 1 Function failed\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
{\r
uint32_t result;\r
\r
\return 0 Function succeeded\r
\return 1 Function failed\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
{\r
uint32_t result;\r
\r
\return 0 Function succeeded\r
\return 1 Function failed\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
{\r
uint32_t result;\r
\r
This function removes the exclusive lock which is created by LDREX.\r
\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
{\r
__ASM volatile ("clrex" ::: "memory");\r
}\r
})\r
\r
\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
- return ((uint8_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
/** \brief Rotate Right with Extend (32 bit)\r
\r
- This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.\r
+ This function moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
\r
\param [in] value Value to rotate\r
\return Rotated value\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
{\r
uint32_t result;\r
\r
\param [in] ptr Pointer to data\r
\return value of type uint8_t at (*ptr)\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r
{\r
uint32_t result;\r
\r
\param [in] ptr Pointer to data\r
\return value of type uint16_t at (*ptr)\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r
{\r
uint32_t result;\r
\r
\param [in] ptr Pointer to data\r
\return value of type uint32_t at (*ptr)\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r
{\r
uint32_t result;\r
\r
\param [in] value Value to store\r
\param [in] ptr Pointer to location\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r
{\r
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
}\r
\param [in] value Value to store\r
\param [in] ptr Pointer to location\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r
{\r
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
}\r
\param [in] value Value to store\r
\param [in] ptr Pointer to location\r
*/\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r
{\r
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );\r
}\r
/**************************************************************************//**\r
* @file core_cmSimd.h\r
* @brief CMSIS Cortex-M SIMD Header File\r
- * @version V4.00\r
- * @date 22. August 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
/**************************************************************************//**\r
* @file core_sc000.h\r
* @brief CMSIS SC000 Core Peripheral Access Layer Header File\r
- * @version V4.00\r
- * @date 22. August 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
{\r
struct\r
{\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} APSR_Type;\r
\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31 /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29 /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28 /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
\r
/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
*/\r
uint32_t w; /*!< Type used for word access */\r
} IPSR_Type;\r
\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
*/\r
struct\r
{\r
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} xPSR_Type;\r
\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Control Registers (CONTROL).\r
*/\r
{\r
struct\r
{\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
} b; /*!< Structure used for bit access */\r
uint32_t w; /*!< Type used for word access */\r
} CONTROL_Type;\r
\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
/*@} end of group CMSIS_CORE */\r
\r
\r
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
uint32_t RESERVED1[154];\r
- __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */\r
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
} SCB_Type;\r
\r
/* SCB CPUID Register Definitions */\r
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
\r
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
\r
-/* SCB Security Features Register Definitions */\r
-#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */\r
-#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */\r
-\r
-#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */\r
-#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */\r
-\r
/*@} end of group CMSIS_SCB */\r
\r
\r
\r
/* Auxiliary Control Register Definitions */\r
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
\r
/*@} end of group CMSIS_SCnotSCB */\r
\r
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
\r
/*@} end of group CMSIS_SysTick */\r
\r
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
\r
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
\r
/* MPU Control Register */\r
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
\r
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
\r
/* MPU Region Number Register */\r
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
\r
/* MPU Region Base Address Register */\r
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */\r
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
\r
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
\r
/* MPU Region Attribute and Size Register */\r
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
\r
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
\r
/*@} end of group CMSIS_MPU */\r
#endif\r
\r
/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
\r
\r
/** \brief Enable External Interrupt\r
*/\r
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+ NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+ NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+ return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+ NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+ NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
- if(IRQn < 0) {\r
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ if((int32_t)(IRQn) < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
else {\r
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
}\r
\r
\r
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
- if(IRQn < 0) {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ if((int32_t)(IRQn) < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
else {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
}\r
\r
\r
{\r
__DSB(); /* Ensure all outstanding memory accesses included\r
buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
SCB_AIRCR_SYSRESETREQ_Msk);\r
__DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
+ while(1) { __NOP(); } /* wait until reset */\r
}\r
\r
/*@} end of CMSIS_Core_NVICFunctions */\r
*/\r
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */\r
\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
}\r
\r
#endif\r
/**************************************************************************//**\r
* @file core_sc300.h\r
* @brief CMSIS SC300 Core Peripheral Access Layer Header File\r
- * @version V4.00\r
- * @date 22. August 2014\r
+ * @version V4.10\r
+ * @date 18. March 2015\r
*\r
* @note\r
*\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
{\r
struct\r
{\r
-#if (__CORTEX_M != 0x04)\r
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
uint32_t w; /*!< Type used for word access */\r
} APSR_Type;\r
\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31 /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29 /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28 /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
\r
/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
*/\r
uint32_t w; /*!< Type used for word access */\r
} IPSR_Type;\r
\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
*/\r
struct\r
{\r
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
uint32_t w; /*!< Type used for word access */\r
} xPSR_Type;\r
\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
\r
/** \brief Union type to access the Control Registers (CONTROL).\r
*/\r
{\r
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
} b; /*!< Structure used for bit access */\r
uint32_t w; /*!< Type used for word access */\r
} CONTROL_Type;\r
\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
/*@} end of group CMSIS_CORE */\r
\r
\r
\r
/* Software Triggered Interrupt Register Definitions */\r
#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
\r
/*@} end of group CMSIS_NVIC */\r
\r
__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
uint32_t RESERVED0[5];\r
__IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED1[129];\r
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
} SCB_Type;\r
\r
/* SCB CPUID Register Definitions */\r
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
\r
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
/* SCB Vector Table Offset Register Definitions */\r
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
\r
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
\r
/* SCB System Control Register Definitions */\r
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
\r
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
\r
/* SCB System Handler Control and State Register Definitions */\r
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
\r
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
\r
/* SCB Configurable Fault Status Registers Definitions */\r
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
\r
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
\r
/* SCB Hard Fault Status Registers Definitions */\r
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
\r
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
\r
/*@} end of group CMSIS_SCB */\r
\r
\r
/* Interrupt Controller Type Register Definitions */\r
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
\r
/*@} end of group CMSIS_SCnotSCB */\r
\r
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
\r
/*@} end of group CMSIS_SysTick */\r
\r
\r
/* ITM Trace Privilege Register Definitions */\r
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
\r
/* ITM Trace Control Register Definitions */\r
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
\r
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
\r
/* ITM Integration Write Register Definitions */\r
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
\r
/* ITM Integration Read Register Definitions */\r
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
\r
/* ITM Integration Mode Control Register Definitions */\r
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
\r
/* ITM Lock Status Register Definitions */\r
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
\r
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
\r
/*@}*/ /* end of group CMSIS_ITM */\r
\r
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
\r
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
\r
/* DWT CPI Count Register Definitions */\r
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
\r
/* DWT Exception Overhead Count Register Definitions */\r
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
\r
/* DWT Sleep Count Register Definitions */\r
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
\r
/* DWT LSU Count Register Definitions */\r
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
\r
/* DWT Folded-instruction Count Register Definitions */\r
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
\r
/* DWT Comparator Mask Register Definitions */\r
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
\r
/* DWT Comparator Function Register Definitions */\r
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
\r
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
\r
/*@}*/ /* end of group CMSIS_DWT */\r
\r
\r
/* TPI Asynchronous Clock Prescaler Register Definitions */\r
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
\r
/* TPI Selected Pin Protocol Register Definitions */\r
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
\r
/* TPI Formatter and Flush Status Register Definitions */\r
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
\r
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
\r
/* TPI Formatter and Flush Control Register Definitions */\r
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
\r
/* TPI TRIGGER Register Definitions */\r
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
\r
/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
\r
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
\r
/* TPI ITATBCTR2 Register Definitions */\r
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
\r
/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
\r
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
\r
/* TPI ITATBCTR0 Register Definitions */\r
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
\r
/* TPI Integration Mode Control Register Definitions */\r
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
\r
/* TPI DEVID Register Definitions */\r
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
\r
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
\r
/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
/*@}*/ /* end of group CMSIS_TPI */\r
\r
\r
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
\r
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
\r
/* MPU Control Register */\r
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
\r
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
\r
/* MPU Region Number Register */\r
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
\r
/* MPU Region Base Address Register */\r
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
\r
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
\r
/* MPU Region Attribute and Size Register */\r
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
\r
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
\r
/*@} end of group CMSIS_MPU */\r
#endif\r
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
\r
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
\r
/* Debug Core Register Selector Register */\r
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
\r
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
\r
/* Debug Exception and Monitor Control Register */\r
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
\r
/*@} end of group CMSIS_CoreDebug */\r
\r
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
{\r
uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
\r
reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */\r
SCB->AIRCR = reg_value;\r
}\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ if((int32_t)IRQn < 0) {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
}\r
\r
\r
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ if((int32_t)IRQn < 0) {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));\r
+ }\r
}\r
\r
\r
*/\r
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
);\r
}\r
\r
*/\r
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
}\r
\r
\r
*/\r
__STATIC_INLINE void NVIC_SystemReset(void)\r
{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1) { __NOP(); } /* wait until reset */\r
}\r
\r
/*@} end of CMSIS_Core_NVICFunctions */\r
*/\r
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */\r
\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
}\r
\r
#endif\r
*/\r
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
{\r
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
{\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }\r
+ ITM->PORT[0].u8 = (uint8_t)ch;\r
}\r
return (ch);\r
}\r
/* The base period used by the timer test tasks. */\r
#define mainTIMER_TEST_PERIOD ( 50 )\r
\r
-/* The LED is used to show the demo status. */\r
+/* The LED is used to show the demo status. (not connected on Rev A hardware) */\r
#define mainTOGGLE_LED() HAL_GPIO_TogglePin( GPIOF, GPIO_PIN_10 )\r
\r
/*-----------------------------------------------------------*/\r
******************************************************************************\r
* @file stm32f7xx_hal.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief This file contains all the functions prototypes for the HAL \r
* module driver.\r
******************************************************************************\r
******************************************************************************\r
* @file stm32f7xx_hal_adc.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of ADC HAL extension module.\r
******************************************************************************\r
* @attention\r
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler\r
* @{\r
*/ \r
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)\r
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)\r
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)\r
+#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)\r
+#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)\r
/**\r
* @}\r
*/ \r
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))\r
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))\r
\r
-#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)\r
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)\r
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)\r
/**\r
/** @defgroup ADC_Private_Macros ADC Private Macros\r
* @{\r
*/\r
-#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \\r
- ((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \\r
- ((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \\r
- ((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV8))\r
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))\r
#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \\r
((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \\r
((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \\r
((__REGTRIG__) == ADC_SOFTWARE_START))\r
#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \\r
((__ALIGN__) == ADC_DATAALIGN_LEFT)) \r
-#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_1) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_2) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_3) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_4) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_5) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_6) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_7) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_8) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_9) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_10) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_11) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_12) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_13) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_14) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_15) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_16) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_17) || \\r
- ((__CHANNEL__) == ADC_CHANNEL_18)) \r
+ \r
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \\r
((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \\r
((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \\r
******************************************************************************\r
* @file stm32f7xx_hal_adc.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of ADC HAL module.\r
******************************************************************************\r
* @attention\r
/**\r
* @}\r
*/ \r
- \r
+\r
+/** @defgroup ADCEx_channels ADC Specific Channels\r
+ * @{\r
+ */\r
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) \r
+/**\r
+ * @}\r
+ */\r
+ \r
/**\r
* @}\r
*/ \r
/** @defgroup ADC_Exported_Macros ADC Exported Macros\r
* @{\r
*/\r
- \r
/**\r
* @}\r
*/\r
/** @defgroup ADCEx_Private_Macros ADC Private Macros\r
* @{\r
*/\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \\r
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))\r
+ \r
#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \\r
((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \\r
((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \\r
******************************************************************************\r
* @file stm32f7xx_hal_can.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of CAN HAL module.\r
******************************************************************************\r
* @attention\r
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.\r
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */\r
\r
- uint32_t Data[8]; /*!< Contains the data to be transmitted.\r
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.\r
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */\r
\r
}CanTxMsgTypeDef;\r
uint32_t DLC; /*!< Specifies the length of the frame that will be received.\r
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */\r
\r
- uint32_t Data[8]; /*!< Contains the data to be received.\r
+ uint8_t Data[8]; /*!< Contains the data to be received.\r
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */\r
\r
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.\r
*/\r
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */\r
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */\r
-\r
/**\r
* @}\r
*/\r
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\r
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r
\r
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \\r
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \\r
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \\r
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \\r
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \\r
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))\r
- \r
-\r
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_SLAK) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \\r
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) || \\r
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \\r
- ((FLAG) == CAN_FLAG_WKU))\r
-\r
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\\r
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\\r
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\\r
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
-\r
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\\r
- ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\\r
- ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\\r
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
-\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_cec.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of CEC HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_conf_template.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief HAL configuration template file. \r
* This file should be copied to the application folder and renamed\r
* to stm32f7xx_hal_conf.h.\r
******************************************************************************\r
* @file stm32f7xx_hal_cortex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of CORTEX HAL module.\r
******************************************************************************\r
* @attention\r
#if (__MPU_PRESENT == 1)\r
/**\r
* @brief Disables the MPU\r
- * @param None \r
* @retval None\r
*/\r
__STATIC_INLINE void HAL_MPU_Disable(void)\r
/**\r
* @brief Enables the MPU\r
* @param MPU_Control: Specifies the control mode of the MPU during hard fault, \r
- * NMI, FAULTMASK and privileged accessto the default memory \r
+ * NMI, FAULTMASK and privileged access to the default memory \r
* This parameter can be one of the following values:\r
* @arg MPU_HFNMI_PRIVDEF_NONE\r
* @arg MPU_HARDFAULT_NMI\r
******************************************************************************\r
* @file stm32f7xx_hal_crc.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of CRC HAL module.\r
******************************************************************************\r
* @attention\r
* @param __VALUE__: 8-bit value to be stored in the ID register\r
* @retval None\r
*/\r
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))\r
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))\r
\r
/**\r
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.\r
******************************************************************************\r
* @file stm32f7xx_hal_crc_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of CRC HAL extension module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_cryp.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of CRYP HAL module.\r
******************************************************************************\r
* @attention\r
* @}\r
*/\r
\r
-#endif /* STM32F756xx */\r
-\r
/**\r
* @}\r
*/ \r
\r
+#endif /* STM32F756xx */\r
+\r
/**\r
* @}\r
*/ \r
******************************************************************************\r
* @file stm32f7xx_hal_cryp_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of CRYP HAL Extension module.\r
******************************************************************************\r
* @attention\r
* @}\r
*/\r
\r
-#endif /* STM32F756xx */\r
/**\r
* @}\r
*/ \r
\r
+#endif /* STM32F756xx */\r
+\r
/**\r
* @}\r
*/ \r
******************************************************************************\r
* @file stm32f7xx_hal_dac.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of DAC HAL module.\r
******************************************************************************\r
* @attention\r
extern "C" {\r
#endif\r
\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
-\r
/* Includes ------------------------------------------------------------------*/\r
#include "stm32f7xx_hal_def.h"\r
\r
/**\r
* @}\r
*/\r
-#endif /* STM32F756xx || STM32F746xx */\r
\r
/**\r
* @}\r
******************************************************************************\r
* @file stm32f7xx_hal_dac.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of DAC HAL Extension module.\r
******************************************************************************\r
* @attention\r
extern "C" {\r
#endif\r
\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
-\r
/* Includes ------------------------------------------------------------------*/\r
#include "stm32f7xx_hal_def.h"\r
\r
/**\r
* @}\r
*/\r
-#endif /* STM32F756xx || STM32F746xx */\r
\r
/**\r
* @}\r
******************************************************************************\r
* @file stm32f7xx_hal_dcmi.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of DCMI HAL module.\r
******************************************************************************\r
* @attention\r
/** @defgroup DCMI_Exported_Types DCMI Exported Types\r
* @{\r
*/\r
-/** \r
- * @brief DCMI Error source\r
- */\r
-typedef enum\r
-{ \r
- DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */\r
- DCMI_OVERRUN = 2, /*!< DCMI Overrun */\r
-}DCMI_ErrorTypeDef;\r
-\r
/** \r
* @brief HAL DCMI State structures definition\r
*/ \r
* @{\r
*/\r
\r
-/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and de-initialization functions\r
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions\r
* @{\r
*/\r
/* Initialization and de-initialization functions *****************************/\r
* @}\r
*/\r
\r
-/** @addtogroup DCMI_Exported_Functions_Group2 Operations functions\r
+/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions\r
* @{\r
*/\r
/* IO operation functions *****************************************************/\r
******************************************************************************\r
* @file stm32f7xx_hal_dcmi_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of DCMI Extension HAL module.\r
******************************************************************************\r
* @attention\r
* @{\r
*/\r
\r
-/** @addtogroup DCMIEx DCMI Extended\r
- * @brief DCMI HAL module driver\r
+/** @addtogroup DCMIEx DCMIEx\r
* @{\r
- */ \r
+ */ \r
+ \r
\r
/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup DCMIEx_Exported_Types DCMI Extende Exported Types\r
+/** @defgroup DCMIEx_Exported_Types DCMIEx Exported Types\r
* @{\r
*/\r
/** \r
\r
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. \r
This parameter can be a value of @ref DCMI_MODE_JPEG */\r
-#if defined(STM32F746xx) || defined(STM32F756xx)\r
+\r
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface \r
This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */\r
\r
\r
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd\r
This parameter can be a value of @ref DCMIEx_Line_Select_Start */\r
- \r
-#endif /* STM32F746xx || STM32F756xx */\r
}DCMI_InitTypeDef;\r
\r
/**\r
* @}\r
*/\r
\r
-#if defined(STM32F746xx) || defined(STM32F756xx)\r
/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants\r
+/** @defgroup DCMIEx_Exported_Constants DCMIEx Exported Constants\r
* @{\r
*/\r
\r
-/** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode\r
+/** @defgroup DCMIEx_Byte_Select_Mode DCMIEx Byte Select Mode\r
* @{\r
*/\r
#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */\r
* @}\r
*/\r
\r
-/** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start\r
+/** @defgroup DCMIEx_Byte_Select_Start DCMIEx Byte Select Start\r
* @{\r
*/ \r
#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */\r
* @}\r
*/\r
\r
-/** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode\r
+/** @defgroup DCMIEx_Line_Select_Mode DCMIEx Line Select Mode\r
* @{\r
*/\r
#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */\r
* @}\r
*/\r
\r
-/** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start\r
+/** @defgroup DCMIEx_Line_Select_Start DCMIEx Line Select Start\r
* @{\r
*/ \r
#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */\r
/* Private variables ---------------------------------------------------------*/\r
/* Private constants ---------------------------------------------------------*/ \r
/* Private macro -------------------------------------------------------------*/\r
-/** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros\r
+/** @defgroup DCMIEx_Private_Macros DCMIEx Private Macros\r
* @{\r
*/\r
#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \\r
/**\r
* @}\r
*/\r
-#endif /* STM32F746xx || STM32F756xx */\r
+\r
/* Private functions ---------------------------------------------------------*/\r
\r
/**\r
******************************************************************************\r
* @file stm32f7xx_hal_def.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief This file contains HAL common defines, enumeration, macros and \r
* structures definitions. \r
******************************************************************************\r
******************************************************************************\r
* @file stm32f7xx_hal_dma.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of DMA HAL module.\r
******************************************************************************\r
* @attention\r
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))\r
\r
/**\r
- * @brief Check whether the specified DMA Stream interrupt has occurred or not.\r
+ * @brief Check whether the specified DMA Stream interrupt is enabled or not.\r
* @param __HANDLE__: DMA handle\r
* @param __INTERRUPT__: specifies the DMA interrupt source to check.\r
* This parameter can be one of the following values:\r
******************************************************************************\r
* @file stm32f7xx_hal_dma2d.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of DMA2D HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_dma_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of DMA HAL extension module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_eth.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of ETH HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_flash.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of FLASH HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_flash_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of FLASH HAL Extension module.\r
******************************************************************************\r
* @attention\r
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP\r
* @{\r
*/\r
-#define OB_IWDG_STOP_FREEZE ((uint32_t)0x40000000) /*!< Freeze IWDG counter in STOP mode */\r
-#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x00000000) /*!< IWDG counter active in STOP mode */\r
+#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */\r
+#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STOP mode */\r
/**\r
* @}\r
*/\r
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY\r
* @{\r
*/\r
-#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x80000000) /*!< Freeze IWDG counter in STANDBY mode */\r
-#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x00000000) /*!< IWDG counter active in STANDBY mode */\r
+#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STANDBY mode */\r
+#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STANDBY mode */\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_gpio.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of GPIO HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_gpio_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of GPIO HAL Extension module.\r
******************************************************************************\r
* @attention\r
#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */\r
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */\r
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */\r
-#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */\r
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */\r
-\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */\r
+#endif /* STM32F756xx || STM32F746xx */\r
/** \r
* @brief AF 10 selection \r
*/ \r
*/ \r
#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */\r
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */\r
-#define GPIO_AF12_SDMMC ((uint8_t)0xC) /* SDMMC Alternate Function mapping */\r
+#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */\r
\r
/** \r
* @brief AF 13 selection \r
*/ \r
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */\r
\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
/** \r
* @brief AF 14 selection \r
*/\r
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */\r
-\r
+#endif /* STM32F756xx || STM32F746xx */\r
/** \r
* @brief AF 15 selection \r
*/ \r
(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))\r
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\r
* @{\r
- */ \r
+ */\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \\r
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
- ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC) || \\r
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \\r
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \\r
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC))\r
+#elif defined(STM32F745xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \\r
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT))\r
+#endif /* STM32F756xx || STM32F746xx */\r
/**\r
* @}\r
*/ \r
******************************************************************************\r
* @file stm32f7xx_hal_hash.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of HASH HAL module.\r
******************************************************************************\r
* @attention\r
* @}\r
*/\r
\r
-#endif /* STM32F756xx */\r
/**\r
* @}\r
*/ \r
-\r
+#endif /* STM32F756xx */\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_hash_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of HASH HAL Extension module.\r
******************************************************************************\r
* @attention\r
* @}\r
*/\r
\r
-#endif /* STM32F756xx */\r
/**\r
* @}\r
*/ \r
-\r
+#endif /* STM32F756xx */\r
/**\r
* @}\r
*/ \r
******************************************************************************\r
* @file stm32f7xx_hal_hcd.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of HCD HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_i2c.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of I2C HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_i2c_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of I2C HAL Extension module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_i2s.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of I2S HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_irda.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of IRDA HAL module.\r
******************************************************************************\r
* @attention\r
#include "stm32f7xx_hal_irda_ex.h" \r
\r
/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions\r
+/** @addtogroup IRDA_Exported_Functions IrDA Exported Functions\r
* @{\r
*/\r
\r
-/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions\r
+/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions\r
* @{\r
*/\r
\r
* @}\r
*/\r
\r
-/** @addtogroup IRDA_Exported_Functions_Group3 Control functions\r
+/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral Control functions\r
* @{\r
*/\r
/* Peripheral State methods **************************************************/\r
******************************************************************************\r
* @file stm32f7xx_hal_irda_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of IRDA HAL Extension module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_iwdg.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of IWDG HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_lptim.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of LPTIM HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_ltdc.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of LTDC HAL module.\r
******************************************************************************\r
* @attention\r
extern "C" {\r
#endif\r
\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
/* Includes ------------------------------------------------------------------*/\r
#include "stm32f7xx_hal_def.h"\r
\r
/**\r
* @}\r
*/ \r
-\r
+#endif /* STM32F756xx || STM32F746xx */\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_nand.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of NAND HAL module.\r
******************************************************************************\r
* @attention\r
* @{\r
*/ \r
\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
/* Exported typedef ----------------------------------------------------------*/\r
/* Exported types ------------------------------------------------------------*/\r
/** @defgroup NAND_Exported_Types NAND Exported Types\r
/**\r
* @}\r
*/\r
-#endif /* STM32F756xx || STM32F746xx */\r
\r
/**\r
* @}\r
******************************************************************************\r
* @file stm32f7xx_hal_nor.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of NOR HAL module.\r
******************************************************************************\r
* @attention\r
* @{\r
*/ \r
\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
/* Exported typedef ----------------------------------------------------------*/\r
/** @defgroup NOR_Exported_Types NOR Exported Types\r
* @{\r
* @}\r
*/\r
\r
-/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions \r
+/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions \r
* @{\r
*/\r
\r
* @}\r
*/\r
\r
-/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions \r
+/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions \r
* @{\r
*/\r
\r
/**\r
* @}\r
*/\r
-#endif /* STM32F756xx || STM32F746xx */\r
+\r
/**\r
* @}\r
*/ \r
******************************************************************************\r
* @file stm32f7xx_hal_pcd.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of PCD HAL module.\r
******************************************************************************\r
* @attention\r
*/\r
#define PCD_PHY_ULPI 1\r
#define PCD_PHY_EMBEDDED 2\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value\r
+ * @{\r
+ */\r
+#ifndef USBD_HS_TRDT_VALUE\r
+ #define USBD_HS_TRDT_VALUE 9\r
+#endif /* USBD_HS_TRDT_VALUE */\r
+#ifndef USBD_FS_TRDT_VALUE\r
+ #define USBD_FS_TRDT_VALUE 5\r
+#endif /* USBD_HS_TRDT_VALUE */\r
+\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_pcd_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of PCD HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_pwr.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of PWR HAL module.\r
******************************************************************************\r
* @attention\r
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line\r
* @{\r
*/\r
-#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
+#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_pwr_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of PWR HAL Extension module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_qspi.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of QSPI HAL module.\r
******************************************************************************\r
* @attention\r
This parameter can be a number between 0 and 255 */ \r
\r
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)\r
- This parameter can be a value between 1 and 16 */\r
+ This parameter can be a value between 1 and 32 */\r
\r
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to \r
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)\r
/** @defgroup QSPI_SIOOMode QSPI SIOO Mode\r
* @{\r
*/\r
-#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/\r
-#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/\r
+#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/\r
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/\r
/**\r
* @}\r
*/\r
/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold \r
* @{\r
*/\r
-#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16))\r
+#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_rcc.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of RCC HAL module.\r
******************************************************************************\r
* @attention\r
* using it.\r
* @{\r
*/\r
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_WWDGEN)) != RESET)\r
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_PWREN)) != RESET)\r
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)\r
\r
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_WWDGEN)) == RESET)\r
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_PWREN)) == RESET)\r
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)\r
/**\r
* @}\r
*/ \r
* @note By default, all peripheral clocks are enabled during SLEEP mode.\r
* @{\r
*/\r
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_CRCSMEN)) != RESET)\r
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_DMA1SMEN)) != RESET)\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)\r
\r
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_CRCSMEN)) == RESET)\r
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_DMA1SMEN)) == RESET)\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)\r
/**\r
* @}\r
*/\r
* @note By default, all peripheral clocks are enabled during SLEEP mode.\r
* @{\r
*/\r
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_WWDGSMEN)) != RESET)\r
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_PWRSMEN)) != RESET)\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)\r
\r
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_WWDGSMEN)) == RESET)\r
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_PWRSMEN)) == RESET)\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)\r
/**\r
* @}\r
*/\r
* @note By default, all peripheral clocks are enabled during SLEEP mode.\r
* @{\r
*/\r
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2SMENR & (RCC_APB2SMENR_SYSCFGSMEN)) != RESET)\r
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2SMENR & (RCC_APB2SMENR_SYSCFGSMEN)) == RESET)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)\r
/**\r
* @}\r
*/ \r
* output frequency is between 192 and 432 MHz.\r
* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)\r
* This parameter must be a number in the range {2, 4, 6, or 8}.\r
- * @note You have to set the PLLP parameter correctly to not exceed 200 MHz on\r
+ * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on\r
* the System clock frequency.\r
* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks\r
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
(RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \\r
((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \\r
((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))\r
+ \r
+/** @brief Macro to configure the PLL clock source.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __PLLSOURCE__: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * \r
+ */\r
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))\r
+\r
+/** @brief Macro to configure the PLL multiplication factor.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r
+ * of 2 MHz to limit PLL jitter.\r
+ * \r
+ */\r
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_rcc_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of RCC HAL Extension module.\r
******************************************************************************\r
* @attention\r
This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r
\r
uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.\r
- This parameter must be a number between Min_Data = 2 and Max_Data = 8. \r
- This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r
+ This parameter must be a number between 0 and 3 for respective values 2, 4, 6 and 8. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source SPDDIF-RX */\r
}RCC_PLLI2SInitTypeDef;\r
\r
/** \r
This parameter will be used only when PLLSAI is selected as Clock Source LTDC */\r
\r
uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.\r
- This parameter must be a number between Min_Data = 2 and Max_Data = 8. \r
+ This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider\r
This parameter will be used only when PLLSAI is disabled */\r
}RCC_PLLSAIInitTypeDef;\r
\r
* @{\r
*/\r
#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)\r
+#endif /* STM32F756xx || STM32F746xx */\r
#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)\r
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)\r
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)\r
#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)\r
#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)\r
#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)\r
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000)\r
\r
\r
/**\r
UNUSED(tmpreg); \\r
} while(0)\r
\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_CLK_ENABLE() do { \\r
__IO uint32_t tmpreg; \\r
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\r
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\r
UNUSED(tmpreg); \\r
} while(0)\r
+#endif /* STM32F756xx || STM32F746xx */\r
\r
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))\r
#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\r
#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))\r
#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))\r
#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))\r
-\r
+#endif /* STM32F756xx || STM32F746xx */\r
/**\r
* @}\r
*/\r
#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)\r
#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)\r
#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)\r
-\r
+#endif /* STM32F756xx || STM32F746xx */\r
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)\r
#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\r
#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)\r
#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)\r
#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)\r
#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) \r
-\r
+#endif /* STM32F756xx || STM32F746xx */\r
/**\r
* @}\r
*/ \r
#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))\r
#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))\r
#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))\r
+#endif /* STM32F756xx || STM32F746xx */\r
\r
#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))\r
#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\r
#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))\r
#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))\r
#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))\r
-\r
+#endif /* STM32F756xx || STM32F746xx */\r
/**\r
* @}\r
*/ \r
#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))\r
#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))\r
#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))\r
+#endif /* STM32F756xx || STM32F746xx */\r
\r
#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))\r
#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\r
#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))\r
#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))\r
#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))\r
-\r
+#endif /* STM32F756xx || STM32F746xx */\r
/**\r
* @}\r
*/\r
#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)\r
#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)\r
#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)\r
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)\r
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)\r
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)\r
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)\r
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)\r
#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)\r
#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)\r
#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)\r
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)\r
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)\r
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)\r
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)\r
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)\r
#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)\r
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)\r
#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)\r
+#endif /* STM32F756xx || STM32F746xx */\r
\r
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)\r
#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)\r
#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)\r
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)\r
#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)\r
+#endif /* STM32F756xx || STM32F746xx */\r
/**\r
* @}\r
*/\r
* @param __PLLSAIR__: specifies the division factor for LTDC clock\r
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
* @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks\r
- * This parameter can be a divider by 2, 4, 6 or 8.\r
+ * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider .\r
*/ \r
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))\r
\r
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r
* on the I2S clock frequency.\r
* @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.\r
- * This parameter can be a divider by 2, 4, 6 or 8. \r
+ * This parameter can be a number between 0 and 3 for respective values 2, 4, 6 and 8 \r
*/\r
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))\r
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))\r
\r
/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.\r
* @note This function must be called before enabling the PLLI2S. \r
/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters\r
* @{\r
*/\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \\r
(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
- (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) \r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#elif defined(STM32F745xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#endif /* STM32F756xx || STM32F746xx */\r
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))\r
#define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))\r
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
******************************************************************************\r
* @file stm32f7xx_hal_rng.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of RNG HAL module.\r
******************************************************************************\r
* @attention\r
extern "C" {\r
#endif\r
\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
- \r
- \r
/* Includes ------------------------------------------------------------------*/\r
#include "stm32f7xx_hal_def.h"\r
\r
* @}\r
*/ \r
\r
-#endif /* STM32F756xx || STM32F746xx */\r
-\r
#ifdef __cplusplus\r
}\r
#endif\r
******************************************************************************\r
* @file stm32f7xx_hal_rtc.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of RTC HAL module.\r
******************************************************************************\r
* @attention\r
\r
#define RTC_TIMEOUT_VALUE 1000\r
\r
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */\r
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_rtc_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of RTC HAL Extension module.\r
******************************************************************************\r
* @attention\r
/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection\r
* @{\r
*/ \r
-#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)\r
+#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)\r
#define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00000002)\r
#define RTC_TIMESTAMPPIN_PC1 ((uint32_t)0x00000004)\r
/**\r
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants\r
* @{\r
*/\r
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ \r
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ \r
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ \r
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ \r
/**\r
* @}\r
*/\r
((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))\r
#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & (uint32_t)0xFFFFFFD6) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))\r
#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)0xFFB6FFFB) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))\r
-#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_PC13) || \\r
+#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \\r
((__PIN__) == RTC_TIMESTAMPPIN_PI8) || \\r
((__PIN__) == RTC_TIMESTAMPPIN_PC1))\r
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \\r
******************************************************************************\r
* @file stm32f7xx_hal_sai.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SAI HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_sai_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SAI Extension HAL module.\r
******************************************************************************\r
* @attention\r
* @{\r
*/\r
\r
-/** @addtogroup SAIEx_Exported_Functions_Group1 SAI Extended Functions Group1\r
+/** @addtogroup SAIEx_Exported_Functions_Group1 Extension features functions\r
* @{\r
*/\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_sd.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SD HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_sdram.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SDRAM HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_smartcard.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SMARTCARD HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_smartcard_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SMARTCARD HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_spdifrx.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SPDIFRX HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_spi.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SPI HAL module.\r
******************************************************************************\r
* @attention\r
* @}\r
*/\r
\r
-/** @addtogroup SPI_Exported_Functions_Group2 Input and Output operation functions \r
+/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions\r
* @{\r
*/\r
\r
* @}\r
*/\r
\r
-/** @addtogroup SPI_Exported_Functions_Group3 Peripheral Control functions \r
+/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r
* @{\r
*/\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_sram.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SRAM HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_tim.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of TIM HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_tim_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of TIM HAL Extension module.\r
******************************************************************************\r
* @attention\r
/* Includes ------------------------------------------------------------------*/\r
#include "stm32f7xx_hal_def.h"\r
\r
-/** @addtogroup STM32F7xx_HAL\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
* @{\r
*/\r
\r
*/\r
\r
/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup TIMEx_Exported_Constants TIM Exported Constants\r
+/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants\r
* @{\r
*/\r
\r
-/** @defgroup TIMEx_Channel TIM Channel\r
+/** @defgroup TIMEx_Channel TIMEx Channel\r
* @{\r
*/\r
\r
* @}\r
*/ \r
\r
-/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes\r
+/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes\r
* @{\r
*/\r
#define TIM_OCMODE_TIMING ((uint32_t)0x0000)\r
* @}\r
*/\r
\r
-/** @defgroup TIMEx_Remap TIM Remap\r
+/** @defgroup TIMEx_Remap TIMEx Remap\r
* @{\r
*/\r
#define TIM_TIM2_TIM8_TRGO (0x00000000)\r
* @}\r
*/ \r
\r
-/** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source\r
+/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source\r
* @{\r
*/\r
#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) \r
* @}\r
*/\r
\r
-/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable\r
+/** @defgroup TIMEx_Break2_Input_enable_disable TIMEx Break input 2 Enable\r
* @{\r
*/ \r
#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)\r
* @}\r
*/\r
\r
-/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3\r
+/** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3\r
* @{\r
*/\r
#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */\r
* @}\r
*/\r
\r
-/** @defgroup TIMEx_Master_Mode_Selection_2 TIM Extended Master Mode Selection 2 (TRGO2)\r
+/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)\r
* @{\r
*/ \r
#define TIM_TRGO2_RESET ((uint32_t)0x00000000) \r
* @}\r
*/ \r
\r
-/** @defgroup TIMEx_Slave_Mode TIM Extended Slave mode\r
+/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode\r
* @{\r
*/\r
#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)\r
*/\r
\r
/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\r
+/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros\r
* @{\r
*/ \r
\r
/* Private variables ---------------------------------------------------------*/\r
/* Private constants ---------------------------------------------------------*/\r
/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup TIMEx_Private_Macros TIM Private Macros\r
+/** @defgroup TIMEx_Private_Macros TIMEx Private Macros\r
* @{\r
*/\r
#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
*/ \r
\r
/* Private functions ---------------------------------------------------------*/\r
-/** @defgroup TIMEx_Private_Functions TIM Private Functions\r
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions\r
* @{\r
*/\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_uart.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of UART HAL module.\r
******************************************************************************\r
* @attention\r
\r
/** @brief Check UART Baud rate\r
* @param BAUDRATE: Baudrate specified by the user\r
- * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 200 MHz)\r
+ * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)\r
* divided by the smallest oversampling used on the USART (i.e. 8)\r
* @retval Test result (TRUE or FALSE).\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_uart_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of UART HAL Extension module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_usart.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of USART HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_usart_ex.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of USART HAL Extension module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal_wwdg.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of WWDG HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_ll_fmc.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of FMC HAL module.\r
******************************************************************************\r
* @attention\r
/** @addtogroup FMC_LL\r
* @{\r
*/\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
- \r
\r
/** @addtogroup FMC_LL_Private_Macros\r
* @{\r
* @}\r
*/\r
\r
-#endif /* STM32F756xx || STM32F746xx */\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_ll_sdmmc.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of SDMMC HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_ll_usb.h\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Header file of USB Core HAL module.\r
******************************************************************************\r
* @attention\r
******************************************************************************\r
* @file stm32f7xx_hal.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief HAL module driver.\r
* This is the common part of the HAL initialization\r
*\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
/**\r
- * @brief STM32F7xx HAL Driver version number V1.0.0RC1\r
+ * @brief STM32F7xx HAL Driver version number V1.0.0\r
*/\r
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
#define __STM32F7xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */\r
#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
-#define __STM32F7xx_HAL_VERSION_RC (0x01) /*!< [7:0] release candidate */ \r
+#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\\r
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\\r
|(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\\r
******************************************************************************\r
* @file stm32f7xx_hal_adc.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief This file provides firmware functions to manage the following \r
* functionalities of the Analog to Digital Convertor (ADC) peripheral:\r
* + Initialization and de-initialization functions\r
\r
if(hadc->State == HAL_ADC_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hadc->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware */\r
HAL_ADC_MspInit(hadc);\r
}\r
\r
/* Private functions ---------------------------------------------------------*/\r
\r
-/** @defgroup ADC_Private_Functions\r
+/** @defgroup ADC_Private_Functions ADC Private Functions\r
* @{\r
*/\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_adc_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief This file provides firmware functions to manage the following \r
* functionalities of the ADC extension peripheral:\r
* + Extended features functions\r
******************************************************************************\r
* @file stm32f7xx_hal_can.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief CAN HAL module driver.\r
*\r
* This file provides firmware functions to manage the following \r
==============================================================================\r
[..] \r
(#) Enable the CAN controller interface clock using \r
- __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN1_CLK_ENABLE() for CAN2\r
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2\r
-@- In case you are using CAN2 only, you have to enable the CAN1 clock.\r
\r
(#) CAN pins configuration\r
\r
\r
if(hcan->State == HAL_CAN_STATE_RESET)\r
- { \r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hcan->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware */\r
HAL_CAN_MspInit(hcan);\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_cec.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief CEC HAL module driver.\r
* \r
* This file provides firmware functions to manage the following \r
}\r
\r
/* Check the parameters */ \r
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));\r
assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));\r
assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); \r
assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));\r
\r
\r
if(hcec->State == HAL_CEC_STATE_RESET)\r
- { \r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hcec->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware : GPIO, CLOCK */\r
- HAL_CEC_MspInit(hcec);\r
+ HAL_CEC_MspInit(hcec);\r
}\r
\r
hcec->State = HAL_CEC_STATE_BUSY;\r
The end of the data processing will be indicated through the \r
dedicated CEC IRQ when using Interrupt mode.\r
The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks \r
- will be executed respectivelly at the end of the transmit or Receive process\r
+ will be executed respectively at the end of the transmit or Receive process\r
The HAL_CEC_ErrorCallback()user callback will be executed when a communication \r
error is detected\r
\r
}\r
} \r
\r
- /* check whether error occured while waiting for TXBR to be set:\r
+ /* check whether error occurred while waiting for TXBR to be set:\r
* has Tx underrun occurred ?\r
* has Tx error occurred ?\r
* has Tx Missing Acknowledge error occurred ? \r
hcec->State = HAL_CEC_STATE_ERROR;\r
}\r
\r
- /* CEC transmit error interrupt occured --------------------------------------*/\r
+ /* CEC transmit error interrupt occurred --------------------------------------*/\r
if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))\r
{ \r
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);\r
hcec->State = HAL_CEC_STATE_ERROR;\r
}\r
\r
- /* CEC TX underrun error interrupt occured --------------------------------------*/\r
+ /* CEC TX underrun error interrupt occurred --------------------------------------*/\r
if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))\r
{ \r
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);\r
hcec->State = HAL_CEC_STATE_ERROR;\r
}\r
\r
- /* CEC TX arbitration error interrupt occured --------------------------------------*/\r
+ /* CEC TX arbitration error interrupt occurred --------------------------------------*/\r
if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))\r
{ \r
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);\r
hcec->State = HAL_CEC_STATE_ERROR;\r
}\r
\r
- /* CEC RX overrun error interrupt occured --------------------------------------*/\r
+ /* CEC RX overrun error interrupt occurred --------------------------------------*/\r
if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))\r
{ \r
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);\r
hcec->State = HAL_CEC_STATE_ERROR;\r
} \r
\r
- /* CEC RX bit rising error interrupt occured --------------------------------------*/\r
+ /* CEC RX bit rising error interrupt occurred --------------------------------------*/\r
if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))\r
{ \r
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);\r
hcec->State = HAL_CEC_STATE_ERROR;\r
} \r
\r
- /* CEC RX short bit period error interrupt occured --------------------------------------*/\r
+ /* CEC RX short bit period error interrupt occurred --------------------------------------*/\r
if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))\r
{ \r
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);\r
hcec->State = HAL_CEC_STATE_ERROR;\r
} \r
\r
- /* CEC RX long bit period error interrupt occured --------------------------------------*/\r
+ /* CEC RX long bit period error interrupt occurred --------------------------------------*/\r
if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))\r
{ \r
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);\r
hcec->State = HAL_CEC_STATE_ERROR;\r
} \r
\r
- /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/\r
+ /* CEC RX missing acknowledge error interrupt occurred --------------------------------------*/\r
if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))\r
{ \r
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);\r
******************************************************************************\r
* @file stm32f7xx_hal_cortex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief CORTEX HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the CORTEX:\r
******************************************************************************\r
* @file stm32f7xx_hal_crc.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief CRC HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:\r
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);\r
/* Exported functions --------------------------------------------------------*/\r
\r
-/** @defgroup CRC_Exported_Functions\r
+/** @defgroup CRC_Exported_Functions CRC Exported Functions\r
* @{\r
*/\r
\r
\r
if(hcrc->State == HAL_CRC_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hcrc->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware */\r
HAL_CRC_MspInit(hcrc);\r
}\r
}\r
if (BufferLength%4 == 2)\r
{\r
- *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));\r
+ *(__IO uint32_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));\r
}\r
if (BufferLength%4 == 3)\r
{\r
- *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));\r
- *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; \r
+ *(__IO uint32_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));\r
+ *(__IO uint32_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; \r
}\r
}\r
\r
}\r
if ((BufferLength%2) != 0)\r
{\r
- *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; \r
+ *(__IO uint32_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; \r
}\r
\r
/* Return the CRC computed value */ \r
******************************************************************************\r
* @file stm32f7xx_hal_crc_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Extended CRC HAL module driver.\r
* \r
* This file provides firmware functions to manage the following \r
******************************************************************************\r
* @file stm32f7xx_hal_cryp.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief CRYP HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Cryptography (CRYP) peripheral:\r
/** @addtogroup STM32F7xx_HAL_Driver\r
* @{\r
*/\r
-\r
+#if defined(STM32F756xx)\r
/** @defgroup CRYP CRYP\r
* @brief CRYP HAL module driver.\r
* @{\r
*/\r
\r
-#ifdef HAL_CRYP_MODULE_ENABLED\r
\r
-#if defined(STM32F756xx)\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
* @}\r
*/\r
\r
-#endif /* STM32F756xx */\r
-\r
#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+\r
/**\r
* @}\r
*/\r
-\r
+#endif /* STM32F756xx */\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_cryp_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Extended CRYP HAL module driver\r
* This file provides firmware functions to manage the following \r
* functionalities of CRYP extension peripheral:\r
/** @addtogroup STM32F7xx_HAL_Driver\r
* @{\r
*/\r
-\r
+#if defined(STM32F756xx)\r
/** @defgroup CRYPEx CRYPEx\r
* @brief CRYP Extension HAL module driver.\r
* @{\r
*/\r
\r
-#ifdef HAL_CRYP_MODULE_ENABLED\r
\r
-#if defined(STM32F756xx)\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
/**\r
* @}\r
*/\r
-#endif /* STM32F756xx */\r
-\r
#endif /* HAL_CRYP_MODULE_ENABLED */\r
\r
/**\r
* @}\r
*/\r
-\r
+#endif /* STM32F756xx */\r
/**\r
* @}\r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_dac.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief DAC HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Digital to Analog Converter (DAC) peripheral:\r
\r
#ifdef HAL_DAC_MODULE_ENABLED\r
\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
/* Private macro -------------------------------------------------------------*/\r
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));\r
\r
if(hdac->State == HAL_DAC_STATE_RESET)\r
- { \r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hdac->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware */\r
HAL_DAC_MspInit(hdac);\r
}\r
/**\r
* @}\r
*/\r
-#endif /* STM32F756xx || STM32F746xx */\r
+\r
#endif /* HAL_DAC_MODULE_ENABLED */\r
\r
/**\r
******************************************************************************\r
* @file stm32f7xx_hal_dac_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Extended DAC HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of DAC extension peripheral:\r
\r
#ifdef HAL_DAC_MODULE_ENABLED\r
\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
-\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
/* Private macro -------------------------------------------------------------*/\r
* @}\r
*/\r
\r
-#endif /* STM32F756xx || STM32F746xx */\r
-\r
#endif /* HAL_DAC_MODULE_ENABLED */\r
\r
/**\r
******************************************************************************\r
* @file stm32f7xx_hal_dcmi.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief DCMI HAL module driver\r
* This file provides firmware functions to manage the following \r
* functionalities of the Digital Camera Interface (DCMI) peripheral:\r
\r
if(hdcmi->State == HAL_DCMI_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hdcmi->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware */\r
HAL_DCMI_MspInit(hdcmi);\r
} \r
******************************************************************************\r
* @file stm32f7xx_hal_dcmi_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief DCMI Extension HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of DCMI extension peripheral:\r
/** @addtogroup STM32F7xx_HAL_Driver\r
* @{\r
*/\r
-/** @defgroup DCMI DCMI\r
- * @brief DCMI HAL module driver\r
+/** @defgroup DCMIEx DCMIEx\r
+ * @brief DCMI Extended HAL module driver\r
* @{\r
*/\r
\r
#ifdef HAL_DCMI_MODULE_ENABLED\r
\r
-#if defined(STM32F746xx) || defined(STM32F756xx)\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
/* Private macro -------------------------------------------------------------*/\r
/* Private function prototypes -----------------------------------------------*/\r
/* Exported functions --------------------------------------------------------*/\r
\r
-/** @defgroup DCMIEx_Exported_Functions DCMI Extended Exported Functions\r
+/** @defgroup DCMIEx_Exported_Functions DCMIEx Exported Functions\r
* @{\r
*/\r
\r
/**\r
* @}\r
*/\r
-#endif /* STM32F746xx || STM32F756xx */\r
#endif /* HAL_DCMI_MODULE_ENABLED */\r
/**\r
* @}\r
******************************************************************************\r
* @file stm32f7xx_hal_dma.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief DMA HAL module driver.\r
* \r
* This file provides firmware functions to manage the following \r
******************************************************************************\r
* @file stm32f7xx_hal_dma2d.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief DMA2D HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the DMA2D peripheral:\r
\r
if(hdma2d->State == HAL_DMA2D_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hdma2d->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware */\r
HAL_DMA2D_MspInit(hdma2d);\r
}\r
if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))\r
{\r
/* Prepare the value to be wrote to the BGCOLR register */\r
- tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF);\r
+ tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF);\r
\r
/* Write to DMA2D BGCOLR register */\r
hdma2d->Instance->BGCOLR = tmp;\r
if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))\r
{\r
/* Prepare the value to be wrote to the FGCOLR register */\r
- tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF);\r
+ tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF);\r
\r
/* Write to DMA2D FGCOLR register */\r
hdma2d->Instance->FGCOLR = tmp;\r
******************************************************************************\r
* @file stm32f7xx_hal_dma_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief DMA Extension HAL module driver\r
* This file provides firmware functions to manage the following \r
* functionalities of the DMA Extension peripheral:\r
******************************************************************************\r
* @file stm32f7xx_hal_eth.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief ETH HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Ethernet (ETH) peripheral:\r
\r
if(heth->State == HAL_ETH_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ heth->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware : GPIO, CLOCK, NVIC. */\r
HAL_ETH_MspInit(heth);\r
}\r
}\r
else /* ((hclk >= 150000000)&&(hclk <= 200000000)) */\r
{\r
- /* CSR Clock Range between 150-200 MHz */ \r
+ /* CSR Clock Range between 150-216 MHz */ \r
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; \r
}\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_flash.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief FLASH HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the internal FLASH memory:\r
\r
/**\r
* @brief This function handles FLASH interrupt request.\r
- * @param None\r
* @retval None\r
*/\r
void HAL_FLASH_IRQHandler(void)\r
\r
/**\r
* @brief Get the specific FLASH error flag.\r
- * @param None\r
* @retval FLASH_ErrorCode: The returned value can be:\r
* @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag \r
* @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag \r
\r
/**\r
* @brief Set the specific FLASH error flag.\r
- * @param None\r
* @retval None\r
*/\r
static void FLASH_SetErrorCode(void)\r
******************************************************************************\r
* @file stm32f7xx_hal_flash_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Extended FLASH HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the FLASH extension peripheral:\r
pOBInit->USERConfig & OB_IWDG_SW,\r
pOBInit->USERConfig & OB_STOP_NO_RST,\r
pOBInit->USERConfig & OB_STDBY_NO_RST, \r
- pOBInit->USERConfig & OB_IWDG_STOP_FREEZE,\r
- pOBInit->USERConfig & OB_IWDG_STDBY_FREEZE);\r
+ pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,\r
+ pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);\r
}\r
\r
/* BOR Level configuration */\r
* This parameter can be one of the following values:\r
* @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 \r
* @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 \r
- * Address: specifies Boot base address\r
+ * @param Address: specifies Boot base address\r
* This parameter can be one of the following values:\r
* @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) \r
* @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r
******************************************************************************\r
* @file stm32f7xx_hal_gpio.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief GPIO HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the General Purpose Input/Output (GPIO) peripheral:\r
******************************************************************************\r
* @file stm32f7xx_hal_hash.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief HASH HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the HASH peripheral:\r
* @{\r
*/\r
\r
+#if defined(STM32F756xx)\r
+\r
/** @defgroup HASH HASH\r
* @brief HASH HAL module driver.\r
* @{\r
*/\r
-\r
#ifdef HAL_HASH_MODULE_ENABLED\r
\r
-#if defined(STM32F756xx)\r
-\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
/* Private macro -------------------------------------------------------------*/\r
\r
if(hhash->State == HAL_HASH_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hhash->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware */\r
HAL_HASH_MspInit(hhash);\r
}\r
* @}\r
*/\r
\r
-#endif /* STM32F756xx */\r
#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
/**\r
* @}\r
*/\r
+#endif /* STM32F756xx */\r
\r
/**\r
* @}\r
******************************************************************************\r
* @file stm32f7xx_hal_hash_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief HASH HAL Extension module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of HASH peripheral:\r
/** @addtogroup STM32F7xx_HAL_Driver\r
* @{\r
*/\r
+#if defined(STM32F756xx)\r
\r
/** @defgroup HASHEx HASHEx\r
* @brief HASH Extension HAL module driver.\r
\r
#ifdef HAL_HASH_MODULE_ENABLED\r
\r
-#if defined(STM32F756xx)\r
-\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
/* Private macro -------------------------------------------------------------*/\r
/**\r
* @}\r
*/\r
-#endif /* STM32F756xx */\r
-\r
#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
/**\r
* @}\r
*/\r
+#endif /* STM32F756xx */\r
\r
/**\r
* @}\r
******************************************************************************\r
* @file stm32f7xx_hal_hcd.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief HCD HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the USB Peripheral Controller:\r
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
USB_HC_Halt(hhcd->Instance, chnum); \r
}\r
- else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||\r
- (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))\r
+ \r
+ hhcd->hc[chnum].state = HC_NAK;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ \r
+ if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||\r
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))\r
{\r
/* re-activate the channel */\r
USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; \r
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
- \r
}\r
- hhcd->hc[chnum].state = HC_NAK;\r
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
}\r
}\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_i2c.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief I2C HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Inter Integrated Circuit (I2C) peripheral:\r
\r
if(hi2c->State == HAL_I2C_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hi2c->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
HAL_I2C_MspInit(hi2c);\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_i2c_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief I2C Extended HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of I2C Extended peripheral:\r
******************************************************************************\r
* @file stm32f7xx_hal_i2s.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief I2S HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Integrated Interchip Sound (I2S) peripheral:\r
/* Includes ------------------------------------------------------------------*/\r
#include "stm32f7xx_hal.h"\r
\r
-/** @addtogroup STM32F3xx_HAL_Driver\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
* @{\r
*/\r
\r
-/** @defgroup I2S I2S HAL module driver\r
+/** @defgroup I2S I2S\r
* @brief I2S HAL module driver\r
* @{\r
*/\r
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); \r
assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));\r
\r
- hi2s->State = HAL_I2S_STATE_BUSY;\r
- \r
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
- HAL_I2S_MspInit(hi2s);\r
+ if(hi2s->State == HAL_I2S_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hi2s->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+ HAL_I2S_MspInit(hi2s);\r
+ }\r
\r
+ hi2s->State = HAL_I2S_STATE_BUSY;\r
+ \r
/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \\r
\r
/**\r
* @brief Get I2S Input Clock based on I2S source clock selection\r
- * @param hsai: pointer to a I2S_HandleTypeDef structure that contains\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
* the configuration information for I2S module. \r
* @retval I2S Clock Input \r
*/\r
******************************************************************************\r
* @file stm32f7xx_hal_irda.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief IRDA HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the IrDA SIR ENDEC block (IrDA):\r
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);\r
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);\r
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);\r
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);\r
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);\r
/**\r
* @}\r
\r
if(hirda->State == HAL_IRDA_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hirda->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
HAL_IRDA_MspInit(hirda);\r
}\r
{\r
IRDA_Transmit_IT(hirda);\r
} \r
- \r
+\r
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/\r
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))\r
+ {\r
+ IRDA_EndTransmit_IT(hirda);\r
+ } \r
}\r
\r
/**\r
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);\r
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);\r
\r
- hirda->State= HAL_IRDA_STATE_TIMEOUT;\r
+ hirda->State= HAL_IRDA_STATE_READY;\r
\r
/* Process Unlocked */\r
__HAL_UNLOCK(hirda);\r
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);\r
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);\r
\r
- hirda->State= HAL_IRDA_STATE_TIMEOUT;\r
+ hirda->State= HAL_IRDA_STATE_READY;\r
\r
/* Process Unlocked */\r
__HAL_UNLOCK(hirda);\r
}\r
}\r
\r
+/**\r
+ * @brief Wraps up transmission in non blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Disable the IRDA Transmit Complete Interrupt */ \r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);\r
+ \r
+ /* Check if a receive process is ongoing or not */\r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);\r
+\r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+ \r
+ HAL_IRDA_TxCpltCallback(hirda);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
/**\r
* @brief Receive an amount of data in non blocking mode. \r
* Function called under interruption only, once\r
\r
/**\r
* @brief DMA IRDA Tx transfer completed callback \r
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
- * the configuration information for the specified IRDA module.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
* @retval None\r
*/\r
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) \r
{\r
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
\r
- /* DMA Normal mode */\r
+ /* DMA Normal mode*/\r
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
{\r
hirda->TxXferCount = 0;\r
- \r
+\r
/* Disable the DMA transfer for transmit request by setting the DMAT bit\r
- in the IRDA CR3 register */\r
- hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);\r
- \r
- /* Wait for IRDA TC Flag */\r
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, HAL_IRDA_TXDMA_TIMEOUTVALUE) != HAL_OK)\r
- {\r
- /* Timeout Occured */ \r
- hirda->State = HAL_IRDA_STATE_TIMEOUT;\r
- HAL_IRDA_ErrorCallback(hirda);\r
- }\r
- else\r
- {\r
- /* No Timeout */\r
- \r
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)\r
- {\r
- hirda->State = HAL_IRDA_STATE_BUSY_RX;\r
- }\r
- else\r
- {\r
- hirda->State = HAL_IRDA_STATE_READY;\r
- }\r
- HAL_IRDA_TxCpltCallback(hirda);\r
- }\r
+ in the IRDA CR3 register */\r
+ hirda->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);\r
+\r
+ /* Enable the IRDA Transmit Complete Interrupt */ \r
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);\r
}\r
/* DMA Circular mode */\r
else\r
{\r
- HAL_IRDA_TxCpltCallback(hirda);\r
+ HAL_IRDA_TxCpltCallback(hirda);\r
}\r
}\r
\r
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) \r
{\r
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
/* DMA Normal mode */\r
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
{\r
hirda->RxXferCount = 0;\r
- \r
+\r
/* Disable the DMA transfer for the receiver request by setting the DMAR bit \r
- in the IRDA CR3 register */\r
+ in the IRDA CR3 register */\r
hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);\r
- \r
+\r
if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) \r
{\r
hirda->State = HAL_IRDA_STATE_BUSY_TX;\r
hirda->State = HAL_IRDA_STATE_READY;\r
}\r
}\r
- \r
+\r
HAL_IRDA_RxCpltCallback(hirda);\r
}\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_iwdg.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief IWDG HAL module driver.\r
* \r
* This file provides firmware functions to manage the following \r
******************************************************************************\r
* @file stm32f7xx_hal_lptim.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief LPTIM HAL module driver.\r
* \r
* This file provides firmware functions to manage the following \r
\r
if(hlptim->State == HAL_LPTIM_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hlptim->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware */\r
HAL_LPTIM_MspInit(hlptim);\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_ltdc.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief LTDC HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the LTDC peripheral:\r
/** @addtogroup STM32F7xx_HAL_Driver\r
* @{\r
*/\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+\r
/** @defgroup LTDC LTDC\r
* @brief LTDC HAL module driver\r
* @{\r
\r
if(hltdc->State == HAL_LTDC_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hltdc->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware */\r
HAL_LTDC_MspInit(hltdc);\r
}\r
*/\r
\r
#endif /* HAL_LTDC_MODULE_ENABLED */\r
+\r
/**\r
* @}\r
*/\r
+#endif /* STM32F756xx || STM32F746xx */\r
\r
/**\r
* @}\r
******************************************************************************\r
* @file stm32f7xx_hal_msp_template.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief HAL MSP module.\r
* This file template is located in the HAL folder and should be copied \r
* to the user folder.\r
##### How to use this driver #####\r
===============================================================================\r
[..]\r
- This file is generated automatically by MicroXplorer and eventually modified \r
+ This file is generated automatically by STM32CubeMX and eventually modified \r
by the user\r
\r
@endverbatim\r
*/\r
void HAL_MspInit(void)\r
{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually \r
modified by the user\r
*/ \r
}\r
*/\r
void HAL_MspDeInit(void)\r
{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually \r
modified by the user\r
*/\r
}\r
*/\r
void HAL_PPP_MspInit(void)\r
{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually \r
modified by the user\r
*/ \r
}\r
*/\r
void HAL_PPP_MspDeInit(void)\r
{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually \r
modified by the user\r
*/\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_nand.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief NAND HAL module driver.\r
* This file provides a generic firmware to drive NAND memories mounted \r
* as external device.\r
\r
#ifdef HAL_NAND_MODULE_ENABLED\r
\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
-\r
/** @defgroup NAND NAND \r
* @brief NAND HAL module driver\r
* @{\r
\r
if(hnand->State == HAL_NAND_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hnand->Lock = HAL_UNLOCKED;\r
/* Initialize the low level hardware (MSP) */\r
HAL_NAND_MspInit(hnand);\r
} \r
/**\r
* @}\r
*/\r
-#endif /* STM32F756xx || STM32F746xx */\r
+\r
#endif /* HAL_NAND_MODULE_ENABLED */\r
\r
/**\r
******************************************************************************\r
* @file stm32f7xx_hal_nor.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief NOR HAL module driver.\r
* This file provides a generic firmware to drive NOR memories mounted \r
* as external device.\r
* @{\r
*/\r
#ifdef HAL_NOR_MODULE_ENABLED\r
-#if defined(STM32F756xx) || defined(STM32F746xx)\r
\r
/* Private typedef -----------------------------------------------------------*/\r
/* Private define ------------------------------------------------------------*/\r
* @}\r
*/\r
\r
-/** @defgroup NOR_Exported_Functions_Group3 Control functions \r
+/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions\r
* @brief management functions \r
*\r
@verbatim \r
* @}\r
*/ \r
\r
-/** @defgroup NOR_Exported_Functions_Group4 State functions \r
+/** @defgroup NOR_Exported_Functions_Group4 NOR State functions \r
* @brief Peripheral State functions \r
*\r
@verbatim \r
/**\r
* @}\r
*/\r
-#endif /* STM32F756xx || STM32F746xx */\r
#endif /* HAL_NOR_MODULE_ENABLED */\r
/**\r
* @}\r
******************************************************************************\r
* @file stm32f7xx_hal_pcd.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief PCD HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the USB Peripheral Controller:\r
if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)\r
{\r
hpcd->Init.speed = USB_OTG_SPEED_HIGH;\r
- hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ; \r
- hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_3);\r
+ hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ;\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);\r
}\r
else\r
{\r
hpcd->Init.speed = USB_OTG_SPEED_FULL;\r
hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; \r
- hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_2);\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);\r
}\r
\r
HAL_PCD_ResetCallback(hpcd);\r
******************************************************************************\r
* @file stm32f7xx_hal_pcd_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief PCD HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the USB Peripheral Controller:\r
******************************************************************************\r
* @file stm32f7xx_hal_pwr.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief PWR HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Power Controller (PWR) peripheral:\r
******************************************************************************\r
* @file stm32f7xx_hal_pwr_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Extended PWR HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of PWR extension peripheral: \r
\r
__HAL_RCC_PWR_CLK_ENABLE();\r
\r
- /* Enable the Over-drive to extend the clock frequency to 200 Mhz */\r
+ /* Enable the Over-drive to extend the clock frequency to 216 MHz */\r
__HAL_PWR_OVERDRIVE_ENABLE();\r
\r
/* Get tick */\r
\r
/**\r
* @brief Returns Voltage Scaling Range.\r
- * @param None \r
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or \r
* PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1\r
*/ \r
* This parameter can be one of the following values:\r
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,\r
* typical output voltage at 1.4 V, \r
- * system frequency up to 200 MHz.\r
+ * system frequency up to 216 MHz.\r
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,\r
* typical output voltage at 1.2 V, \r
* system frequency up to 180 MHz.\r
******************************************************************************\r
* @file stm32f7xx_hal_qspi.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief QSPI HAL module driver.\r
*\r
* This file provides firmware functions to manage the following \r
assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));\r
assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));\r
assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));\r
- assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));\r
assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));\r
\r
+ if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )\r
+ {\r
+ assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));\r
+ }\r
+ \r
/* Process locked */\r
__HAL_LOCK(hqspi);\r
\r
if(hqspi->State == HAL_QSPI_STATE_RESET)\r
- { \r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hqspi->Lock = HAL_UNLOCKED;\r
+ \r
/* Init the low level hardware : GPIO, CLOCK */\r
HAL_QSPI_MspInit(hqspi);\r
\r
* @param hqspi: QSPI handle\r
* @param cmd: structure that contains the command configuration information\r
* @param FunctionalMode: functional mode to configured\r
- * This parameter can be a value of @ref QSPI_FunctionalMode\r
+ * This parameter can be one of the following values:\r
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode\r
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode\r
* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode\r
******************************************************************************\r
* @file stm32f7xx_hal_rcc.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief RCC HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Reset and Clock Control (RCC) peripheral:\r
(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r
\r
(#) PLL (clocked by HSI or HSE), featuring two different output clocks:\r
- (++) The first output is used to generate the high speed system clock (up to 200 MHz)\r
+ (++) The first output is used to generate the high speed system clock (up to 216 MHz)\r
(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_rcc_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief Extension RCC HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities RCC extension peripheral:\r
}\r
\r
/*-------------------------------------- LTDC Configuration -----------------------------------*/\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)\r
{\r
pllsaiused = 1; \r
}\r
- \r
+#endif /* STM32F756xx || STM32F746xx */\r
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/\r
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\r
{\r
\r
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/\r
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */\r
- if(plli2sused == 1)\r
+ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))\r
{\r
/* Disable the PLLI2S */\r
__HAL_RCC_PLLI2S_DISABLE(); \r
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */\r
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);\r
- } \r
- \r
+ } \r
+ \r
+ /*----------------- In Case of PLLI2S is just selected -----------------*/ \r
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\r
+ {\r
+ /* Check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\r
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r
+\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */\r
+ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\r
+ } \r
+ \r
/* Enable the PLLI2S */\r
__HAL_RCC_PLLI2S_ENABLE();\r
\r
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);\r
} \r
\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
/*---------------------------- LTDC configuration -------------------------------*/\r
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))\r
{\r
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ \r
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);\r
} \r
- \r
+#endif /* STM32F756xx || STM32F746xx */ \r
+\r
/* Enable PLLSAI Clock */\r
__HAL_RCC_PLLSAI_ENABLE();\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_rng.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief RNG HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Random Number Generator (RNG) peripheral:\r
\r
#ifdef HAL_RNG_MODULE_ENABLED\r
\r
-#if defined(STM32F746xx) || defined(STM32F756xx)\r
-\r
-\r
/* Private types -------------------------------------------------------------*/\r
/* Private defines -----------------------------------------------------------*/\r
/* Private variables ---------------------------------------------------------*/\r
* @}\r
*/\r
\r
-#endif /* STM32F746xx || STM32F756xx */\r
#endif /* HAL_RNG_MODULE_ENABLED */\r
\r
/**\r
******************************************************************************\r
* @file stm32f7xx_hal_rtc.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief RTC HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Real Time Clock (RTC) peripheral:\r
\r
if(hrtc->State == HAL_RTC_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hrtc->Lock = HAL_UNLOCKED;\r
/* Initialize RTC MSP */\r
HAL_RTC_MspInit(hrtc);\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_rtc_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief RTC HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Real Time Clock (RTC) Extension peripheral:\r
/* Private function prototypes -----------------------------------------------*/\r
/* Private functions ---------------------------------------------------------*/\r
\r
-/** @defgroup RTCEx_Exported_Functions RTC Extended Exported Functions\r
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions\r
* @{\r
*/\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_sai.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief SAI HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Serial Audio Interface (SAI) peripheral:\r
******************************************************************************\r
* @file stm32f7xx_hal_sai_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief SAI Extension HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of SAI extension peripheral:\r
******************************************************************************\r
* @file stm32f7xx_hal_sd.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief SD card HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Secure Digital (SD) peripheral:\r
__IO HAL_SD_ErrorTypedef errorstate = SD_OK;\r
SD_InitTypeDef tmpinit;\r
\r
+ /* Allocate lock resource and initialize it */\r
+ hsd->Lock = HAL_UNLOCKED;\r
+ \r
/* Initialize the low level hardware (MSP) */\r
HAL_SD_MspInit(hsd);\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_sdram.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief SDRAM HAL module driver.\r
* This file provides a generic firmware to drive SDRAM memories mounted \r
* as external device.\r
\r
if(hsdram->State == HAL_SDRAM_STATE_RESET)\r
{ \r
+ /* Allocate lock resource and initialize it */\r
+ hsdram->Lock = HAL_UNLOCKED;\r
/* Initialize the low level hardware (MSP) */\r
HAL_SDRAM_MspInit(hsdram);\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_smartcard.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief SMARTCARD HAL module driver.\r
* This file provides firmware functions to manage the following\r
* functionalities of the SMARTCARD peripheral:\r
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r
\r
if(hsc->State == HAL_SMARTCARD_STATE_RESET)\r
- { \r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hsc->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
HAL_SMARTCARD_MspInit(hsc);\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_smartcard_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief SMARTCARD HAL module driver.\r
*\r
* This file provides extended firmware functions to manage the following \r
/* Private function prototypes -----------------------------------------------*/\r
/* Private functions ---------------------------------------------------------*/\r
\r
-/** @defgroup SMARTCARDEx_Private_Functions\r
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions\r
* @{\r
*/\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_spdifrx.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief This file provides firmware functions to manage the following \r
* functionalities of the SPDIFRX audio interface:\r
* + Initialization and Configuration\r
\r
if(hspdif->State == HAL_SPDIFRX_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hspdif->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
HAL_SPDIFRX_MspInit(hspdif);\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_spi.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief SPI HAL module driver.\r
* \r
* This file provides firmware functions to manage the following \r
\r
(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\r
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
- by calling the customed HAL_SPI_MspInit() API.\r
+ by calling the customised HAL_SPI_MspInit() API.\r
[..]\r
Circular mode restriction:\r
(#) The DMA circular mode cannot be used when the SPI is configured in these modes:\r
/* Private macro -------------------------------------------------------------*/\r
/* Private variables ---------------------------------------------------------*/\r
/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup SPI_Private_Functions SPI Private Functions\r
+/** @addtogroup SPI_Private_Functions\r
* @{\r
*/\r
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
hspi->RxXferCount--;\r
}\r
\r
- /* Set the Rx Fido thresold */\r
+ /* Set the Rx Fido threshold */\r
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
{\r
- /* set fiforxthresold according the reception data length: 16bit */\r
+ /* set fiforxthreshold according the reception data length: 16bit */\r
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
}\r
else\r
{\r
- /* set fiforxthresold according the reception data length: 8bit */\r
+ /* set fiforxthreshold according the reception data length: 8bit */\r
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
}\r
\r
/* Wait until TXE flag */\r
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) \r
{\r
- /* Erreur on the CRC reception */\r
+ /* Error on the CRC reception */\r
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
}\r
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
{\r
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
{\r
- /* Erreur on the CRC reception */\r
+ /* Error on the CRC reception */\r
hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r
}\r
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
hspi->RxXferCount -= 2;\r
if(hspi->RxXferCount <= 1)\r
{\r
- /* set fiforxthresold before to switch on 8 bit data size */\r
+ /* set fiforxthreshold before to switch on 8 bit data size */\r
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
}\r
}\r
/* Wait until TXE flag */\r
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
{\r
- /* Erreur on the CRC reception */\r
+ /* Error on the CRC reception */\r
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
}\r
\r
{\r
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
{\r
- /* Erreur on the CRC reception */\r
+ /* Error on the CRC reception */\r
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
}\r
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
/* check the data size to adapt Rx threshold and the set the function for IT treatment */\r
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r
{\r
- /* set fiforxthresold according the reception data length: 16 bit */\r
+ /* set fiforxthreshold according the reception data length: 16 bit */\r
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
hspi->RxISR = SPI_RxISR_16BIT;\r
hspi->TxISR = NULL;\r
}\r
else\r
{\r
- /* set fiforxthresold according the reception data length: 8 bit */\r
+ /* set fiforxthreshold according the reception data length: 8 bit */\r
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
hspi->RxISR = SPI_RxISR_8BIT;\r
hspi->TxISR = NULL;\r
/* check if packing mode is enabled and if there is more than 2 data to receive */\r
if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))\r
{\r
- /* set fiforxthresold according the reception data length: 16 bit */\r
+ /* set fiforxthreshold according the reception data length: 16 bit */\r
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
}\r
else\r
{\r
- /* set fiforxthresold according the reception data length: 8 bit */\r
+ /* set fiforxthreshold according the reception data length: 8 bit */\r
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
}\r
\r
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
{\r
- /* set fiforxthresold according the reception data length: 16bit */\r
+ /* set fiforxthreshold according the reception data length: 16bit */\r
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
}\r
else\r
{\r
- /* set fiforxthresold according the reception data length: 8bit */\r
+ /* set fiforxthreshold according the reception data length: 8bit */\r
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
}\r
\r
}\r
else\r
{\r
- /* set fiforxthresold according the reception data length: 8bit */\r
+ /* set fiforxthreshold according the reception data length: 8bit */\r
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
\r
if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
\r
if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
{\r
- /* set fiforxthresold according the reception data length: 16bit */\r
+ /* set fiforxthreshold according the reception data length: 16bit */\r
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
\r
/* Size must include the CRC length */\r
is performed in DMA reception complete callback */\r
hspi->hdmatx->XferHalfCpltCallback = NULL;\r
hspi->hdmatx->XferCpltCallback = NULL;\r
- \r
- /* Set the DMA error callback */\r
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r
+\r
+ if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)\r
+ {\r
+ /* Set the DMA error callback */\r
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r
+ }\r
+ else\r
+ {\r
+ hspi->hdmatx->XferErrorCallback = NULL;\r
+ } \r
\r
/* Enable the Tx DMA channel */\r
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r
- \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
/* Check if the SPI is already enabled */ \r
if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r
{\r
\r
/* Enable Tx DMA Request */ \r
hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;\r
- \r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
- \r
+ \r
return HAL_OK;\r
}\r
else\r
return;\r
}\r
\r
- /* SPI in mode Tramitter ---------------------------------------------------*/\r
+ /* SPI in mode Transmitter ---------------------------------------------------*/\r
if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))\r
{ \r
hspi->TxISR(hspi);\r
return;\r
}\r
\r
- /* SPI in Erreur Treatment ---------------------------------------------------*/\r
+ /* SPI in ERROR Treatment ---------------------------------------------------*/\r
if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) \r
{\r
- /* SPI Overrun error interrupt occured -------------------------------------*/\r
+ /* SPI Overrun error interrupt occurred -------------------------------------*/\r
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) \r
{\r
if(hspi->State != HAL_SPI_STATE_BUSY_TX)\r
}\r
}\r
\r
- /* SPI Mode Fault error interrupt occured -------------------------------------*/\r
+ /* SPI Mode Fault error interrupt occurred -------------------------------------*/\r
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)\r
{ \r
hspi->ErrorCode |= HAL_SPI_ERROR_MODF;\r
__HAL_SPI_CLEAR_MODFFLAG(hspi);\r
}\r
\r
- /* SPI Frame error interrupt occured ----------------------------------------*/\r
+ /* SPI Frame error interrupt occurred ----------------------------------------*/\r
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)\r
{ \r
hspi->ErrorCode |= HAL_SPI_ERROR_FRE;\r
* @}\r
*/\r
\r
-\r
-\r
-\r
-\r
-\r
- \r
-\r
-\r
/**\r
* @}\r
*/\r
* @}\r
*/\r
\r
-/** @addtogroup SPI_Private_Functions\r
- * @brief Private functions\r
+/** @defgroup SPI_Private_Functions SPI Private Functions\r
* @{\r
*/\r
+\r
/**\r
* @brief DMA SPI transmit process complete callback\r
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
__IO uint16_t tmpreg;\r
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
\r
- /* CRC handling */\r
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- /* Wait until TXE flag */\r
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
- {\r
- /* Erreur on the CRC reception */\r
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC; \r
- }\r
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- { \r
- tmpreg = hspi->Instance->DR;\r
- UNUSED(tmpreg); /* To avoid GCC warning */\r
- }\r
- else\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ { \r
+ /* CRC handling */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
{\r
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
- UNUSED(tmpreg); /* To avoid GCC warning */\r
-\r
- if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+ /* Wait until TXE flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
{\r
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
- {\r
- /* Erreur on the CRC reception */\r
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC; \r
- }\r
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; \r
+ }\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ { \r
+ tmpreg = hspi->Instance->DR;\r
UNUSED(tmpreg); /* To avoid GCC warning */\r
}\r
- } \r
- }\r
-\r
- /* Disable Rx DMA Request */\r
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r
- /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\r
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r
-\r
- /* Check the end of the transaction */\r
- SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);\r
- \r
- hspi->RxXferCount = 0;\r
- hspi->State = HAL_SPI_STATE_READY;\r
- \r
- /* Check if CRC error occurred */\r
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
- {\r
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
- HAL_SPI_RxCpltCallback(hspi);\r
- }\r
- else\r
- {\r
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+ else\r
+ {\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ \r
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+ {\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; \r
+ }\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Disable Rx DMA Request */\r
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r
+ /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\r
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r
+ \r
+ /* Check the end of the transaction */\r
+ SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);\r
+ \r
+ hspi->RxXferCount = 0;\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ \r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
{\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
HAL_SPI_RxCpltCallback(hspi);\r
}\r
else\r
{\r
- HAL_SPI_ErrorCallback(hspi); \r
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_RxCpltCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi); \r
+ }\r
}\r
}\r
+ else\r
+ {\r
+ HAL_SPI_RxCpltCallback(hspi);\r
+ }\r
}\r
\r
/**\r
{\r
if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
{\r
- /* Erreur on the CRC reception */\r
+ /* Error on the CRC reception */\r
hspi->ErrorCode|= HAL_SPI_ERROR_CRC; \r
}\r
tmpreg = hspi->Instance->DR;\r
hspi->RxXferCount -= 2;\r
if(hspi->RxXferCount == 1)\r
{\r
- /* set fiforxthresold according the reception data length: 8bit */\r
+ /* set fiforxthreshold according the reception data length: 8bit */\r
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
}\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_sram.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief SRAM HAL module driver.\r
* This file provides a generic firmware to drive SRAM memories \r
* mounted as external device.\r
\r
if(hsram->State == HAL_SRAM_STATE_RESET)\r
{ \r
+ /* Allocate lock resource and initialize it */\r
+ hsram->Lock = HAL_UNLOCKED;\r
/* Initialize the low level hardware (MSP) */\r
HAL_SRAM_MspInit(hsram);\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_tim.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief TIM HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Timer (TIM) peripheral:\r
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
\r
if(htim->State == HAL_TIM_STATE_RESET)\r
- { \r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
HAL_TIM_OC_MspInit(htim);\r
}\r
\r
if(htim->State == HAL_TIM_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
HAL_TIM_PWM_MspInit(htim);\r
}\r
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); \r
\r
if(htim->State == HAL_TIM_STATE_RESET)\r
- { \r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
HAL_TIM_IC_MspInit(htim);\r
}\r
assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r
\r
if(htim->State == HAL_TIM_STATE_RESET)\r
- { \r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
HAL_TIM_OnePulse_MspInit(htim);\r
}\r
\r
if(htim->State == HAL_TIM_STATE_RESET)\r
{ \r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
HAL_TIM_Encoder_MspInit(htim);\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_tim_ex.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief TIM HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Timer extension peripheral:\r
* @{\r
*/\r
\r
-/** @defgroup TIMEx TIM Extended HAL module driver\r
+/** @defgroup TIMEx TIMEx\r
* @brief TIM Extended HAL module driver\r
* @{\r
*/\r
*/\r
/* Private functions ---------------------------------------------------------*/\r
\r
-/** @defgroup TIMEx_Private_Functions\r
+/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions\r
* @{\r
*/\r
\r
* @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.\r
* @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
* the configuration information for TIM module.\r
- * @param TIM_Remap: specifies the TIM input remapping source.\r
+ * @param Remap: specifies the TIM input remapping source.\r
* This parameter can be one of the following values:\r
* @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)\r
* @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.\r
******************************************************************************\r
* @file stm32f7xx_hal_uart.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief UART HAL module driver.\r
*\r
* This file provides firmware functions to manage the following \r
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
static void UART_DMAError(DMA_HandleTypeDef *hdma); \r
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);\r
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);\r
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);\r
/* Private functions ---------------------------------------------------------*/\r
\r
-/** @defgroup UART_Private_Functions\r
+/** @defgroup UART_Exported_Functions UART Exported Functions\r
* @{\r
*/\r
\r
-/** @defgroup HAL_UART_Group1 Initialization/de-initialization functions \r
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions \r
* @brief Initialization and Configuration functions \r
*\r
@verbatim \r
\r
if(huart->State == HAL_UART_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware : GPIO, CLOCK */\r
HAL_UART_MspInit(huart);\r
}\r
assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));\r
\r
if(huart->State == HAL_UART_STATE_RESET)\r
- { \r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware : GPIO, CLOCK */\r
HAL_UART_MspInit(huart);\r
}\r
assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\r
\r
if(huart->State == HAL_UART_STATE_RESET)\r
- { \r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED; \r
/* Init the low level hardware : GPIO, CLOCK */\r
HAL_UART_MspInit(huart);\r
}\r
* @}\r
*/\r
\r
-/** @defgroup HAL_UART_Group2 IO operation functions \r
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions \r
* @brief UART Transmit/Receive functions \r
*\r
@verbatim \r
UART_Transmit_IT(huart);\r
}\r
\r
+ /* UART in mode Transmitter (transmission end) -----------------------------*/\r
+ if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))\r
+ {\r
+ UART_EndTransmit_IT(huart);\r
+ }\r
+ \r
}\r
\r
\r
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);\r
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);\r
\r
- huart->State= HAL_UART_STATE_TIMEOUT;\r
+ huart->State= HAL_UART_STATE_READY;\r
\r
/* Process Unlocked */\r
__HAL_UNLOCK(huart);\r
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);\r
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);\r
\r
- huart->State= HAL_UART_STATE_TIMEOUT;\r
+ huart->State= HAL_UART_STATE_READY;\r
\r
/* Process Unlocked */\r
__HAL_UNLOCK(huart);\r
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) \r
{\r
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
- huart->TxXferCount = 0;\r
- \r
- /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
- in the UART CR3 register */\r
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);\r
\r
- /* Wait for UART TC Flag */\r
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TXDMA_TIMEOUTVALUE) != HAL_OK)\r
+ /* DMA Normal mode*/\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
{\r
- /* Timeout Occured */ \r
- huart->State = HAL_UART_STATE_TIMEOUT;\r
- HAL_UART_ErrorCallback(huart);\r
+ huart->TxXferCount = 0;\r
+\r
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the UART CR3 register */\r
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);\r
}\r
+ /* DMA Circular mode */\r
else\r
{\r
- /* No Timeout */\r
- /* Check if a receive process is ongoing or not */\r
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)\r
- {\r
- huart->State = HAL_UART_STATE_BUSY_RX;\r
- }\r
- else\r
- {\r
- huart->State = HAL_UART_STATE_READY;\r
- }\r
HAL_UART_TxCpltCallback(huart);\r
}\r
}\r
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) \r
{\r
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
- huart->RxXferCount = 0;\r
- \r
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit \r
- in the UART CR3 register */\r
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);\r
\r
- /* Check if a transmit Process is ongoing or not */\r
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX) \r
- {\r
- huart->State = HAL_UART_STATE_BUSY_TX;\r
- }\r
- else\r
- {\r
- huart->State = HAL_UART_STATE_READY;\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ { \r
+ huart->RxXferCount = 0;\r
+ \r
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit \r
+ in the UART CR3 register */\r
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);\r
+ \r
+ /* Check if a transmit Process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
}\r
HAL_UART_RxCpltCallback(huart);\r
}\r
}\r
}\r
\r
+/**\r
+ * @brief Wrap up transmission in non-blocking mode.\r
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable the UART Transmit Complete Interrupt */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);\r
+\r
+ /* Check if a receive process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)\r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);\r
+\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+\r
+ HAL_UART_TxCpltCallback(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
/**\r
* @brief Receive an amount of data in interrupt mode \r
* Function called under interruption only, once\r
* @}\r
*/\r
\r
-/** @defgroup HAL_UART_Group3 Peripheral Control functions \r
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions \r
* @brief UART control functions \r
*\r
@verbatim \r
/* Wait until TEACK flag is set */\r
if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) \r
{\r
- /* Timeout Occured */\r
+ /* Timeout Occurred */\r
return HAL_TIMEOUT;\r
}\r
}\r
/* Wait until REACK flag is set */\r
if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) \r
{ \r
- /* Timeout Occured */\r
+ /* Timeout Occurred */\r
return HAL_TIMEOUT;\r
}\r
}\r
******************************************************************************\r
* @file stm32f7xx_hal_usart.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief USART HAL module driver.\r
*\r
* This file provides firmware functions to manage the following \r
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);\r
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);\r
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);\r
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);\r
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);\r
/**\r
\r
if(husart->State == HAL_USART_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ husart->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware : GPIO, CLOCK */\r
HAL_USART_MspInit(husart);\r
}\r
}\r
}\r
\r
+ /* USART in mode Transmitter (transmission end) -----------------------------*/\r
+ if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET))\r
+ {\r
+ USART_EndTransmit_IT(husart);\r
+ }\r
+ \r
}\r
\r
/**\r
/* Disable the USART Transmit Complete Interrupt */\r
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r
\r
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
-\r
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- husart->State = HAL_USART_STATE_READY;\r
-\r
- HAL_USART_TxCpltCallback(husart);\r
+ /* Enable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r
\r
return HAL_OK;\r
}\r
}\r
}\r
\r
+/**\r
+ * @brief Wraps up transmission in non-blocking mode.\r
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified USART module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)\r
+{\r
+ /* Disable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_TxCpltCallback(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
/**\r
* @brief Simplex Receive an amount of data in non-blocking mode.\r
* Function called under interruption only, once\r
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);\r
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
\r
- husart->State= HAL_USART_STATE_TIMEOUT;\r
+ husart->State= HAL_USART_STATE_READY;\r
\r
/* Process Unlocked */\r
__HAL_UNLOCK(husart);\r
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);\r
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
\r
- husart->State= HAL_USART_STATE_TIMEOUT;\r
+ husart->State= HAL_USART_STATE_READY;\r
\r
/* Process Unlocked */\r
__HAL_UNLOCK(husart);\r
{\r
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
\r
- husart->TxXferCount = 0;\r
- \r
- if(husart->State == HAL_USART_STATE_BUSY_TX)\r
- {\r
- /* Wait for USART TC Flag */\r
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TXDMA_TIMEOUTVALUE) != HAL_OK)\r
- {\r
- /* Timeout occurred */ \r
- husart->State = HAL_USART_STATE_TIMEOUT;\r
- HAL_USART_ErrorCallback(husart);\r
- }\r
- else\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ { \r
+ husart->TxXferCount = 0;\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
{\r
- /* No Timeout */\r
- /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
- in the USART CR3 register */\r
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit\r
+ in the USART CR3 register */\r
husart->Instance->CR3 &= ~(USART_CR3_DMAT);\r
- husart->State= HAL_USART_STATE_READY;\r
+\r
+ /* Enable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r
}\r
}\r
- /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/\r
+ /* DMA Circular mode */\r
else\r
{\r
- husart->State= HAL_USART_STATE_BUSY_RX;\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
HAL_USART_TxCpltCallback(husart);\r
- }\r
+ }\r
+ }\r
}\r
\r
\r
{\r
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
\r
- husart->RxXferCount = 0;\r
-\r
- /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit\r
- in USART CR3 register */\r
- husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);\r
- /* similarly, disable the DMA TX transfer that was started to provide the\r
- clock to the slave device */\r
- husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ { \r
+ husart->RxXferCount = 0;\r
\r
- husart->State= HAL_USART_STATE_READY;\r
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit\r
+ in USART CR3 register */\r
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);\r
+ /* similarly, disable the DMA TX transfer that was started to provide the\r
+ clock to the slave device */\r
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);\r
\r
- HAL_USART_RxCpltCallback(husart);\r
+ if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ HAL_USART_RxCpltCallback(husart);\r
+ }\r
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r
+ else\r
+ {\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+ }\r
+ husart->State= HAL_USART_STATE_READY;\r
+ }\r
+ /* DMA circular mode */\r
+ else\r
+ {\r
+ if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ HAL_USART_RxCpltCallback(husart);\r
+ }\r
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r
+ else\r
+ {\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+ }\r
+ }\r
}\r
\r
/**\r
uint32_t tmpreg = 0x0;\r
USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;\r
HAL_StatusTypeDef ret = HAL_OK;\r
+ uint16_t brrtemp = 0x0000;\r
+ uint16_t usartdiv = 0x0000;\r
\r
/* Check the parameters */\r
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));\r
USART_GETCLOCKSOURCE(husart, clocksource);\r
switch (clocksource)\r
{\r
- case USART_CLOCKSOURCE_PCLK1: \r
- husart->Instance->BRR = (uint16_t)(2*HAL_RCC_GetPCLK1Freq() / husart->Init.BaudRate);\r
- break;\r
- case USART_CLOCKSOURCE_PCLK2: \r
- husart->Instance->BRR = (uint16_t)(2*HAL_RCC_GetPCLK2Freq() / husart->Init.BaudRate);\r
- break;\r
- case USART_CLOCKSOURCE_HSI: \r
- husart->Instance->BRR = (uint16_t)(2*HSI_VALUE / husart->Init.BaudRate); \r
- break; \r
- case USART_CLOCKSOURCE_SYSCLK: \r
- husart->Instance->BRR = (uint16_t)(2*HAL_RCC_GetSysClockFreq() / husart->Init.BaudRate);\r
- break; \r
- case USART_CLOCKSOURCE_LSE: \r
- husart->Instance->BRR = (uint16_t)(2*LSE_VALUE / husart->Init.BaudRate); \r
- break;\r
- case USART_CLOCKSOURCE_UNDEFINED: \r
- default:\r
- ret = HAL_ERROR; \r
- break; \r
+ case USART_CLOCKSOURCE_PCLK1:\r
+ usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_PCLK2:\r
+ usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK2Freq()) / husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_HSI:\r
+ usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_SYSCLK:\r
+ usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_LSE:\r
+ usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_UNDEFINED:\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
} \r
\r
+ brrtemp = usartdiv & 0xFFF0;\r
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);\r
+ husart->Instance->BRR = brrtemp;\r
+ \r
return ret; \r
}\r
\r
******************************************************************************\r
* @file stm32f7xx_hal_wwdg.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief WWDG HAL module driver.\r
* This file provides firmware functions to manage the following \r
* functionalities of the Window Watchdog (WWDG) peripheral:\r
\r
if(hwwdg->State == HAL_WWDG_STATE_RESET)\r
{\r
+ /* Allocate lock resource and initialize it */\r
+ hwwdg->Lock = HAL_UNLOCKED;\r
/* Init the low level hardware */\r
HAL_WWDG_MspInit(hwwdg);\r
}\r
******************************************************************************\r
* @file stm32f7xx_ll_fmc.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief FMC Low Layer HAL module driver.\r
* \r
* This file provides firmware functions to manage the following \r
******************************************************************************\r
* @file stm32f7xx_ll_sdmmc.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief SDMMC Low Layer HAL module driver.\r
* \r
* This file provides firmware functions to manage the following \r
******************************************************************************\r
* @file stm32f7xx_ll_usb.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 12-May-2015\r
* @brief USB Low Layer HAL module driver.\r
* \r
* This file provides firmware functions to manage the following \r
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************\r
;* File Name : startup_stm32f756xx.s\r
;* Author : MCD Application Team\r
-;* Version : V1.0.0RC1\r
-;* Date : 24-March-2015\r
+;* Version : V1.0.0
+;* Date : 22-May-2015\r
;* Description : STM32F756xx devices vector table for EWARM toolchain.\r
;* This module performs:\r
;* - Set the initial SP\r
/*-Specials-*/\r
define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
/*-Memory Regions-*/\r
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;\r
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;\r
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;\r
-define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF;\r
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;\r
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF;\r
/*-Sizes-*/\r
define symbol __ICFEDIT_size_cstack__ = 0x400;\r
define symbol __ICFEDIT_size_heap__ = 0x200;\r
define memory mem with size = 4G;\r
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];\r
\r
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
\r
-initialize by copy { readwrite };\r
+initialize by copy { readwrite, section .itcmram };\r
do not initialize { section .noinit };\r
\r
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
\r
place in ROM_region { readonly };\r
place in RAM_region { readwrite,\r
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };\r
+place in ITCMRAM_region { section .itcmram };
\ No newline at end of file
/**\r
******************************************************************************\r
- * @file stm32f7xx_hal_msp_template.c\r
+ * @file stm32f7xx_hal_msp.c\r
* @author MCD Application Team\r
- * @version V0.0.1\r
- * @date 21-October-2014\r
+ * @version V1.0.0\r
+ * @date 22-May-2015\r
* @brief HAL MSP module.\r
* This file template is located in the HAL folder and should be copied \r
* to the user folder.\r
##### How to use this driver #####\r
===============================================================================\r
[..]\r
- This file is generated automatically by MicroXplorer and eventually modified \r
+ This file is generated automatically by STM32CubeMX and eventually modified \r
by the user\r
\r
@endverbatim\r
******************************************************************************\r
* @attention\r
*\r
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
*\r
* Redistribution and use in source and binary forms, with or without modification,\r
* are permitted provided that the following conditions are met:\r
*/\r
void HAL_MspInit(void)\r
{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually \r
modified by the user\r
*/ \r
}\r
*/\r
void HAL_MspDeInit(void)\r
{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
- modified by the user\r
- */\r
-}\r
-\r
-/**\r
- * @brief Initializes the PPP MSP.\r
- * @param None\r
- * @retval None\r
- */\r
-void HAL_PPP_MspInit(void)\r
-{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
- modified by the user\r
- */ \r
-}\r
-\r
-/**\r
- * @brief DeInitializes the PPP MSP.\r
- * @param None \r
- * @retval None\r
- */\r
-void HAL_PPP_MspDeInit(void)\r
-{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually \r
modified by the user\r
*/\r
}\r
******************************************************************************\r
* @file system_stm32f7xx.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 28-April-2015\r
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.\r
*\r
* This file provides two functions and one global variable to be called from \r
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************\r
;* File Name : startup_stm32f756xx.s\r
;* Author : MCD Application Team\r
-;* Version : V1.0.0RC1\r
-;* Date : 24-March-2015\r
+;* Version : V1.0.0
+;* Date : 22-May-2015\r
;* Description : STM32F756xx devices vector table for MDK-ARM toolchain. \r
;* This module performs:\r
;* - Set the initial SP\r
;* <<< Use Configuration Wizard in Context Menu >>> \r
;*******************************************************************************\r
; \r
-;* Redistribution and use in source and binary forms, with or without modification,\r
+;* Redistribution and use in so urce and binary forms, with or without modification,\r
;* are permitted provided that the following conditions are met:\r
;* 1. Redistributions of source code must retain the above copyright notice,\r
;* this list of conditions and the following disclaimer.\r
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
; </h>\r
\r
-Stack_Size EQU 0x00000400\r
+Stack_Size EQU 0x400;\r
\r
AREA STACK, NOINIT, READWRITE, ALIGN=3\r
Stack_Mem SPACE Stack_Size\r
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
; </h>\r
\r
-Heap_Size EQU 0x00000200\r
+Heap_Size EQU 0x200;\r
\r
AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
__heap_base\r
/**\r
******************************************************************************\r
- * @file stm32f7xx_hal_msp_template.c\r
+ * @file stm32f7xx_hal_msp.c\r
* @author MCD Application Team\r
- * @version V0.0.1\r
- * @date 21-October-2014\r
+ * @version V1.0.0\r
+ * @date 22-May-2015\r
* @brief HAL MSP module.\r
* This file template is located in the HAL folder and should be copied \r
* to the user folder.\r
##### How to use this driver #####\r
===============================================================================\r
[..]\r
- This file is generated automatically by MicroXplorer and eventually modified \r
+ This file is generated automatically by STM32CubeMX and eventually modified \r
by the user\r
\r
@endverbatim\r
******************************************************************************\r
* @attention\r
*\r
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
*\r
* Redistribution and use in source and binary forms, with or without modification,\r
* are permitted provided that the following conditions are met:\r
*/\r
void HAL_MspInit(void)\r
{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually \r
modified by the user\r
*/ \r
}\r
*/\r
void HAL_MspDeInit(void)\r
{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
- modified by the user\r
- */\r
-}\r
-\r
-/**\r
- * @brief Initializes the PPP MSP.\r
- * @param None\r
- * @retval None\r
- */\r
-void HAL_PPP_MspInit(void)\r
-{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
- modified by the user\r
- */ \r
-}\r
-\r
-/**\r
- * @brief DeInitializes the PPP MSP.\r
- * @param None \r
- * @retval None\r
- */\r
-void HAL_PPP_MspDeInit(void)\r
-{\r
- /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually \r
modified by the user\r
*/\r
}\r
/**\r
******************************************************************************\r
- * @file system_stm32f7xx.c\r
+ * @file Templates/system_stm32f7xx.c\r
* @author MCD Application Team\r
- * @version V1.0.0RC1\r
- * @date 24-March-2015\r
+ * @version V1.0.0\r
+ * @date 22-May-2015\r
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.\r
*\r
* This file provides two functions and one global variable to be called from \r
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