This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
config TARGET_MPC8266ADS
bool "Support MPC8266ADS"
-config TARGET_VOVPN_GW
- bool "Support VoVPN-GW"
-
config TARGET_KM82XX
bool "Support km82xx"
source "board/cpu87/Kconfig"
source "board/ep82xxm/Kconfig"
source "board/freescale/mpc8266ads/Kconfig"
-source "board/funkwerk/vovpn-gw/Kconfig"
source "board/gw8260/Kconfig"
source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
+++ /dev/null
-if TARGET_VOVPN_GW
-
-config SYS_BOARD
- default "vovpn-gw"
-
-config SYS_VENDOR
- default "funkwerk"
-
-config SYS_CONFIG_NAME
- default "VoVPN-GW"
-
-endif
+++ /dev/null
-VOVPN-GW BOARD
-#M: -
-S: Maintained
-F: board/funkwerk/vovpn-gw/
-F: include/configs/VoVPN-GW.h
-F: configs/VoVPN-GW_66MHz_defconfig
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := vovpn-gw.o flash.o m88e6060.o
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- * ------------------------------------------
- * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3
- * and 28F128J3A flashs working in 8 Bit mode.
- *
- * Most of this code is taken from existing u-boot source code.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_READ_STATUS 0x70
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xd0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_SUSPEND_ERASE 0xb0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_WRITE_BUFF 0xe8
-#define FLASH_CMD_PROG_RESUME 0xd0
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xd0
-#define FLASH_STATUS_DONE 0x80
-
-#define FLASH_WRITE_BUFFER_SIZE 32
-
-#ifdef CONFIG_SYS_FLASH_16BIT
-#define FLASH_WORD_SIZE unsigned short
-#define FLASH_ID_MASK 0xffff
-#define FLASH_CMD_ADDR_SHIFT 0
-#else
-#define FLASH_WORD_SIZE unsigned char
-#define FLASH_ID_MASK 0xff
-/* A0 is not used in either 8x or 16x for READ ID */
-#define FLASH_CMD_ADDR_SHIFT 1
-#endif
-
-
-static unsigned long
-flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
-{
- volatile FLASH_WORD_SIZE *p;
- FLASH_WORD_SIZE value;
- int i;
-
- addr[0] = FLASH_CMD_READ_ID;
-
- /* manufactor */
- value = addr[0 << FLASH_CMD_ADDR_SHIFT];
- switch (value) {
- case (INTEL_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- *addr = FLASH_CMD_RESET;
- return (0);
-
- }
-
- /* device */
- value = addr[1 << FLASH_CMD_ADDR_SHIFT];
- switch (value) {
- case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break;
- case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break;
- case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- *addr = FLASH_CMD_RESET;
- return (0);
- }
-
- /* setup sectors */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count);
- }
-
- /* check protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- p = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1;
- }
-
- /* reset bank */
- *addr = FLASH_CMD_RESET;
- return (info->size);
-}
-
-unsigned long
-flash_init(void)
-{
- unsigned long size;
- int i;
-
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
- size = flash_get((volatile FLASH_WORD_SIZE *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH Size=0x%08lx\n", size);
- return (0);
- }
-
- /* always protect 1 sector containing the HRCW */
- flash_protect(FLAG_PROTECT_SET,
- flash_info[0].start[0],
- flash_info[0].start[1] - 1,
- &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_FLASH,
- CONFIG_SYS_MONITOR_FLASH+CONFIG_SYS_MONITOR_LEN-1,
- &flash_info[0]);
-#endif
-#ifdef CONFIG_ENV_IS_IN_FLASH
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return (size);
-}
-
-void
-flash_print_info(flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A: printf ("28F320JA3 (32 Mbit)\n");
- break;
- case FLASH_28F640J3A: printf ("28F640JA3 (64 Mbit)\n");
- break;
- case FLASH_28F128J3A: printf ("28F128JA3 (128 Mbit)\n");
- break;
- default: printf ("Unknown Chip Type");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-int
-flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- unsigned long start, now, last;
- int flag, prot, sect;
- volatile FLASH_WORD_SIZE *addr;
- FLASH_WORD_SIZE status;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return (1);
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Cannot erase unknown flash - aborted\n");
- return (1);
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
-
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect]) {
- continue;
- }
-
- addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
-#ifdef DEBUG
- printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
-#endif
-
- *addr = FLASH_CMD_CLEAR_STATUS;
- *addr = FLASH_CMD_BLOCK_ERASE;
- *addr = FLASH_CMD_ERASE_CONFIRM;
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Flash erase timeout at address %lx\n", info->start[sect]);
- *addr = FLASH_CMD_SUSPEND_ERASE;
- *addr = FLASH_CMD_RESET;
- return (1);
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- *addr = FLASH_CMD_RESET;
- }
- printf (" done\n");
- return (0);
-}
-
-static int
-write_buff2( volatile FLASH_WORD_SIZE *dst,
- volatile FLASH_WORD_SIZE *src,
- unsigned long cnt )
-{
- unsigned long start;
- FLASH_WORD_SIZE status;
- int flag, i;
-
- start = get_timer (0);
- while (1) {
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
- dst[0] = FLASH_CMD_WRITE_BUFF;
- if ((status = *dst) & FLASH_STATUS_DONE) {
- break;
- }
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (-1);
- }
- }
- dst[0] = (FLASH_WORD_SIZE)(cnt - 1);
- for (i=0; i<cnt; i++) {
- dst[i] = src[i];
- }
- dst[0] = FLASH_CMD_PROG_RESUME;
-
- if (flag) {
- enable_interrupts();
- }
-
- return( 0 );
-}
-
-static int
-poll_status( volatile FLASH_WORD_SIZE *addr )
-{
- unsigned long start;
-
- start = get_timer (0);
- /* wait for error or finish */
- while (1) {
- if (*addr == FLASH_STATUS_DONE) {
- if (*addr == FLASH_STATUS_DONE) {
- break;
- }
- }
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = FLASH_CMD_RESET;
- return (-1);
- }
- }
- *addr = FLASH_CMD_RESET;
- return (0);
-}
-
-/*
- * write_buff return values:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-int
-write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt)
-{
- volatile FLASH_WORD_SIZE *addr, *dst;
- unsigned long bcnt;
- int flag, i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return (4);
- }
-
- addr = (volatile FLASH_WORD_SIZE *)(info->start[0]);
- dst = (volatile FLASH_WORD_SIZE *) udst;
-
-#ifdef CONFIG_SYS_FLASH_16BIT
-#error NYI
-#else
- while (cnt > 0) {
- /* Check if buffer write is possible */
- if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) {
- bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt;
- /* Check if Flash is (sufficiently) erased */
- for (i=0; i<bcnt; i++) {
- if ((dst[i] & src[i]) != src[i]) {
- return (2);
- }
- }
- if (write_buff2( dst,src,bcnt ) != 0) {
- addr[0] = FLASH_CMD_READ_STATUS;
- }
- if (poll_status( dst ) != 0) {
- return (1);
- }
- cnt -= bcnt;
- dst += bcnt;
- src += bcnt;
- continue;
- }
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dst & *src) != *src) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
- addr[0] = FLASH_CMD_ERASE_CONFIRM;
- addr[0] = FLASH_CMD_WRITE;
- *dst++ = *src++;
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- if (poll_status( dst ) != 0) {
- return (1);
- }
- cnt --;
- }
-#endif
- return (0);
-}
-
-int
-flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- volatile FLASH_WORD_SIZE *addr;
- unsigned long start;
-
- addr = (volatile FLASH_WORD_SIZE *)(info->start[sector]);
- *addr = FLASH_CMD_CLEAR_STATUS;
- *addr = FLASH_CMD_PROTECT;
-
- if(prot) {
- *addr = FLASH_CMD_PROTECT_SET;
- } else {
- *addr = FLASH_CMD_PROTECT_CLEAR;
- }
-
- /* wait for error or finish */
- start = get_timer (0);
- while(!(addr[0] & FLASH_STATUS_DONE)){
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Flash protect timeout at address %lx\n", info->start[sector]);
- addr[0] = FLASH_CMD_RESET;
- return (1);
- }
- }
-
- /* Set software protect flag */
- info->protect[sector] = prot;
- *addr = FLASH_CMD_RESET;
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- * ------------------------------------------
- * Initialize Marvell M88E6060 Switch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <net.h>
-#include <miiphy.h>
-
-#include "m88e6060.h"
-
-#if defined(CONFIG_CMD_NET)
-static int prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 };
-static int phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 };
-
-static m88x_regCfg_t prtCfg0[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x001e },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t prtCfg1[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x001d },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t prtCfg2[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x001b },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t prtCfg3[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x0017 },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t prtCfg4[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x000f },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t *prtCfg[M88X_PRT_CNT] = {
- prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL
-};
-
-static m88x_regCfg_t phyCfgX[] = {
- { 4, 0xfa1f, 0x01e0 },
- { 0, 0x213f, 0x1200 },
- { 24, 0x81ff, 0x1200 },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t *phyCfg[M88X_PHY_CNT] = {
- phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL
-};
-
-#if 0
-static void
-m88e6060_dump( int devAddr )
-{
- int i, j;
- unsigned short val[6];
-
- printf( "M88E6060 Register Dump\n" );
- printf( "====================================\n" );
- printf( "PortNo 0 1 2 3 4 5\n" );
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] );
- printf( "STAT %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] );
- printf( "ID %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] );
- printf( "CNTL %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] );
- printf( "VLAN %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] );
- printf( "PAV %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] );
- printf( "RX %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] );
- printf( "TX %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- printf( "------------------------------------\n" );
- printf( "PhyNo 0 1 2 3 4\n" );
- for (i=0; i<9; i++) {
- for (j=0; j<5; j++) {
- miiphy_read( devAddr+phyTab[j],i,&val[j] );
- }
- printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n",
- i,val[0],val[1],val[2],val[3],val[4] );
- }
- for (i=0x10; i<0x1d; i++) {
- for (j=0; j<5; j++) {
- miiphy_read( devAddr+phyTab[j],i,&val[j] );
- }
- printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n",
- i,val[0],val[1],val[2],val[3],val[4] );
- }
-}
-#endif
-
-int
-m88e6060_initialize( int devAddr )
-{
- static char *_f = "m88e6060_initialize:";
- m88x_regCfg_t *p;
- int err;
- int i;
- unsigned short val;
-
- /*** reset all phys into powerdown ************************************/
- for (i=0, err=0; i<M88X_PHY_CNT; i++) {
- err += bb_miiphy_read(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,&val );
- /* keep SpeedLSB, Duplex */
- val &= 0x2100;
- /* set SWReset, AnegEn, PwrDwn, RestartAneg */
- val |= 0x9a00;
- err += bb_miiphy_write(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,val );
- }
- if (err) {
- printf( "%s [ERR] reset phys\n",_f );
- return( -1 );
- }
-
- /*** disable all ports ************************************************/
- for (i=0, err=0; i<M88X_PRT_CNT; i++) {
- err += bb_miiphy_read(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,&val );
- val &= 0xfffc;
- err += bb_miiphy_write(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,val );
- }
- if (err) {
- printf( "%s [ERR] disable ports\n",_f );
- return( -1 );
- }
-
- /*** initialize switch ************************************************/
- /* set switch mac addr */
-#define ea eth_get_dev()->enetaddr
- val = (ea[4] << 8) | ea[5];
- err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val );
- val = (ea[2] << 8) | ea[3];
- err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val );
- val = (ea[0] << 8) | ea[1];
-#undef ea
- val &= 0xfeff; /* clear DiffAddr */
- err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val );
- if (err) {
- printf( "%s [ERR] switch mac address register\n",_f );
- return( -1 );
- }
-
- /* !DiscardExcessive, MaxFrameSize, CtrMode */
- err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val );
- val &= 0xd870;
- val |= 0x0500;
- err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val );
- if (err) {
- printf( "%s [ERR] switch global control register\n",_f );
- return( -1 );
- }
-
- /* LernDis off, ATUSize 1024, AgeTime 5min */
- err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val );
- val &= 0x000f;
- val |= 0x2130;
- err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val );
- if (err) {
- printf( "%s [ERR] atu control register\n",_f );
- return( -1 );
- }
-
- /*** initialize ports *************************************************/
- for (i=0; i<M88X_PRT_CNT; i++) {
- if ((p = prtCfg[i]) == NULL) {
- continue;
- }
- while (p->reg != -1) {
- err = 0;
- err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val );
- val &= p->msk;
- val |= p->val;
- err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val );
- if (err) {
- printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
- /* XXX what todo */
- }
- p++;
- }
- }
-
- /*** initialize phys **************************************************/
- for (i=0; i<M88X_PHY_CNT; i++) {
- if ((p = phyCfg[i]) == NULL) {
- continue;
- }
- while (p->reg != -1) {
- err = 0;
- err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val );
- val &= p->msk;
- val |= p->val;
- err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val );
- if (err) {
- printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
- /* XXX what todo */
- }
- p++;
- }
- }
- udelay(100000);
- return( 0 );
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- * ------------------------------------------
- * Initialize Marvell M88E6060 Switch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _INC_m88e6060_h_
-#define _INC_m88e6060_h_
-
-/* ************************************************************************** */
-/* *** DEFINES ************************************************************** */
-
-/* switch hw */
-#define M88X_PRT_CNT 6
-#define M88X_PHY_CNT 5
-
-/* phy register offsets */
-#define M88X_PHY_CNTL 0x00
-#define M88X_PHY_STAT 0x00
-#define M88X_PHY_ID0 0x02
-#define M88X_PHY_ID1 0x03
-#define M88X_PHY_ANEG_ADV 0x04
-#define M88X_PHY_LPA 0x05
-#define M88X_PHY_ANEG_EXP 0x06
-#define M88X_PHY_NPT 0x07
-#define M88X_PHY_LPNP 0x08
-
-/* port register offsets */
-#define M88X_PRT_STAT 0x00
-#define M88X_PRT_ID 0x03
-#define M88X_PRT_CNTL 0x04
-#define M88X_PRT_VLAN 0x06
-#define M88X_PRT_PAV 0x0b
-#define M88X_PRT_RX 0x10
-#define M88X_PRT_TX 0x11
-
-/* global/atu register offsets */
-#define M88X_GLB_STAT 0x00
-#define M88X_GLB_MAC01 0x01
-#define M88X_GLB_MAC23 0x02
-#define M88X_GLB_MAC45 0x03
-#define M88X_GLB_CNTL 0x04
-#define M88X_ATU_CNTL 0x0a
-#define M88X_ATU_OP 0x0b
-
-/* id0 register - 0x02 */
-#define M88X_PHY_ID0_VALUE 0x0141
-
-/* id1 register - 0x03 */
-#define M88X_PHY_ID1_VALUE 0x0c80 /* without revision ! */
-
-
-/* misc */
-#define M88E6060_ID ((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE)
-
-/* ************************************************************************** */
-/* *** TYPEDEFS ************************************************************* */
-
-typedef struct {
- int reg;
- unsigned short msk;
- unsigned short val;
-} m88x_regCfg_t;
-
-/* ************************************************************************** */
-/* *** PROTOTYPES *********************************************************** */
-
-extern int m88e6060_initialize( int );
-
-#endif /* _INC_m88e6060_h_ */
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <miiphy.h>
-#include <linux/compiler.h>
-
-#include "m88e6060.h"
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */
- /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */
- /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */
- /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */
- /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */
- /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */
- /* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */
- /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */
- /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */
- /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */
- /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */
- /* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */
- /* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */
- /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */
- /* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */
- /* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */
- /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */
- /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */
- /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */
- /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */
- /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */
- /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */
- /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */
- /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */
- /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */
- /* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */
- /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */
- /* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */
- /* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */
- /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */
- /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */
- /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */
- /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */
- /* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */
- /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */
- /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */
- /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */
- /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */
- /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */
- /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */
- /* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */
- /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */
- /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */
- /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */
- /* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */
- /* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */
- /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
- /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */
- /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */
- /* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */
- /* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */
- /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */
- /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
- }
-};
-
-void reset_phy (void)
-{
- volatile ioport_t *iop;
-#if defined(CONFIG_CMD_NET)
- int i;
- unsigned short val;
-#endif
-
- iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
-
- /* Reset the PHY */
- iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */
-#if defined(CONFIG_CMD_NET)
- udelay(20000);
- iop->pdat |= 0x00080000;
- for (i=0; i<100; i++) {
- udelay(20000);
- if (bb_miiphy_read("FCC1", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) {
- break;
- }
- }
- /* initialize switch */
- m88e6060_initialize( CONFIG_SYS_PHY_ADDR );
-#endif
-}
-
-static unsigned long UPMATable[] = {
- 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
- 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */
- 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
- 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
- 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
- 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
- 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
- 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */
-};
-
-int board_early_init_f (void)
-{
- volatile immap_t *immap;
- volatile memctl8260_t *memctl;
- volatile unsigned char *dummy;
- int i;
-
- immap = (immap_t *) CONFIG_SYS_IMMR;
- memctl = &immap->im_memctl;
-
-#if 0
- /* CS2-5 - DSP via UPMA */
- dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
- memctl->memc_mar = 0;
- memctl->memc_mamr = MxMR_OP_WARR;
- for (i = 0; i < 64; i++) {
- memctl->memc_mdr = UPMATable[i];
- *dummy = 0;
- }
- memctl->memc_mamr = 0x00044440;
-#else
- /* CS7 - DPRAM via UPMA */
- dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
- memctl->memc_mar = 0;
- memctl->memc_mamr = MxMR_OP_WARR;
- for (i = 0; i < 64; i++) {
- memctl->memc_mdr = UPMATable[i];
- *dummy = 0;
- }
- memctl->memc_mamr = 0x00044440;
-#endif
- return 0;
-}
-
-int misc_init_r (void)
-{
- volatile ioport_t *iop;
- __maybe_unused unsigned char temp;
-#if 0
- /* DUMP UPMA RAM */
- volatile immap_t *immap;
- volatile memctl8260_t *memctl;
- volatile unsigned char *dummy;
- unsigned char c;
- int i;
-
- immap = (immap_t *) CONFIG_SYS_IMMR;
- memctl = &immap->im_memctl;
-
-
- dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
- memctl->memc_mar = 0;
- memctl->memc_mamr = MxMR_OP_RARR;
- for (i = 0; i < 64; i++) {
- c = *dummy;
- printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
- memctl->memc_mamr,
- memctl->memc_mar,
- memctl->memc_mdr );
- }
- memctl->memc_mamr = 0x00044440;
-#endif
- /* enable buffers (DSP, DPRAM) */
- iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
- iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */
-
- /* destroy DPRAM magic */
- *(volatile unsigned char *)0xf0500000 = 0x00;
-
- /* clear any pending DPRAM irq */
- temp = *(volatile unsigned char *)0xf05003ff;
-
- /* write module-id into DPRAM */
- *(volatile unsigned char *)0xf0500201 = 0x50;
-
- return 0;
-}
-
-#if defined(CONFIG_HAVE_OWN_RESET)
-int
-do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- volatile ioport_t *iop;
-
- iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2);
- iop->pdat |= 0x00002000; /* PC18 = HW_RESET */
- return 1;
-}
-#endif /* CONFIG_HAVE_OWN_RESET */
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap;
- volatile memctl8260_t *memctl;
- volatile uchar *ramaddr;
- int i;
- uchar c;
-
- immap = (immap_t *) CONFIG_SYS_IMMR;
- memctl = &immap->im_memctl;
- ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
- c = 0xff;
-
- immap->im_siu_conf.sc_ppc_acr = 0x02;
- immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
- immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
- immap->im_siu_conf.sc_tescr1 = 0x00000000;
- immap->im_siu_conf.sc_tescr2 = 0x00000000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM;
-
- /* Precharge all banks */
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
- *ramaddr = c;
-
- /* CBR refresh */
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- /* Mode Register write */
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
- *ramaddr = c;
-
- /* Refresh enable */
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
- *ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return (CONFIG_SYS_SDRAM_SIZE);
-}
-
-int checkboard (void)
-{
-#ifdef CONFIG_CLKIN_66MHz
- puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
-#else
- puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
-#endif
- return 0;
-}
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_VOVPN_GW=y
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+VoVPN-GW powerpc mpc8260 - -
ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com>
ppmc8260 powerpc mpc8260 - - Brad Kemp <Brad.Kemp@seranoa.com>
sacsng powerpc mpc8260 - - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* define cpu used */
-#define CONFIG_MPC8272 1
-
-/* define busmode: 8260 */
-#undef CONFIG_BUSMODE_60x
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifdef CONFIG_CLKIN_66MHz
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_8260_CLKIN 100000000 /* in Hz */
-#endif
-
-/* call board_early_init_f */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-/* have misc_init_r() function */
-#define CONFIG_MISC_INIT_R 1
-
-/* have reset_phy_r() function */
-#define CONFIG_RESET_PHY_R 1
-
-/* have special reset function */
-#define CONFIG_HAVE_OWN_RESET 1
-
-/* allow serial and ethaddr to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/* watchdog disabled */
-#undef CONFIG_WATCHDOG
-
-/* include support for bzip2 compressed images */
-#undef CONFIG_BZIP2
-
-/* status led */
-#undef CONFIG_STATUS_LED /* XXX jse */
-
-/* vendor parameter protection */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC
-#undef CONFIG_CONS_ON_SCC
-#undef CONFIG_CONS_NONE
-#define CONFIG_CONS_INDEX 1
-
-/* serial port default baudrate */
-#define CONFIG_BAUDRATE 115200
-
-/* echo on for serial download */
-#define CONFIG_LOADS_ECHO 1
-
-/* don't allow baudrate change */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_ON_FCC
-#undef CONFIG_ETHER_NONE
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-/* which SCC/FCC channel for ethernet */
-#define CONFIG_ETHER_INDEX 1
-
-/* Marvell Switch SMI base addr */
-#define CONFIG_SYS_PHY_ADDR 0x10
-
-/* FCC1 RMII REFCLK is CLK10 */
-#define CONFIG_SYS_CMXFCR_VALUE CMXFCR_TF1CS_CLK10
-#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK)
-
-/* BDs and buffers on 60x bus */
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-
-/* Local Protect, Full duplex, Flowcontrol, RMII */
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\
- FCC_PSMR_FCE|FCC_PSMR_RMII)
-
-/* bit-bang MII PHY management */
-#define CONFIG_BITBANGMII
-
-#define MDIO_PORT 1 /* Port B */
-
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */
-#define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */
-#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDC_PIN
-#define MIIDELAY udelay(1)
-
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMLS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SOURCE
-
-
-/*
- * boot options & environment
- */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "run flash_self"
-#undef CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"clean_nv=erase fff20000 ffffffff\0" \
-"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
-"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
-"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
-"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
-"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
-"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
-"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
-"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
-"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
-"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
-"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
-"fstype=cramfs\0" \
-"rootpath=/root_fs\0" \
-"uboot=PPC/u-boot.bin\0" \
-"kernel=PPC/uImage\0" \
-"kernel_addr=ffe00000\0" \
-"fs=PPC/root_fs\0" \
-"console=ttyS0\0" \
-"netdev=eth0\0" \
-"rootdev=31:3\0" \
-"ethaddr=00:09:4f:01:02:03\0" \
-"ipaddr=10.0.0.201\0" \
-"netmask=255.255.255.0\0" \
-"serverip=10.0.0.136\0" \
-"gatewayip=10.0.0.10\0" \
-"hostname=bastard\0" \
-""
-
-
-/*
- * miscellaneous configurable options
- */
-
-/* undef to save memory */
-#define CONFIG_SYS_LONGHELP
-
-/* monitor command prompt */
-
-/* console i/o buffer size */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024
-#else
-#define CONFIG_SYS_CBSIZE 256
-#endif
-
-/* print buffer size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-
-/* boot argument buffer size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-/* 1 ... 15 MB in DRAM */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000
-/* full featured memtest */
-#define CONFIG_SYS_ALT_MEMTEST
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-/* decrementer freq: 1 ms ticks */
-
-/* configure flash */
-#define CONFIG_SYS_FLASH_BASE 0xff800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 64
-#define CONFIG_SYS_FLASH_SIZE 8
-#undef CONFIG_SYS_FLASH_16BIT
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-#define CONFIG_SYS_FLASH_LOCK_TOUT 500
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/* monitor in flash */
-#define CONFIG_SYS_MONITOR_OFFSET 0x00700000
-
-/* environment in flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00020000)
-#define CONFIG_ENV_SIZE 0x00020000
-#define CONFIG_ENV_SECT_SIZE 0x00020000
-
-/*
- * Initial memory map for linux
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-
-/* hard reset configuration words */
-#ifdef CONFIG_CLKIN_66MHz
-#define CONFIG_SYS_HRCW_MASTER 0x04643050
-#else
-#error NO HRCW FOR 100MHZ SPECIFIED !!!
-#endif
-#define CONFIG_SYS_HRCW_SLAVE1 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE2 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE3 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE4 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE5 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE6 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE7 0x00000000
-
-/* internal memory mapped register */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/* definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE (32*1024*1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_FLASH (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
-#define CONFIG_SYS_MONITOR_LEN 0x00020000
-#define CONFIG_SYS_MALLOC_LEN 0x00020000
-
-/* cache configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* for MPC8260 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of above */
-#endif
-
-/*
- * HIDx - Hardware Implementation-dependent Registers
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|\
- HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/* RMR - reset mode register - turn on checkstop reset enable */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/* BCR - bus configuration */
-#define CONFIG_SYS_BCR 0x00000000
-
-/* SIUMCR - siu module configuration */
-#define CONFIG_SYS_SIUMCR 0x4905c000
-
-/* SYPCR - system protection control */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR 0xffffff87
-#else
-#define CONFIG_SYS_SYPCR 0xffffff83
-#endif
-
-/* TMCNTSC - time counter status and control */
-/* clear interrupts XXX jse */
-/*#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\
- TMCNTSC_TCF|TMCNTSC_TCE)
-
-/* PISCR - periodic interrupt status and control */
-/* clear interrupts XXX jse */
-/*#define CONFIG_SYS_PISCR (PISCR_PS) */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/* SCCR - system clock control */
-#define CONFIG_SYS_SCCR 0x000001a9
-
-/* RCCR - risc controller configuration */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * MEMORY MAP
- * ----------
- * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
- * CS1 - SDRAM 32MB/64Bit base=0x00000000
- * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
- * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
- * CS4 - DSP/SL3 1MB/16Bit base=0xf0300000
- * CS5 - DSP/SL4 1MB/16Bit base=0xf0400000
- * CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored)
- * x - IMMR 384KB base=0xf0000000
- */
-/* XXX jse 100MHz TODO */
-#define CONFIG_SYS_BR0_PRELIM 0xff800801
-#define CONFIG_SYS_OR0_PRELIM 0xff801e44
-#define CONFIG_SYS_BR1_PRELIM 0x00000041
-#define CONFIG_SYS_OR1_PRELIM 0xfe002ec0
-#if 1
-#define CONFIG_SYS_BR2_PRELIM 0xf0101001
-#define CONFIG_SYS_OR2_PRELIM 0xfff00ef4
-#define CONFIG_SYS_BR3_PRELIM 0xf0201001
-#define CONFIG_SYS_OR3_PRELIM 0xfff00ef4
-#define CONFIG_SYS_BR4_PRELIM 0xf0301001
-#define CONFIG_SYS_OR4_PRELIM 0xfff00ef4
-#define CONFIG_SYS_BR5_PRELIM 0xf0401001
-#define CONFIG_SYS_OR5_PRELIM 0xfff00ef4
-#else
-#define CONFIG_SYS_BR2_PRELIM 0xf0101081
-#define CONFIG_SYS_OR2_PRELIM 0xfff00104
-#define CONFIG_SYS_BR3_PRELIM 0xf0201081
-#define CONFIG_SYS_OR3_PRELIM 0xfff00104
-#define CONFIG_SYS_BR4_PRELIM 0xf0301081
-#define CONFIG_SYS_OR4_PRELIM 0xfff00104
-#define CONFIG_SYS_BR5_PRELIM 0xf0401081
-#define CONFIG_SYS_OR5_PRELIM 0xfff00104
-#endif
-#define CONFIG_SYS_BR7_PRELIM 0xf0500881
-#define CONFIG_SYS_OR7_PRELIM 0xffff8104
-#define CONFIG_SYS_MPTPR 0x2700
-#define CONFIG_SYS_PSDMR 0x822a2452 /* optimal */
-/*#define CONFIG_SYS_PSDMR 0x822a48a3 */ /* relaxed */
-#define CONFIG_SYS_PSRT 0x1a
-
-/* "bad" address */
-#define CONFIG_SYS_RESET_ADDRESS 0x40000000
-
-#endif /* __CONFIG_H */
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