Heiko Schocher <hs@denx.de>
+ charon MPC5200
ids8247 MPC8247
jupiter MPC5200
kmeter1 MPC8360
Stefano Babic <sbabic@denx.de>
+ ea20 davinci
polaris xscale
trizepsiv xscale
mx51evk i.MX51
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
-Simon Kagstrom <simon.kagstrom@netinsight.net>
-
- openrd_base ARM926EJS (Kirkwood SoC)
-
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
Prafulla Wadaskar <prafulla@marvell.com>
+ aspenite ARM926EJS (ARMADA100 88AP168 SoC)
mv88f6281gtw_ge ARM926EJS (Kirkwood SoC)
+ openrd_base ARM926EJS (Kirkwood SoC)
rd6281a ARM926EJS (Kirkwood SoC)
sheevaplug ARM926EJS (Kirkwood SoC)
lart SA1100
dnp1110 SA1110
+Syed Mohammed Khasim <sm.khasim@gmail.com>
+Sughosh Ganu <urwithsughosh@gmail.com>
+
+ hawkboard ARM926EJS (OMAP-L138)
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
ap926ejs \
ap946es \
ap966 \
+ aspenite \
cp920t \
cp922_XA10 \
cp926ejs \
#define DEBUG
#undef DEBUG
-/* U-Boot routines needed */
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
/*****************************************************************************
*
* This is the API core.
--- /dev/null
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y = cpu.o timer.o dram.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+#include <asm/io.h>
+
+#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID (1<<8)
+#define L2C_RAM_SEL (1<<4)
+
+int arch_cpu_init(void)
+{
+ u32 val;
+ struct armd1cpu_registers *cpuregs =
+ (struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+ struct armd1apb1_registers *apb1clkres =
+ (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+
+ struct armd1mpmu_registers *mpmu =
+ (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+
+ /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
+ val = readl(&cpuregs->cpu_conf);
+ val = val | SET_MRVL_ID;
+ writel(val, &cpuregs->cpu_conf);
+
+ /* Enable Clocks for all hardware units */
+ writel(0xFFFFFFFF, &mpmu->acgr);
+
+ /* Turn on AIB and AIB-APB Functional clock */
+ writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
+
+ /* ensure L2 cache is not mapped as SRAM */
+ val = readl(&cpuregs->cpu_conf);
+ val = val & ~(L2C_RAM_SEL);
+ writel(val, &cpuregs->cpu_conf);
+
+ /* Enable GPIO clock */
+ writel(APBC_APBCLK, &apb1clkres->gpio);
+
+ /*
+ * Enable Functional and APB clock at 14.7456MHz
+ * for configured UART console
+ */
+#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
+ writel(UARTCLK14745KHZ, &apb1clkres->uart3);
+#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
+ writel(UARTCLK14745KHZ, &apb1clkres->uart2);
+#else
+ writel(UARTCLK14745KHZ, &apb1clkres->uart1);
+#endif
+ icache_enable();
+
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u32 id;
+ struct armd1cpu_registers *cpuregs =
+ (struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+ id = readl(&cpuregs->chip_id);
+ printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMADA100 DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet Appendix A.17
+ */
+struct armd1ddr_map_registers {
+ u32 cs; /* Memory Address Map Register -CS */
+ u32 pad[3];
+};
+
+struct armd1ddr_registers {
+ u8 pad[0x100 - 0x000];
+ struct armd1ddr_map_registers mmap[2];
+};
+
+/*
+ * armd1_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd1_sdram_base(int chip_sel)
+{
+ struct armd1ddr_registers *ddr_regs =
+ (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+ u32 result = 0;
+ u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+ if (!CS_valid)
+ return 0;
+
+ result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+ return result;
+}
+
+/*
+ * armd1_sdram_size - reads SDRAM size
+ */
+u32 armd1_sdram_size(int chip_sel)
+{
+ struct armd1ddr_registers *ddr_regs =
+ (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+ u32 result = 0;
+ u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+ if (!CS_valid)
+ return 0;
+
+ result = readl(&ddr_regs->mmap[chip_sel].cs);
+ result = (result >> 16) & 0xF;
+ if (result < 0x7) {
+ printf("Unknown DRAM Size\n");
+ return -1;
+ } else {
+ return ((0x8 << (result - 0x7)) * 1024 * 1024);
+ }
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+ int i;
+
+ gd->ram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = armd1_sdram_base(i);
+ gd->bd->bi_dram[i].size = armd1_sdram_size(i);
+ /*
+ * It is assumed that all memory banks are consecutive
+ * and without gaps.
+ * If the gap is found, ram_size will be reported for
+ * consecutive memory only
+ */
+ if (gd->bd->bi_dram[i].start != gd->ram_size)
+ break;
+
+ gd->ram_size += gd->bd->bi_dram[i].size;
+
+ }
+
+ for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* If above loop terminated prematurely, we need to set
+ * remaining banks' start address & size as 0. Otherwise other
+ * u-boot functions and Linux kernel gets wrong values which
+ * could result in crash */
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+ return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+ dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+/*
+ * Timer registers
+ * Refer Section A.6 in Datasheet
+ */
+struct armd1tmr_registers {
+ u32 clk_ctrl; /* Timer clk control reg */
+ u32 match[9]; /* Timer match registers */
+ u32 count[3]; /* Timer count registers */
+ u32 status[3];
+ u32 ie[3];
+ u32 preload[3]; /* Timer preload value */
+ u32 preload_ctrl[3];
+ u32 wdt_match_en;
+ u32 wdt_match_r;
+ u32 wdt_val;
+ u32 wdt_sts;
+ u32 icr[3];
+ u32 wdt_icr;
+ u32 cer; /* Timer count enable reg */
+ u32 cmr;
+ u32 ilr[3];
+ u32 wcr;
+ u32 wfar;
+ u32 wsar;
+ u32 cvwr;
+};
+
+#define TIMER 0 /* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x) ((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 0xffffffff
+#define COUNT_RD_REQ 0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+
+/* For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+ struct armd1tmr_registers *armd1timers =
+ (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+ volatile int loop=100;
+
+ writel(COUNT_RD_REQ, &armd1timers->cvwr);
+ while (loop--);
+ return(readl(&armd1timers->cvwr));
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ gd->tbl = read_timer();
+ gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = read_timer();
+
+ if (now >= gd->tbl) {
+ /* normal mode */
+ gd->tbu += now - gd->tbl;
+ } else {
+ /* we have an overflow ... */
+ gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+ }
+ gd->tbl = now;
+
+ return gd->tbu;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+ base);
+}
+
+void set_timer(ulong t)
+{
+ gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong delayticks;
+ ulong endtime;
+
+ delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+ endtime = get_timer_masked() + delayticks;
+
+ while (get_timer_masked() < endtime);
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+ struct armd1apb1_registers *apb1clkres =
+ (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+ struct armd1tmr_registers *armd1timers =
+ (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+
+ /* Enable Timer clock at 3.25 MHZ */
+ writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+ /* load value into timer */
+ writel(0x0, &armd1timers->clk_ctrl);
+ /* Use Timer 0 Match Resiger 0 */
+ writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
+ /* Preload value is 0 */
+ writel(0x0, &armd1timers->preload[TIMER]);
+ /* Enable match comparator 0 for Timer 0 */
+ writel(0x1, &armd1timers->preload_ctrl[TIMER]);
+
+ /* Enable timer 0 */
+ writel(0x1, &armd1timers->cer);
+ /* init the gd->tbu and gd->tbl value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+#define MPMU_APRR_WDTR (1<<4)
+#define TMR_WFAR 0xbaba /* WDT Register First key */
+#define TMP_WSAR 0xeb10 /* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+ struct armd1mpmu_registers *mpmu =
+ (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+ struct armd1tmr_registers *armd1timers =
+ (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+ u32 val;
+
+ /* negate hardware reset to the WDT after system reset */
+ val = readl(&mpmu->aprr);
+ val = val | MPMU_APRR_WDTR;
+ writel(val, &mpmu->aprr);
+
+ /* reset/enable WDT clock */
+ writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
+ readl(&mpmu->wdtpcr);
+ writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+ readl(&mpmu->wdtpcr);
+
+ /* clear previous WDT status */
+ writel(TMR_WFAR, &armd1timers->wfar);
+ writel(TMP_WSAR, &armd1timers->wsar);
+ writel(0, &armd1timers->wdt_sts);
+
+ /* set match counter */
+ writel(TMR_WFAR, &armd1timers->wfar);
+ writel(TMP_WSAR, &armd1timers->wsar);
+ writel(0xf, &armd1timers->wdt_match_r);
+
+ /* enable WDT reset */
+ writel(TMR_WFAR, &armd1timers->wfar);
+ writel(TMP_WSAR, &armd1timers->wsar);
+ writel(0x3, &armd1timers->wdt_match_en);
+
+ while(1);
+}
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_ARMADA100_H
+#define _ASM_ARCH_ARMADA100_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* __ASSEMBLY__ */
+
+#if defined (CONFIG_ARMADA100)
+#include <asm/arch/cpu.h>
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
+#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
+#define APBC_RST (1<<2) /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
+
+/* Register Base Addresses */
+#define ARMD1_DRAM_BASE 0xB0000000
+#define ARMD1_TIMER_BASE 0xD4014000
+#define ARMD1_APBC1_BASE 0xD4015000
+#define ARMD1_APBC2_BASE 0xD4015800
+#define ARMD1_UART1_BASE 0xD4017000
+#define ARMD1_UART2_BASE 0xD4018000
+#define ARMD1_GPIO_BASE 0xD4019000
+#define ARMD1_SSP1_BASE 0xD401B000
+#define ARMD1_SSP2_BASE 0xD401C000
+#define ARMD1_MFPR_BASE 0xD401E000
+#define ARMD1_SSP3_BASE 0xD401F000
+#define ARMD1_SSP4_BASE 0xD4020000
+#define ARMD1_SSP5_BASE 0xD4021000
+#define ARMD1_UART3_BASE 0xD4026000
+#define ARMD1_MPMU_BASE 0xD4050000
+#define ARMD1_APMU_BASE 0xD4282800
+#define ARMD1_CPU_BASE 0xD4282C00
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Datasheet Appendix A.8
+ */
+struct armd1mpmu_registers {
+ u8 pad0[0x08 - 0x00];
+ u32 fccr; /*0x0008*/
+ u32 pocr; /*0x000c*/
+ u32 posr; /*0x0010*/
+ u32 succr; /*0x0014*/
+ u8 pad1[0x030 - 0x014 - 4];
+ u32 gpcr; /*0x0030*/
+ u8 pad2[0x200 - 0x030 - 4];
+ u32 wdtpcr; /*0x0200*/
+ u8 pad3[0x1000 - 0x200 - 4];
+ u32 apcr; /*0x1000*/
+ u32 apsr; /*0x1004*/
+ u8 pad4[0x1020 - 0x1004 - 4];
+ u32 aprr; /*0x1020*/
+ u32 acgr; /*0x1024*/
+ u32 arsr; /*0x1028*/
+};
+
+/*
+ * APB1 Clock Reset/Control Registers
+ * Refer Datasheet Appendix A.10
+ */
+struct armd1apb1_registers {
+ u32 uart1; /*0x000*/
+ u32 uart2; /*0x004*/
+ u32 gpio; /*0x008*/
+ u32 pwm1; /*0x00c*/
+ u32 pwm2; /*0x010*/
+ u32 pwm3; /*0x014*/
+ u32 pwm4; /*0x018*/
+ u8 pad0[0x028 - 0x018 - 4];
+ u32 rtc; /*0x028*/
+ u32 twsi0; /*0x02c*/
+ u32 kpc; /*0x030*/
+ u32 timers; /*0x034*/
+ u8 pad1[0x03c - 0x034 - 4];
+ u32 aib; /*0x03c*/
+ u32 sw_jtag; /*0x040*/
+ u32 timer1; /*0x044*/
+ u32 onewire; /*0x048*/
+ u8 pad2[0x050 - 0x048 - 4];
+ u32 asfar; /*0x050 AIB Secure First Access Reg*/
+ u32 assar; /*0x054 AIB Secure Second Access Reg*/
+ u8 pad3[0x06c - 0x054 - 4];
+ u32 twsi1; /*0x06c*/
+ u32 uart3; /*0x070*/
+ u8 pad4[0x07c - 0x070 - 4];
+ u32 timer2; /*0x07C*/
+ u8 pad5[0x084 - 0x07c - 4];
+ u32 ac97; /*0x084*/
+};
+
+#endif /* CONFIG_ARMADA100 */
+#endif /* _ASM_ARCH_ARMADA100_H */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ARMADA100CPU_H
+#define _ARMADA100CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * CPU Interface Registers
+ * Refer Datasheet Appendix A.2
+ */
+struct armd1cpu_registers {
+ u32 chip_id; /* Chip Id Reg */
+ u32 pad;
+ u32 cpu_conf; /* CPU Conf Reg */
+ u32 pad1;
+ u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
+ u32 pad2;
+ u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
+ u32 mcb_conf; /* MCB Conf Reg */
+ u32 sys_boot_ctl; /* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 armd1_sdram_base(int);
+u32 armd1_sdram_size(int);
+
+#endif /* _ARMADA100CPU_H */
--- /dev/null
+/*
+ * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
+ * (C) Copyright 2007
+ * Marvell Semiconductor <www.marvell.com>
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARMADA100_MFP_H
+#define __ARMADA100_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART1 */
+#define MFP107_UART1_TXD MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST
+#define MFP107_UART1_RXD MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST
+#define MFP108_UART1_RXD MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST
+#define MFP108_UART1_TXD MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST
+#define MFP109_UART1_CTS MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP109_UART1_RTS MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP110_UART1_RTS MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP110_UART1_CTS MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP111_UART1_RI MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP111_UART1_DSR MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP112_UART1_DTR MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP112_UART1_DCD MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* UART2 */
+#define MFP47_UART2_RXD MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP48_UART2_TXD MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP88_UART2_RXD MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP89_UART2_TXD MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* UART3 */
+#define MFPO8_UART3_RXD MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFPO9_UART3_TXD MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* More macros can be defined here... */
+
+#define MFP_PIN_MAX 117
+
+#endif /* __ARMADA100_MFP_H */
--- /dev/null
+/*
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MISC_H
+#define __MISC_H
+
+/* pin muxer definitions */
+#define PIN_MUX_NUM_FIELDS 8 /* Per register */
+#define PIN_MUX_FIELD_SIZE 4 /* n in bits */
+#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1)
+
+/* pin definition */
+struct pinmux_config {
+ dv_reg *mux; /* Address of mux register */
+ unsigned char value; /* Value to set in field */
+ unsigned char field; /* field number */
+};
+
+/* pin table definition */
+struct pinmux_resource {
+ const struct pinmux_config *pins;
+ const int n_pins;
+};
+
+#define PINMUX_ITEM(item) { \
+ .pins = item, \
+ .n_pins = ARRAY_SIZE(item) \
+ }
+
+#define HAWKBOARD_KICK0_UNLOCK 0x83e70b13
+#define HAWKBOARD_KICK1_UNLOCK 0x95a4f1e0
+
+struct lpsc_resource {
+ const int lpsc_no;
+};
+
+int dvevm_read_mac_address(uint8_t *buf);
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
+int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+ int n_items);
+#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+void davinci_emac_mii_mode_sel(int mode_sel);
+#endif
+#if defined(CONFIG_SOC_DA8XX)
+void irq_init(void);
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+ const int n_items);
+#endif
+
+#endif /* __MISC_H */
#define DAVINCI_PSC1_BASE 0x01e27000
#define DAVINCI_SPI0_BASE 0x01c41000
#define DAVINCI_USB_OTG_BASE 0x01e00000
-#define DAVINCI_SPI1_BASE 0x01e12000
+#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
+ 0x01e12000 : 0x01f0e000)
#define DAVINCI_GPIO_BASE 0x01e26000
#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
#define DAVINCI_INTC_BASE 0xfffee000
#define DAVINCI_BOOTCFG_BASE 0x01c14000
+#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
+#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
+#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
+#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
+#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
#endif /* CONFIG_SOC_DA8XX */
/* Power and Sleep Controller (PSC) Domains */
#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
+#define ASYNC3 get_async3_src()
+#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
+#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
/* Boot config */
struct davinci_syscfg_regs {
dv_reg revid;
- dv_reg rsvd[71];
+ dv_reg rsvd[13];
+ dv_reg kick0;
+ dv_reg kick1;
+ dv_reg rsvd1[56];
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;
#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+static inline int cpu_is_da830(void)
+{
+ unsigned int jtag_id = REG(JTAG_ID_REG);
+ unsigned short part_no = (jtag_id >> 12) & 0xffff;
+
+ return ((part_no == 0xb7df) ? 1 : 0);
+}
+static inline int cpu_is_da850(void)
+{
+ unsigned int jtag_id = REG(JTAG_ID_REG);
+ unsigned short part_no = (jtag_id >> 12) & 0xffff;
+
+ return ((part_no == 0xb7d1) ? 1 : 0);
+}
+
+static inline int get_async3_src(void)
+{
+ return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
+ PLL1_SYSCLK2 : 2;
+}
+
#endif /* CONFIG_SOC_DA8XX */
#endif /* __ASM_ARCH_HARDWARE_H */
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_M5208
-int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
return 0;
}
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* Call the board specific reset actions first. */
if(board_reset) {
#endif
#ifdef CONFIG_M5272
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5275
-int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
return 0;
}
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
return 0;
return 0;
}
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(MCFSIM_SYPCR, 0xc0);
return 0;
}
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(SIM_SYPCR, 0xc0);
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS +=
return (0);
}
-int do_reset(void)
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
/* indirect call to go beyond 256MB limitation of toolchain */
!defined(CONFIG_ELPPC) && \
!defined(CONFIG_PPMC7XX)
/* no generic way to do board reset. simply call soft_reset. */
-void
-do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr;
/* flush and disable I/D cache */
addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
soft_restart(addr);
- while(1); /* not reached */
+
+ /* not reached */
+ while(1)
+ ;
+
+ return 1;
}
#endif
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
*(.fixup)
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
/* ------------------------------------------------------------------------- */
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
}
-void
-do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
while (1)
;
+
+ return 1;
}
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
static void DQS_calibration_process(void);
#endif
#endif
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
static unsigned char spd_read(uchar chip, uint addr)
{
*-------------------------------------------------------------------------------
*/
-/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
- *
+/*
+ * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
*
- * The processor starts at 0xfffffffc and the code is executed
- * from flash/rom.
- * in memory, but as long we don't jump around before relocating.
- * board_init lies at a quite high address and when the cpu has
- * jumped there, everything is ok.
- * This works because the cpu gives the FLASH (CS0) the whole
- * address space at startup, and board_init lies as a echo of
- * the flash somewhere up there in the memorymap.
+ * The following description only applies to the NOR flash style booting.
+ * NAND booting is different. For more details about NAND booting on 4xx
+ * take a look at doc/README.nand-boot-ppc440.
*
- * board_init will change CS0 to be positioned at the correct
- * address and (s)dram will be positioned at address 0
+ * The CPU starts at address 0xfffffffc (last word in the address space).
+ * The U-Boot image therefore has to be located in the "upper" area of the
+ * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
+ * the boot chip-select (CS0) is quite big and covers this area. On the
+ * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
+ * reconfigure this CS0 (and other chip-selects as well when configured
+ * this way) in the boot process to the "correct" values matching the
+ * board layout.
*/
+
#include <asm-offsets.h>
#include <config.h>
#include <asm/ppc4xx.h>
/* NOTREACHED - board_init_f() does not return */
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
/*
* 4xx RAM-booting U-Boot image is started from offset 0
*/
#include "config.h" /* CONFIG_BOARDDIR */
#ifndef RESET_VECTOR_ADDRESS
+#ifdef CONFIG_RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
+#else
#define RESET_VECTOR_ADDRESS 0xfffffffc
#endif
+#endif
OUTPUT_ARCH(powerpc)
PROVIDE (erotext = .);
.reloc :
{
- KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
* start.o, since the first shadow TLB only covers 4k
* of address space.
*/
+#ifdef CONFIG_INIT_TLB
+ CONFIG_INIT_TLB (.bootpg)
+#else
CONFIG_BOARDDIR/init.o (.bootpg)
+#endif
} :text = 0xffff
#endif
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern ulong get_effective_memsize(void);
static ulong get_sp (void);
static void set_clocks_in_mhz (bd_t *kbd);
int
kgdb_setjmp(long *buf)
{
- asm ("mflr 0; stw 0,0(%0);"
- "stw 1,4(%0); stw 2,8(%0);"
- "mfcr 0; stw 0,12(%0);"
- "stmw 13,16(%0)"
- : : "r" (buf));
+ unsigned long temp;
+
+ asm volatile("mflr %0; stw %0,0(%1);"
+ "stw %%r1,4(%1); stw %%r2,8(%1);"
+ "mfcr %0; stw %0,12(%1);"
+ "stmw %%r13,16(%1)"
+ : "=&r"(temp) : "r" (buf));
/* XXX should save fp regs as well */
return 0;
}
void
kgdb_longjmp(long *buf, int val)
{
+ unsigned long temp;
+
if (val == 0)
val = 1;
- asm ("lmw 13,16(%0);"
- "lwz 0,12(%0); mtcrf 0x38,0;"
- "lwz 0,0(%0); lwz 1,4(%0); lwz 2,8(%0);"
- "mtlr 0; mr 3,%1"
- : : "r" (buf), "r" (val));
+
+ asm volatile("lmw %%r13,16(%1);"
+ "lwz %0,12(%1); mtcrf 0x38,%0;"
+ "lwz %0,0(%1); lwz %%r1,4(%1); lwz %%r2,8(%1);"
+ "mtlr %0; mr %%r3,%2"
+ : "=&r"(temp) : "r" (buf), "r" (val));
}
static inline unsigned long
int init_timebase (void)
{
+ unsigned long temp;
+
#if defined(CONFIG_5xx) || defined(CONFIG_8xx)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#endif
/* reset */
- asm ("li 3,0 ; mttbu 3 ; mttbl 3 ;");
+ asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;"
+ : "=&r"(temp) );
#if defined(CONFIG_5xx) || defined(CONFIG_8xx)
/* enable */
--- /dev/null
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := aspenite.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ u32 mfp_cfg[] = {
+ /* Enable Console on UART1 */
+ MFP107_UART1_RXD,
+ MFP108_UART1_TXD,
+ MFP_EOC /*End of configureation*/
+ };
+ /* configure MFP's */
+ mfp_config(mfp_cfg);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of Board */
+ gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ return 0;
+}
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Use board specific linker script
-LDSCRIPT := $(SRCTREE)/board/amirix/ap1000/u-boot.lds
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# ATC boards
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
#include "fwupdate.h"
-extern int do_bootm(cmd_tbl_t *, int, int, char * const []);
extern long do_fat_read(const char *, void *, unsigned long, int);
extern int do_fat_fsload(cmd_tbl_t *, int, int, char * const []);
+++ /dev/null
-#
-# (C) Copyright 2003
-# Martin Winistoerfer, martinwinistoerfer@gmx.ch.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# CMI Board Configuration
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+++ /dev/null
-#
-# (C) Copyright 2001-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# CPC45 board
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# CPU86 boards
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+++ /dev/null
-#
-# (C) Copyright 2001-2005
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# CPU87 board
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004
-# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Cogent CSB272 board
-#
-
-LDFLAGS += $(LINKER_UNDEFS)
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004
-# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Cogent CSB472 board
-#
-
-LDFLAGS += $(LINKER_UNDEFS)
LIB = $(obj)lib$(VENDOR).o
-COBJS := misc.o
+COBJS := misc.o davinci_pinmux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * DaVinci pinmux functions.
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+/*
+ * Change the setting of a pin multiplexer field.
+ *
+ * Takes an array of pinmux settings similar to:
+ *
+ * struct pinmux_config uart_pins[] = {
+ * { &davinci_syscfg_regs->pinmux[8], 2, 7 },
+ * { &davinci_syscfg_regs->pinmux[9], 2, 0 }
+ * };
+ *
+ * Stepping through the array, each pinmux[n] register has the given value
+ * set in the pin mux field specified.
+ *
+ * The number of pins in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Returns 0 if all field numbers and values are in the correct range,
+ * else returns -1.
+ */
+int davinci_configure_pin_mux(const struct pinmux_config *pins,
+ const int n_pins)
+{
+ int i;
+
+ /* check for invalid pinmux values */
+ for (i = 0; i < n_pins; i++) {
+ if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
+ (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
+ return -1;
+ }
+
+ /* configure the pinmuxes */
+ for (i = 0; i < n_pins; i++) {
+ const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
+ const unsigned int value = pins[i].value << offset;
+ const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
+ const dv_reg *mux = pins[i].mux;
+
+ writel(value | (readl(mux) & (~mask)), mux);
+ }
+
+ return 0;
+}
+
+/*
+ * Configure multiple pinmux resources.
+ *
+ * Takes an pinmux_resource array of pinmux_config and pin counts:
+ *
+ * const struct pinmux_resource pinmuxes[] = {
+ * PINMUX_ITEM(uart_pins),
+ * PINMUX_ITEM(i2c_pins),
+ * };
+ *
+ * The number of items in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Each item entry is configured in the defined order. If configuration
+ * of any item fails, -1 is returned and none of the following items are
+ * configured. On success, 0 is returned.
+ */
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+ const int n_items)
+{
+ int i;
+
+ for (i = 0; i < n_items; i++) {
+ if (davinci_configure_pin_mux(item[i].pins,
+ item[i].n_pins) != 0)
+ return -1;
+ }
+
+ return 0;
+}
#include <net.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
-#include "misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_PRELOADER
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
}
+#endif
#ifdef CONFIG_DRIVER_TI_EMAC
return 0;
}
+/*
+ * Set the mii mode as MII or RMII
+ */
+#if defined(CONFIG_DRIVER_TI_EMAC)
+void davinci_emac_mii_mode_sel(int mode_sel)
+{
+ int val;
+
+ val = readl(&davinci_syscfg_regs->cfgchip3);
+ if (mode_sel == 0)
+ val &= ~(1 << 8);
+ else
+ val |= (1 << 8);
+ writel(val, &davinci_syscfg_regs->cfgchip3);
+}
+#endif
/*
* If there is no MAC address in the environment, then it will be initialized
* (silently) from the value in the EEPROM.
}
}
-#endif /* DAVINCI_EMAC */
+#endif /* CONFIG_DRIVER_TI_EMAC */
-/*
- * Change the setting of a pin multiplexer field.
- *
- * Takes an array of pinmux settings similar to:
- *
- * struct pinmux_config uart_pins[] = {
- * { &davinci_syscfg_regs->pinmux[8], 2, 7 },
- * { &davinci_syscfg_regs->pinmux[9], 2, 0 }
- * };
- *
- * Stepping through the array, each pinmux[n] register has the given value
- * set in the pin mux field specified.
- *
- * The number of pins in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Returns 0 if all field numbers and values are in the correct range,
- * else returns -1.
- */
-int davinci_configure_pin_mux(const struct pinmux_config *pins,
- const int n_pins)
+#if defined(CONFIG_SOC_DA8XX)
+#ifndef CONFIG_USE_IRQ
+void irq_init(void)
{
- int i;
+ /*
+ * Mask all IRQs by clearing the global enable and setting
+ * the enable clear for all the 90 interrupts.
+ */
- /* check for invalid pinmux values */
- for (i = 0; i < n_pins; i++) {
- if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
- (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
- return -1;
- }
+ writel(0, &davinci_aintc_regs->ger);
- /* configure the pinmuxes */
- for (i = 0; i < n_pins; i++) {
- const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
- const unsigned int value = pins[i].value << offset;
- const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
- const dv_reg *mux = pins[i].mux;
+ writel(0, &davinci_aintc_regs->hier);
- writel(value | (readl(mux) & (~mask)), mux);
- }
-
- return 0;
+ writel(0xffffffff, &davinci_aintc_regs->ecr1);
+ writel(0xffffffff, &davinci_aintc_regs->ecr2);
+ writel(0xffffffff, &davinci_aintc_regs->ecr3);
}
+#endif
/*
- * Configure multiple pinmux resources.
- *
- * Takes an pinmux_resource array of pinmux_config and pin counts:
- *
- * const struct pinmux_resource pinmuxes[] = {
- * PINMUX_ITEM(uart_pins),
- * PINMUX_ITEM(i2c_pins),
- * };
- *
- * The number of items in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Each item entry is configured in the defined order. If configuration
- * of any item fails, -1 is returned and none of the following items are
- * configured. On success, 0 is returned.
+ * Enable PSC for various peripherals.
*/
-int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
const int n_items)
{
int i;
- for (i = 0; i < n_items; i++) {
- if (davinci_configure_pin_mux(item[i].pins,
- item[i].n_pins) != 0)
- return -1;
- }
+ for (i = 0; i < n_items; i++)
+ lpsc_on(item[i].lpsc_no);
return 0;
}
+#endif
+++ /dev/null
-/*
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __MISC_H
-#define __MISC_H
-
-/* pin muxer definitions */
-#define PIN_MUX_NUM_FIELDS 8 /* Per register */
-#define PIN_MUX_FIELD_SIZE 4 /* n in bits */
-#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1)
-
-/* pin definition */
-struct pinmux_config {
- dv_reg *mux; /* Address of mux register */
- unsigned char value; /* Value to set in field */
- unsigned char field; /* field number */
-};
-
-/* pin table definition */
-struct pinmux_resource {
- const struct pinmux_config *pins;
- const int n_pins;
-};
-
-#define PINMUX_ITEM(item) { \
- .pins = item, \
- .n_pins = ARRAY_SIZE(item) \
- }
-
-int dvevm_read_mac_address(uint8_t *buf);
-void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
-int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
-int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
- int n_items);
-
-#endif /* __MISC_H */
LIB = $(obj)lib$(BOARD).o
-COBJS-y += common.o
COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o
COBJS-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o
+COBJS-$(CONFIG_MACH_DAVINCI_HAWK) += hawkboard.o
COBJS := $(COBJS-y)
+++ /dev/null
-/*
- * Miscellaneous DA8XX functions.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include "common.h"
-
-#ifndef CONFIG_USE_IRQ
-void irq_init(void)
-{
- /*
- * Mask all IRQs by clearing the global enable and setting
- * the enable clear for all the 90 interrupts.
- */
-
- writel(0, &davinci_aintc_regs->ger);
-
- writel(0, &davinci_aintc_regs->hier);
-
- writel(0xffffffff, &davinci_aintc_regs->ecr1);
- writel(0xffffffff, &davinci_aintc_regs->ecr2);
- writel(0xffffffff, &davinci_aintc_regs->ecr3);
-}
-#endif
-
-/*
- * Enable PSC for various peripherals.
- */
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
- const int n_items)
-{
- int i;
-
- for (i = 0; i < n_items; i++)
- lpsc_on(item[i].lpsc_no);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __COMMON_H
-#define __COMMON_H
-
-struct lpsc_resource {
- const int lpsc_no;
-};
-
-void irq_init(void);
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
- int n_items);
-
-#endif /* __COMMON_H */
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
-#include "../common/misc.h"
-#include "common.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
-#include "../common/misc.h"
-#include "common.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DRIVER_TI_EMAC
static const struct pinmux_config emac_pins[] = {
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+ { pinmux(14), 8, 2 },
+ { pinmux(14), 8, 3 },
+ { pinmux(14), 8, 4 },
+ { pinmux(14), 8, 5 },
+ { pinmux(14), 8, 6 },
+ { pinmux(14), 8, 7 },
+ { pinmux(15), 8, 1 },
+#else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
{ pinmux(2), 8, 1 },
{ pinmux(2), 8, 2 },
{ pinmux(2), 8, 3 },
{ pinmux(3), 8, 5 },
{ pinmux(3), 8, 6 },
{ pinmux(3), 8, 7 },
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
{ pinmux(4), 8, 0 },
{ pinmux(4), 8, 1 }
};
-#endif /* CONFIG_DRIVER_TI_EMAC */
/* I2C pin muxer settings */
static const struct pinmux_config i2c_pins[] = {
};
#endif
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define HAS_RMII 1
+#else
+#define HAS_RMII 0
+#endif
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;
- /* set cfgchip3 to select MII */
- writel(readl(&davinci_syscfg_regs->cfgchip3) & ~(1 << 8),
- &davinci_syscfg_regs->cfgchip3);
+
+ davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
#ifdef CONFIG_DRIVER_TI_EMAC
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+/**
+ * rmii_hw_init
+ *
+ * DA850/OMAP-L138 EVM can interface to a daughter card for
+ * additional features. This card has an I2C GPIO Expander TCA6416
+ * to select the required functions like camera, RMII Ethernet,
+ * character LCD, video.
+ *
+ * Initialization of the expander involves configuring the
+ * polarity and direction of the ports. P07-P05 are used here.
+ * These ports are connected to a Mux chip which enables only one
+ * functionality at a time.
+ *
+ * For RMII phy to respond, the MII MDIO clock has to be disabled
+ * since both the PHY devices have address as zero. The MII MDIO
+ * clock is controlled via GPIO2[6].
+ *
+ * This code is valid for Beta version of the hardware
+ */
+int rmii_hw_init(void)
+{
+ const struct pinmux_config gpio_pins[] = {
+ { pinmux(6), 8, 1 }
+ };
+ u_int8_t buf[2];
+ unsigned int temp;
+ int ret;
+
+ /* PinMux for GPIO */
+ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+ return 1;
+
+ /* I2C Exapnder configuration */
+ /* Set polarity to non-inverted */
+ buf[0] = 0x0;
+ buf[1] = 0x0;
+ ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
+ if (ret) {
+ printf("\nExpander @ 0x%02x write FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ return ret;
+ }
+
+ /* Configure P07-P05 as outputs */
+ buf[0] = 0x1f;
+ buf[1] = 0xff;
+ ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
+ if (ret) {
+ printf("\nExpander @ 0x%02x write FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ }
+
+ /* For Ethernet RMII selection
+ * P07(SelA)=0
+ * P06(SelB)=1
+ * P05(SelC)=1
+ */
+ if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+ printf("\nExpander @ 0x%02x read FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ }
+
+ buf[0] &= 0x1f;
+ buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
+ if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+ printf("\nExpander @ 0x%02x write FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ }
+
+ /* Set the output as high */
+ temp = REG(GPIO_BANK2_REG_SET_ADDR);
+ temp |= (0x01 << 6);
+ REG(GPIO_BANK2_REG_SET_ADDR) = temp;
+
+ /* Set the GPIO direction as output */
+ temp = REG(GPIO_BANK2_REG_DIR_ADDR);
+ temp &= ~(0x01 << 6);
+ REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
+
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+ /* Select RMII fucntion through the expander */
+ if (rmii_hw_init())
+ printf("RMII hardware init failed!!!\n");
+#endif
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
--- /dev/null
+/*
+ * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
+ *
+ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <ns16550.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * Kick Registers need to be set to allow access to Pin Mux registers
+ */
+ writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+ writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+ /* set cfgchip3 to select mii */
+ writel(readl(&davinci_syscfg_regs->cfgchip3) &
+ ~(1 << 8), &davinci_syscfg_regs->cfgchip3);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ char buf[32];
+
+ printf("ARM Clock : %s MHz\n",
+ strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
+
+ return 0;
+}
--- /dev/null
+/*
+ * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
+ *
+ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <ns16550.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+
+static const struct pinmux_config mii_pins[] = {
+ { pinmux(2), 8, 1 },
+ { pinmux(2), 8, 2 },
+ { pinmux(2), 8, 3 },
+ { pinmux(2), 8, 4 },
+ { pinmux(2), 8, 5 },
+ { pinmux(2), 8, 6 },
+ { pinmux(2), 8, 7 }
+};
+
+static const struct pinmux_config mdio_pins[] = {
+ { pinmux(4), 8, 0 },
+ { pinmux(4), 8, 1 }
+};
+
+static const struct pinmux_config nand_pins[] = {
+ { pinmux(7), 1, 1 },
+ { pinmux(7), 1, 2 },
+ { pinmux(7), 1, 4 },
+ { pinmux(7), 1, 5 },
+ { pinmux(9), 1, 0 },
+ { pinmux(9), 1, 1 },
+ { pinmux(9), 1, 2 },
+ { pinmux(9), 1, 3 },
+ { pinmux(9), 1, 4 },
+ { pinmux(9), 1, 5 },
+ { pinmux(9), 1, 6 },
+ { pinmux(9), 1, 7 },
+ { pinmux(12), 1, 5 },
+ { pinmux(12), 1, 6 }
+};
+
+static const struct pinmux_config uart2_pins[] = {
+ { pinmux(0), 4, 6 },
+ { pinmux(0), 4, 7 },
+ { pinmux(4), 2, 4 },
+ { pinmux(4), 2, 5 }
+};
+
+static const struct pinmux_config i2c_pins[] = {
+ { pinmux(4), 2, 4 },
+ { pinmux(4), 2, 5 }
+};
+
+static const struct pinmux_resource pinmuxes[] = {
+ PINMUX_ITEM(mii_pins),
+ PINMUX_ITEM(mdio_pins),
+ PINMUX_ITEM(i2c_pins),
+ PINMUX_ITEM(nand_pins),
+ PINMUX_ITEM(uart2_pins),
+};
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+void board_init_f(ulong bootflag)
+{
+ /*
+ * Kick Registers need to be set to allow access to Pin Mux registers
+ */
+ writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+ writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc);
+
+ /* Power on required peripherals
+ * ARM does not have acess by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc));
+
+ /* configure pinmux settings */
+ davinci_configure_pin_mux_items(pinmuxes,
+ ARRAY_SIZE(pinmuxes));
+
+ writel(readl(&davinci_uart2_ctrl_regs->pwremu_mgmt) |
+ (DAVINCI_UART_PWREMU_MGMT_FREE) |
+ (DAVINCI_UART_PWREMU_MGMT_URRST) |
+ (DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ NS16550_init((NS16550_t)(DAVINCI_UART2_BASE),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+ puts("Nand boot...\n");
+
+ nand_boot();
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
+
+void putc(char c)
+{
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+
+ if (c == '\n')
+ NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), '\r');
+
+ NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), c);
+}
+
+void hang(void)
+{
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;)
+ ;
+}
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/nand_defs.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio_defs.h>
#include <asm/arch/nand_defs.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/gpio_defs.h>
#include <netdev.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += ea20.o
+
+COBJS := $(COBJS-y)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Based on da850evm.c, original Copyrights follow:
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+
+/* SPI0 pin muxer settings */
+static const struct pinmux_config spi1_pins[] = {
+ { pinmux(5), 1, 1 },
+ { pinmux(5), 1, 2 },
+ { pinmux(5), 1, 4 },
+ { pinmux(5), 1, 5 }
+};
+
+/* UART pin muxer settings */
+static const struct pinmux_config uart_pins[] = {
+ { pinmux(0), 4, 6 },
+ { pinmux(0), 4, 7 },
+ { pinmux(4), 2, 4 },
+ { pinmux(4), 2, 5 }
+};
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define HAS_RMII 1
+static const struct pinmux_config emac_pins[] = {
+ { pinmux(14), 8, 2 },
+ { pinmux(14), 8, 3 },
+ { pinmux(14), 8, 4 },
+ { pinmux(14), 8, 5 },
+ { pinmux(14), 8, 6 },
+ { pinmux(14), 8, 7 },
+ { pinmux(15), 8, 1 },
+ { pinmux(4), 8, 0 },
+ { pinmux(4), 8, 1 }
+};
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+const struct pinmux_config nand_pins[] = {
+ { pinmux(7), 1, 1 },
+ { pinmux(7), 1, 2 },
+ { pinmux(7), 1, 4 },
+ { pinmux(7), 1, 5 },
+ { pinmux(9), 1, 0 },
+ { pinmux(9), 1, 1 },
+ { pinmux(9), 1, 2 },
+ { pinmux(9), 1, 3 },
+ { pinmux(9), 1, 4 },
+ { pinmux(9), 1, 5 },
+ { pinmux(9), 1, 6 },
+ { pinmux(9), 1, 7 },
+ { pinmux(12), 1, 5 },
+ { pinmux(12), 1, 6 }
+};
+#endif
+
+static const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_SPI_FLASH
+ PINMUX_ITEM(spi1_pins),
+#endif
+ PINMUX_ITEM(uart_pins),
+#ifdef CONFIG_NAND_DAVINCI
+ PINMUX_ITEM(nand_pins),
+#endif
+};
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+
+
+#ifdef CONFIG_NAND_DAVINCI
+ /*
+ * NAND CS setup - cycle counts based on da850evm NAND timings in the
+ * Linux kernel @ 25MHz EMIFA
+ */
+ writel((DAVINCI_ABCR_WSETUP(0) |
+ DAVINCI_ABCR_WSTROBE(0) |
+ DAVINCI_ABCR_WHOLD(0) |
+ DAVINCI_ABCR_RSETUP(0) |
+ DAVINCI_ABCR_RSTROBE(1) |
+ DAVINCI_ABCR_RHOLD(0) |
+ DAVINCI_ABCR_TA(0) |
+ DAVINCI_ABCR_ASIZE_8BIT),
+ &davinci_emif_regs->ab2cr); /* CS3 */
+#endif
+
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_EA20;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2),
+ &davinci_syscfg_regs->suspsrc);
+
+ /* configure pinmux settings */
+ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+ return 1;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+ if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
+ return 1;
+
+ davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ /*
+ * This board has a RMII PHY. However, the MDC line on the SOM
+ * must not be disabled (there is no MII PHY on the
+ * baseboard) via the GPIO2[6], because this pin
+ * disables at the same time the SPI flash.
+ */
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/hardware.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
* do_reset is done here because in this case it is board specific, since the
* 7xx CPUs can only be reset by external HW (the RTC in this case).
*/
-void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if defined(CONFIG_RTC_MK48T59)
/* trigger watchdog immediately */
#else
#error "You must define the macro CONFIG_RTC_MK48T59."
#endif
+ return 0;
}
/* ------------------------------------------------------------------------- */
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# EP8260 boards
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
#undef FPGA_DEBUG
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
DECLARE_GLOBAL_DATA_PTR;
-/*cmd_boot.c*/
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* ------------------------------------------------------------------------- */
#define FPGA_DEBUG
#endif
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
DECLARE_GLOBAL_DATA_PTR;
-/*cmd_boot.c*/
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-
/* ------------------------------------------------------------------------- */
#if 0
#if defined(CONFIG_CMD_BSP)
-extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
extern int do_source (cmd_tbl_t *, int, int, char *[]);
#define ADDRMASK 0xfffff000
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void __ft_board_setup(void *blob, bd_t *bd);
#undef FPGA_DEBUG
extern flash_info_t flash_info[];
-extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
/* ------------------------------------------------------------------------- */
DECLARE_GLOBAL_DATA_PTR;
-/*cmd_boot.c*/
-
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Use board specific linker script
-LDSCRIPT := $(SRCTREE)/board/esd/dasa_sim/u-boot.lds
DECLARE_GLOBAL_DATA_PTR;
-/*cmd_boot.c*/
-
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
#define FPGA_DEBUG
#endif
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
#if defined(CONFIG_CMD_BSP)
-extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-
/*
* Command loadpci: wait for signal from host and boot image.
*/
DECLARE_GLOBAL_DATA_PTR;
/* Prototypes */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
unsigned long fpga_done_state(void);
unsigned long fpga_init_state(void);
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
/* Prototypes */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
#define FPGA_DEBUG
#endif
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
#define FPGA_DEBUG
#endif
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include <malloc.h>
#include <asm/immap.h>
-
-/* Prototypes */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
int checkboard (void) {
ulong val;
uchar val8;
#if defined(CONFIG_HAVE_OWN_RESET)
int
-do_reset (void *cmdtp, int flag, int argc, char * const argv[])
+do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile ioport_t *iop;
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# ICU862 boards
-#
-
-OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
+++ /dev/null
-#
-# (C) Copyright 2005
-# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# IDS 8247 Board
-#
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+++ /dev/null
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# INKA 4X0 board:
-#
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
- * CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
-#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_4xx_DCACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
MY_TLB_WORD2_I_ENABLE);
+#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_4xx_DCACHE)
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+#else /* CONFIG_4xx_DCACHE */
/*
* Setup 2nd TLB with same physical address but different virtual address
* with cache enabled. This is done for fast ECC generation.
*/
program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#ifdef CONFIG_DDR_ECC
/*
* If ECC is enabled, initialize the parity bits.
*/
program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#endif
+
+ /*
+ * Now after initialization (auto-calibration and ECC generation)
+ * remove the TLB entries with caches enabled and program again with
+ * desired cache functionality
+ */
+ remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif /* CONFIG_4xx_DCACHE */
+#endif /* CONFIG_DDR_ECC */
/*
* Clear possible errors resulting from data-eye-search.
+++ /dev/null
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
+++ /dev/null
-#
-# (C) Copyright 2003-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Use board specific linker script
-LDSCRIPT := $(SRCTREE)/board/ml2/u-boot.lds
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MOUSSE boards
-#
-LDSCRIPT := $(SRCTREE)/board/mousse/u-boot.lds
+++ /dev/null
-#
-# (C) Copyright 2003
-# Martin Winistoerfer, martinwinistoerfer@gmx.ch.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+++ /dev/null
-#
-# (C) Copyright 2001-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys PM826 board:
-#
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+++ /dev/null
-#
-# (C) Copyright 2003-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys PM828 board:
-#
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
#if defined(CONFIG_CMD_BSP)
-extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-
/*
* Command led: controls the various LEDs 0..11 on the PN62 card.
*/
+++ /dev/null
-#
-# (C) Copyright 2005
-# Richard Danter, Wind River Systems
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-TEXT_END = 0xFFF40000
*
* Shell command to reset the board.
*/
-void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf( "Resetting...\n" );
_start();
/* Should never get here */
- while(1);
+ while(1)
+ ;
+
+ return 1;
}
int board_eth_init(bd_t *bis)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MBX8xx boards
-#
-
-TEXT_END = 0xfe080000
DECLARE_GLOBAL_DATA_PTR;
-/* Prototypes */
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
/* predefine these here for FPGA programming (before including fpga.c) */
#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-LDSCRIPT := $(SRCTREE)/board/rsdproto/u-boot.lds
extern void eth_loopback_test(void);
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
#include "clkinit.h"
#include "ioconfig.h" /* I/O configuration table */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void board_init_f(unsigned long bootflag)
+{
+ relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
+ CONFIG_SYS_TEXT_BASE);
+}
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Siemens SCM boards
-#
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
+#include <mtd/cfi_flash.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
{
return board_scan_options;
}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/mtd/cfi_flash.c
+ *
+ * The NOR flash devices "behind" the FPGA's (Xilinx DS617)
+ * can only be read correctly in 16bit mode. We need to emulate
+ * 8bit and 32bit reads here in the board specific code.
+ */
+u8 flash_read8(void *addr)
+{
+ u16 val = __raw_readw((void *)((u32)addr & ~1));
+
+ if ((u32)addr & 1)
+ return val;
+
+ return val >> 8;
+}
+
+u32 flash_read32(void *addr)
+{
+ return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
+}
+
+void flash_cmd_reset(flash_info_t *info)
+{
+ /*
+ * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
+ * needs the Spansion type reset commands. The other flash chip
+ * is located behind a FPGA (Xilinx DS617) and needs the Intel type
+ * reset command.
+ */
+ if (info->start[0] == CONFIG_SYS_FLASH_BASE)
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+ else
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
LIB = $(obj)lib$(BOARD).o
-COBJS := sdp.o
+COBJS := sdp.o cmd_bat.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_BAT
+#include <twl6030.h>
+
+int do_vbat(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc == 2) {
+ if (strncmp(argv[1], "startcharge", 12) == 0)
+ twl6030_start_usb_charging();
+ else if (strncmp(argv[1], "stopcharge", 11) == 0)
+ twl6030_stop_usb_charging();
+ else if (strncmp(argv[1], "status", 7) == 0) {
+ twl6030_get_battery_voltage();
+ twl6030_get_battery_current();
+ } else {
+ goto bat_cmd_usage;
+ }
+ } else {
+ goto bat_cmd_usage;
+ }
+ return 0;
+
+bat_cmd_usage:
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ bat, 2, 1, do_vbat,
+ "battery charging, voltage/current measurements",
+ "status - display battery voltage and current\n"
+ "bat startcharge - start charging via USB\n"
+ "bat stopcharge - stop charging\n"
+);
+#endif /* CONFIG_BAT_CMD */
* MA 02111-1307 USA
*/
#include <common.h>
+#include <twl6030.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
*/
int misc_init_r(void)
{
+#ifdef CONFIG_TWL6030_POWER
+ twl6030_init_battery_charging();
+#endif
return 0;
}
void ps2mult_early_init(void);
#endif
+#if defined(CONFIG_VIDEO)
+/*
+ * EDID block has been generated using Phoenix EDID Designer 1.3.
+ * This tool creates a text file containing:
+ *
+ * EDID BYTES:
+ *
+ * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
+ * ------------------------------------------------
+ * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
+ * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
+ * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
+ * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
+ * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
+ * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
+ * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
+ * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
+ *
+ * Then this data has been manually converted to the char
+ * array below.
+ */
+static unsigned char edid_buf[128] = {
+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+ 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
+};
+#endif
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
# define CARRIER_NAME "CAM5200"
#elif defined(CONFIG_FO300)
# define CARRIER_NAME "FO300"
+#elif defined(CONFIG_CHARON)
+# define CARRIER_NAME "CHARON"
#else
# error "UNKNOWN"
#endif
}
#endif /* CONFIG_FO300 */
+#if defined(CONFIG_CHARON)
+#include <i2c.h>
+#include <asm/io.h>
+
+/* The TFP410 registers */
+#define TFP410_REG_VEN_ID_L 0x00
+#define TFP410_REG_VEN_ID_H 0x01
+#define TFP410_REG_DEV_ID_L 0x02
+#define TFP410_REG_DEV_ID_H 0x03
+#define TFP410_REG_REV_ID 0x04
+
+#define TFP410_REG_CTL_1_MODE 0x08
+#define TFP410_REG_CTL_2_MODE 0x09
+#define TFP410_REG_CTL_3_MODE 0x0A
+
+#define TFP410_REG_CFG 0x0B
+
+#define TFP410_REG_DE_DLY 0x32
+#define TFP410_REG_DE_CTL 0x33
+#define TFP410_REG_DE_TOP 0x34
+#define TFP410_REG_DE_CNT_L 0x36
+#define TFP410_REG_DE_CNT_H 0x37
+#define TFP410_REG_DE_LIN_L 0x38
+#define TFP410_REG_DE_LIN_H 0x39
+
+#define TFP410_REG_H_RES_L 0x3A
+#define TFP410_REG_H_RES_H 0x3B
+#define TFP410_REG_V_RES_L 0x3C
+#define TFP410_REG_V_RES_H 0x3D
+
+static int tfp410_read_reg(int reg, uchar *buf)
+{
+ if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
+ puts ("Error reading the chip.\n");
+ return 1;
+ }
+ return 0;
+}
+
+static int tfp410_write_reg(int reg, uchar buf)
+{
+ if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
+ puts ("Error writing the chip.\n");
+ return 1;
+ }
+ return 0;
+}
+
+typedef struct _tfp410_config {
+ int reg;
+ uchar val;
+}TFP410_CONFIG;
+
+static TFP410_CONFIG tfp410_configtbl[] = {
+ {TFP410_REG_CTL_1_MODE, 0x37},
+ {TFP410_REG_CTL_2_MODE, 0x20},
+ {TFP410_REG_CTL_3_MODE, 0x80},
+ {TFP410_REG_DE_DLY, 0x90},
+ {TFP410_REG_DE_CTL, 0x00},
+ {TFP410_REG_DE_TOP, 0x23},
+ {TFP410_REG_DE_CNT_H, 0x02},
+ {TFP410_REG_DE_CNT_L, 0x80},
+ {TFP410_REG_DE_LIN_H, 0x01},
+ {TFP410_REG_DE_LIN_L, 0xe0},
+ {-1, 0},
+};
+
+static int charon_last_stage_init(void)
+{
+ volatile struct mpc5xxx_lpb *lpb =
+ (struct mpc5xxx_lpb *) MPC5XXX_LPB;
+ int oldbus = i2c_get_bus_num();
+ uchar buf;
+ int i = 0;
+
+ i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
+
+ /* check version */
+ if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
+ return -1;
+ if (!(buf & 0x04))
+ return -1;
+ if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
+ return -1;
+ if (!(buf & 0x10))
+ return -1;
+ /* OK, now init the chip */
+ while (tfp410_configtbl[i].reg != -1) {
+ int ret;
+
+ ret = tfp410_write_reg(tfp410_configtbl[i].reg,
+ tfp410_configtbl[i].val);
+ if (ret != 0)
+ return -1;
+ i++;
+ }
+ printf("TFP410 initialized.\n");
+ i2c_set_bus_num(oldbus);
+
+ /* set deadcycle for cs3 to 0 */
+ setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
+ return 0;
+}
+#endif
+
int last_stage_init (void)
{
/*
#endif
#endif /* !CONFIG_TQM5200S */
+#if defined(CONFIG_CHARON)
+ charon_last_stage_init();
+#endif
return 0;
}
{
if (line_number == 1) {
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
+#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
+ defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
} else if (line_number == 2) {
+#if defined (CONFIG_CHARON)
+ strcpy (info, " on a CHARON carrier board");
+#endif
#if defined (CONFIG_STK52XX)
strcpy (info, " on a STK52xx carrier board");
#endif
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+#if defined(CONFIG_VIDEO)
+ fdt_add_edid(blob, "smi,sm501", edid_buf);
+#endif
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#if defined(CONFIG_RESET_PHY_R)
+#include <miiphy.h>
+
+void reset_phy(void)
+{
+ /* init Micrel KSZ8993 PHY */
+ miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
+}
+#endif
+
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis); /* Built in FEC comes first */
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8260 boards
-#
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8272 boards
-#
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
-void do_reset (void)
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_SYS_GPIO_0
*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
puts ("Reseting board\n");
asm ("bra r0");
#endif
+ return 0;
}
int gpio_init (void)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
$(call cmd_link_o_target, $^)
clean:
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start)
-
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
$(call cmd_link_o_target, $^)
clean:
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start_440)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start_440)
-
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
ulong flash_get_size(ulong base, int banknum);
void env_crc_update(void);
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
static u32 start_time;
netstar arm arm925t
voiceblue arm arm925t
omap1510inn arm arm925t - ti
+aspenite arm arm926ejs - Marvell armada100
afeb9260 arm arm926ejs - - at91
at91cap9adk arm arm926ejs - atmel at91
top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000
pm9263 arm arm926ejs - ronetix at91
da830evm arm arm926ejs da8xxevm davinci davinci
da850evm arm arm926ejs da8xxevm davinci davinci
+hawkboard arm arm926ejs da8xxevm davinci davinci
+hawkboard_nand arm arm926ejs da8xxevm davinci davinci hawkboard:NAND_U_BOOT
+hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT
+ea20 arm arm926ejs ea20 davinci davinci
davinci_dm355evm arm arm926ejs dm355evm davinci davinci
davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci
davinci_dm365evm arm arm926ejs dm365evm davinci davinci
aev powerpc mpc5xxx tqm5200 tqc
cam5200 powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B
cam5200_niosflash powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH
+charon powerpc mpc5xxx tqm5200 tqc - charon
fo300 powerpc mpc5xxx tqm5200 tqc - TQM5200:FO300
MiniFAP powerpc mpc5xxx tqm5200 tqc - TQM5200:MINIFAP
TB5200 powerpc mpc5xxx tqm5200 tqc
yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE
yucca powerpc ppc4xx - amcc
AP1000 powerpc ppc4xx ap1000 amirix
-fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x03000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds
-fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xFFCB0000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds
-v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x03000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds
-v5fx30teval_flash powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0xFF1C0000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds
+fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o
+fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o
+v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
+v5fx30teval_flash powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o
CRAYL1 powerpc ppc4xx L1 cray
CATcenter powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1
CATcenter_25 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25
KAREF powerpc ppc4xx karef sandburst
METROBOX powerpc ppc4xx metrobox sandburst
xpedite1000 powerpc ppc4xx - xes
-ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds
-ml507_flash powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0xFE360000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds
-xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds
-xilinx-ppc405-generic_flash powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0xFE360000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds
-xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds
-xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0xFE360000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds
+ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
+ml507_flash powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o
+xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC
+xilinx-ppc405-generic_flash powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC
+xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1
+xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC
rsk7203 sh sh2 rsk7203 renesas -
mpr2 sh sh3 mpr2 - -
ms7720se sh sh3 ms7720se - -
" passing 'arg' as arguments"
);
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
U_BOOT_CMD(
reset, 1, 0, do_reset,
"Perform RESET of the CPU",
static void *boot_get_kernel (cmd_tbl_t *cmdtp, int flag,int argc, char * const argv[],
bootm_headers_t *images, ulong *os_data, ulong *os_len);
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/*
* Continue booting an OS image; caller already has:
DECLARE_GLOBAL_DATA_PTR;
-const char *weekdays[] = {
+static const char * const weekdays[] = {
"Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur",
};
#define RELOC(a) a
#endif
-int mk_date (char *, struct rtc_time *);
+int mk_date (const char *, struct rtc_time *);
int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/*
* simple conversion of two-digit string with error checking
*/
-static int cnvrt2 (char *str, int *valp)
+static int cnvrt2 (const char *str, int *valp)
{
int val;
* Some basic checking for valid values is done, but this will not catch
* all possible error conditions.
*/
-int mk_date (char *datestr, struct rtc_time *tmp)
+int mk_date (const char *datestr, struct rtc_time *tmp)
{
int len, val;
char *ptr;
image_header_t *hdr; /* used for fdc boot */
unsigned char boot_drive;
int i,nrofblk;
- char *ep;
int rcode = 0;
#if defined(CONFIG_FIT)
const void *fit_hdr = NULL;
load_addr = addr;
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
size, load_addr);
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
printf ("Automatic boot of image at addr 0x%08lX ...\n", load_addr);
load_addr = addr;
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
typedef struct op_tbl_s op_tbl_t;
-op_tbl_t op_table [] = {
+static const op_tbl_t op_table [] = {
{ "-lt", LT },
{ "<" , LT },
{ "-gt", GT },
{ "<=" , LE },
};
-#define op_tbl_size (sizeof(op_table)/sizeof(op_table[0]))
-
static long evalexp(char *s, int w)
{
long l = 0;
int binary_test (char *op, char *arg1, char *arg2, int w)
{
int len, i;
- op_tbl_t *optp;
+ const op_tbl_t *optp;
len = strlen(op);
for (optp = (op_tbl_t *)&op_table, i = 0;
- i < op_tbl_size;
+ i < ARRAY_SIZE(op_table);
optp++, i++) {
if ((strncmp (op, optp->op, len) == 0) && (len == strlen (optp->op))) {
char * name;
} MII_reg_desc_t;
-MII_reg_desc_t reg_0_5_desc_tbl[] = {
+static const MII_reg_desc_t reg_0_5_desc_tbl[] = {
{ 0, "PHY control register" },
{ 1, "PHY status register" },
{ 2, "PHY ID 1 register" },
char * name;
} MII_field_desc_t;
-MII_field_desc_t reg_0_desc_tbl[] = {
+static const MII_field_desc_t reg_0_desc_tbl[] = {
{ 15, 15, 0x01, "reset" },
{ 14, 14, 0x01, "loopback" },
{ 13, 6, 0x81, "speed selection" }, /* special */
{ 5, 0, 0x3f, "(reserved)" }
};
-MII_field_desc_t reg_1_desc_tbl[] = {
+static const MII_field_desc_t reg_1_desc_tbl[] = {
{ 15, 15, 0x01, "100BASE-T4 able" },
{ 14, 14, 0x01, "100BASE-X full duplex able" },
{ 13, 13, 0x01, "100BASE-X half duplex able" },
{ 0, 0, 0x01, "extended capabilities" },
};
-MII_field_desc_t reg_2_desc_tbl[] = {
+static const MII_field_desc_t reg_2_desc_tbl[] = {
{ 15, 0, 0xffff, "OUI portion" },
};
-MII_field_desc_t reg_3_desc_tbl[] = {
+static const MII_field_desc_t reg_3_desc_tbl[] = {
{ 15, 10, 0x3f, "OUI portion" },
{ 9, 4, 0x3f, "manufacturer part number" },
{ 3, 0, 0x0f, "manufacturer rev. number" },
};
-MII_field_desc_t reg_4_desc_tbl[] = {
+static const MII_field_desc_t reg_4_desc_tbl[] = {
{ 15, 15, 0x01, "next page able" },
{ 14, 14, 0x01, "reserved" },
{ 13, 13, 0x01, "remote fault" },
{ 4, 0, 0x1f, "xxx to do" },
};
-MII_field_desc_t reg_5_desc_tbl[] = {
+static const MII_field_desc_t reg_5_desc_tbl[] = {
{ 15, 15, 0x01, "next page able" },
{ 14, 14, 0x01, "acknowledge" },
{ 13, 13, 0x01, "remote fault" },
{ 5, 5, 0x01, "10BASE-T able" },
{ 4, 0, 0x1f, "xxx to do" },
};
-
-#define DESC0LEN (sizeof(reg_0_desc_tbl)/sizeof(reg_0_desc_tbl[0]))
-#define DESC1LEN (sizeof(reg_1_desc_tbl)/sizeof(reg_1_desc_tbl[0]))
-#define DESC2LEN (sizeof(reg_2_desc_tbl)/sizeof(reg_2_desc_tbl[0]))
-#define DESC3LEN (sizeof(reg_3_desc_tbl)/sizeof(reg_3_desc_tbl[0]))
-#define DESC4LEN (sizeof(reg_4_desc_tbl)/sizeof(reg_4_desc_tbl[0]))
-#define DESC5LEN (sizeof(reg_5_desc_tbl)/sizeof(reg_5_desc_tbl[0]))
-
typedef struct _MII_field_desc_and_len_t {
- MII_field_desc_t * pdesc;
+ const MII_field_desc_t *pdesc;
ushort len;
} MII_field_desc_and_len_t;
-MII_field_desc_and_len_t desc_and_len_tbl[] = {
- { reg_0_desc_tbl, DESC0LEN },
- { reg_1_desc_tbl, DESC1LEN },
- { reg_2_desc_tbl, DESC2LEN },
- { reg_3_desc_tbl, DESC3LEN },
- { reg_4_desc_tbl, DESC4LEN },
- { reg_5_desc_tbl, DESC5LEN },
+static const MII_field_desc_and_len_t desc_and_len_tbl[] = {
+ { reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl) },
+ { reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl) },
+ { reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl) },
+ { reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl) },
+ { reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl) },
+ { reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl) },
};
static void dump_reg(
ushort regval,
- MII_reg_desc_t * prd,
- MII_field_desc_and_len_t * pdl);
+ const MII_reg_desc_t *prd,
+ const MII_field_desc_and_len_t *pdl);
static int special_field(
ushort regno,
- MII_field_desc_t * pdesc,
+ const MII_field_desc_t *pdesc,
ushort regval);
-void MII_dump_0_to_5(
+static void MII_dump_0_to_5(
ushort regvals[6],
uchar reglo,
uchar reghi)
static void dump_reg(
ushort regval,
- MII_reg_desc_t * prd,
- MII_field_desc_and_len_t * pdl)
+ const MII_reg_desc_t *prd,
+ const MII_field_desc_and_len_t *pdl)
{
ulong i;
ushort mask_in_place;
- MII_field_desc_t * pdesc;
+ const MII_field_desc_t *pdesc;
printf("%u. (%04hx) -- %s --\n",
prd->regno, regval, prd->name);
static int special_field(
ushort regno,
- MII_field_desc_t * pdesc,
+ const MII_field_desc_t *pdesc,
ushort regval)
{
if ((regno == 0) && (pdesc->lo == 6)) {
return 0;
}
-char last_op[2];
-uint last_data;
-uint last_addr_lo;
-uint last_addr_hi;
-uint last_reg_lo;
-uint last_reg_hi;
+static char last_op[2];
+static uint last_data;
+static uint last_addr_lo;
+static uint last_addr_hi;
+static uint last_reg_lo;
+static uint last_reg_hi;
static void extract_range(
char * input,
}
/* ---------------------------------------------------------------- */
-int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char op[2];
unsigned char addrlo, addrhi, reglo, reghi;
ulong offset, ulong addr, char *cmd)
{
int r;
- char *ep, *s;
+ char *s;
size_t cnt;
image_header_t *hdr;
#if defined(CONFIG_FIT)
load_addr = addr;
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
local_args[0] = cmd;
local_args[1] = NULL;
#include <command.h>
#include <net.h>
-extern int do_bootm (cmd_tbl_t *, int, int, char * const []);
-
static int netboot_common (proto_t, cmd_tbl_t *, int , char * const []);
int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
flush_cache(load_addr, size);
/* Loading ok, check if we should attempt an auto-start */
- if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
local_args[0] = argv[0];
local_args[1] = NULL;
e.key = name;
e.data = NULL;
- ep = hsearch (e, FIND);
+ hsearch_r(e, FIND, &ep, &env_htab);
if (ep == NULL)
return 0;
len = printf ("%s=%s\n", ep->key, ep->data);
}
/* print whole list */
- len = hexport('\n', &res, 0);
+ len = hexport_r(&env_htab, '\n', &res, 0);
if (len > 0) {
puts(res);
*/
e.key = name;
e.data = NULL;
- ep = hsearch (e, FIND);
+ hsearch_r(e, FIND, &ep, &env_htab);
/* Check for console redirection */
if (strcmp(name,"stdin") == 0) {
/* Delete only ? */
if ((argc < 3) || argv[2] == NULL) {
- int rc = hdelete(name);
+ int rc = hdelete_r(name, &env_htab);
return !rc;
}
e.key = name;
e.data = value;
- ep = hsearch(e, ENTER);
+ hsearch_r(e, ENTER, &ep, &env_htab);
free(value);
if (!ep) {
printf("## Error inserting \"%s\" variable, errno=%d\n",
e.key = name;
e.data = NULL;
- ep = hsearch (e, FIND);
+ hsearch_r(e, FIND, &ep, &env_htab);
return (ep ? ep->data : NULL);
}
}
if (sep) { /* export as text file */
- len = hexport(sep, &addr, size);
+ len = hexport_r(&env_htab, sep, &addr, size);
if (len < 0) {
error("Cannot export environment: errno = %d\n",
errno);
else /* export as raw binary data */
res = addr;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n",
errno);
addr = (char *)ep->data;
}
- if (himport(addr, size, sep, del ? 0 : H_NOCLEAR) == 0) {
+ if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR) == 0) {
error("Environment import failed: errno = %d\n", errno);
return 1;
}
*/
#if defined(CONFIG_CMD_EDITENV)
-U_BOOT_CMD(
+U_BOOT_CMD_COMPLETE(
editenv, 2, 0, do_env_edit,
"edit environment variable",
"name\n"
- " - edit environment variable 'name'"
+ " - edit environment variable 'name'",
+ var_complete
);
#endif
-U_BOOT_CMD(
+U_BOOT_CMD_COMPLETE(
printenv, CONFIG_SYS_MAXARGS, 1, do_env_print,
"print environment variables",
"\n - print values of all environment variables\n"
"printenv name ...\n"
- " - print value of environment variable 'name'"
+ " - print value of environment variable 'name'",
+ var_complete
);
-U_BOOT_CMD(
+U_BOOT_CMD_COMPLETE(
setenv, CONFIG_SYS_MAXARGS, 0, do_env_set,
"set environment variables",
"name value ...\n"
" - set environment variable 'name' to 'value ...'\n"
"setenv name\n"
- " - delete environment variable 'name'"
+ " - delete environment variable 'name'",
+ var_complete
);
#if defined(CONFIG_CMD_ASKENV)
#endif
#if defined(CONFIG_CMD_RUN)
-U_BOOT_CMD(
+U_BOOT_CMD_COMPLETE(
run, CONFIG_SYS_MAXARGS, 1, do_run,
"run commands in an environment variable",
"var [...]\n"
- " - run the commands in the environment variable(s) 'var'"
+ " - run the commands in the environment variable(s) 'var'",
+ var_complete
);
#endif
return 0;
}
+static int onenand_write_oneblock_withoob(loff_t to, const u_char * buf,
+ size_t *retlen)
+{
+ struct mtd_oob_ops ops = {
+ .len = mtd->writesize,
+ .ooblen = mtd->oobsize,
+ .mode = MTD_OOB_AUTO,
+ };
+ int page, ret = 0;
+ for (page = 0; page < (mtd->erasesize / mtd->writesize); page ++) {
+ ops.datbuf = (u_char *)buf;
+ buf += mtd->writesize;
+ ops.oobbuf = (u_char *)buf;
+ buf += mtd->oobsize;
+ ret = mtd->write_oob(mtd, to, &ops);
+ if (ret)
+ break;
+ to += mtd->writesize;
+ }
+
+ *retlen = (ret) ? 0 : mtd->erasesize;
+ return ret;
+}
+
static int onenand_block_write(loff_t to, size_t len,
- size_t *retlen, const u_char * buf)
+ size_t *retlen, const u_char * buf, int withoob)
{
struct onenand_chip *this = mtd->priv;
int blocks = len >> this->erase_shift;
goto next;
}
- ret = mtd->write(mtd, ofs, blocksize, &_retlen, buf);
+ if (!withoob)
+ ret = mtd->write(mtd, ofs, blocksize, &_retlen, buf);
+ else
+ ret = onenand_write_oneblock_withoob(ofs, buf, &_retlen);
if (ret) {
printk("Write failed 0x%x, %d", (u32)ofs, ret);
skip_ofs += blocksize;
{
ulong addr, ofs;
size_t len;
- int ret = 0;
+ int ret = 0, withoob = 0;
size_t retlen = 0;
if (argc < 3)
return cmd_usage(cmdtp);
+ if (strncmp(argv[0] + 6, "yaffs", 5) == 0)
+ withoob = 1;
+
addr = (ulong)simple_strtoul(argv[1], NULL, 16);
printf("\nOneNAND write: ");
if (arg_off_size(argc - 2, argv + 2, &ofs, &len) != 0)
return 1;
- ret = onenand_block_write(ofs, len, &retlen, (u8 *)addr);
+ ret = onenand_block_write(ofs, len, &retlen, (u8 *)addr, withoob);
printf(" %d bytes written: %s\n", retlen, ret ? "ERROR" : "OK");
U_BOOT_CMD_MKENT(bad, 1, 0, do_onenand_bad, "", ""),
U_BOOT_CMD_MKENT(read, 4, 0, do_onenand_read, "", ""),
U_BOOT_CMD_MKENT(write, 4, 0, do_onenand_write, "", ""),
+ U_BOOT_CMD_MKENT(write.yaffs, 4, 0, do_onenand_write, "", ""),
U_BOOT_CMD_MKENT(erase, 3, 0, do_onenand_erase, "", ""),
U_BOOT_CMD_MKENT(test, 3, 0, do_onenand_test, "", ""),
U_BOOT_CMD_MKENT(dump, 2, 0, do_onenand_dump, "", ""),
"info - show available OneNAND devices\n"
"onenand bad - show bad blocks\n"
"onenand read[.oob] addr off size\n"
- "onenand write addr off size\n"
+ "onenand write[.yaffs] addr off size\n"
" read/write 'size' bytes starting at offset 'off'\n"
" to/from memory address 'addr', skipping bad blocks.\n"
"onenand erase [force] [off size] - erase 'size' bytes from\n"
flush_cache (addr, (cnt+1)*info.blksz);
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
printf ("Automatic boot of image at addr 0x%08lX ...\n", addr);
flush_cache(addr, (cnt+1)*info.blksz);
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
printf("Automatic boot of image at addr 0x%08lX ...\n", addr);
return 0;
}
-static void install_auto_complete_handler(const char *cmd,
- int (*complete)(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]))
-{
- cmd_tbl_t *cmdtp;
-
- cmdtp = find_cmd(cmd);
- if (cmdtp == NULL)
- return;
-
- cmdtp->complete = complete;
-}
-
-void install_auto_complete(void)
-{
-#if defined(CONFIG_CMD_EDITENV)
- install_auto_complete_handler("editenv", var_complete);
-#endif
- install_auto_complete_handler("printenv", var_complete);
- install_auto_complete_handler("setenv", var_complete);
-#if defined(CONFIG_CMD_RUN)
- install_auto_complete_handler("run", var_complete);
-#endif
-}
-
/*************************************************************************************/
static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[])
/** U-Boot INIT FUNCTIONS *************************************************/
-struct stdio_dev *search_device(int flags, char *name)
+struct stdio_dev *search_device(int flags, const char *name)
{
struct stdio_dev *dev;
return NULL;
}
-int console_assign(int file, char *devname)
+int console_assign(int file, const char *devname)
{
int flag;
struct stdio_dev *dev;
"\0"
};
+struct hsearch_data env_htab;
+
static uchar env_get_char_init (int index)
{
uchar c;
puts("Using default environment\n\n");
}
- if (himport((char *)default_environment,
+ if (himport_r(&env_htab, (char *)default_environment,
sizeof(default_environment), '\0', 0) == 0) {
error("Environment import failed: errno = %d\n", errno);
}
}
}
- if (himport((char *)ep->data, ENV_SIZE, '\0', 0)) {
+ if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0)) {
gd->flags |= GD_FLG_ENV_READY;
return 1;
}
char *res;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
BUG_ON(env_ptr != NULL);
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
goto done;
goto done;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
goto done;
return 1;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
return 1;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
return 1;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
int rcode = 0;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
};
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
goto done;
#include <common.h> /* readline */
#include <hush.h>
#include <command.h> /* find_cmd */
-/*cmd_boot.c*/
-extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); /* do_bootd */
#endif
#ifndef __U_BOOT__
#include <ctype.h> /* isalpha, isdigit */
static char the_command[CONFIG_SYS_CBSIZE];
#ifdef CONFIG_BOOT_RETRY_TIME
-# ifdef CONFIG_RESET_TO_RETRY
- extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-# else
+# ifndef CONFIG_RESET_TO_RETRY
# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
# endif
reset_cmd_timeout();
} else {
int rcode;
#if defined(CONFIG_CMD_BOOTD)
- extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
/* avoid "bootd" recursion */
if (cmdtp->cmd == do_bootd) {
if (flag & CMD_FLAG_BOOTD) {
#include <image.h>
#endif /* !USE_HOSTCC*/
-static table_entry_t uimage_arch[] = {
+static const table_entry_t uimage_arch[] = {
{ IH_ARCH_INVALID, NULL, "Invalid ARCH", },
{ IH_ARCH_ALPHA, "alpha", "Alpha", },
{ IH_ARCH_ARM, "arm", "ARM", },
{ -1, "", "", },
};
-static table_entry_t uimage_os[] = {
+static const table_entry_t uimage_os[] = {
{ IH_OS_INVALID, NULL, "Invalid OS", },
{ IH_OS_LINUX, "linux", "Linux", },
#if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC)
{ -1, "", "", },
};
-static table_entry_t uimage_type[] = {
+static const table_entry_t uimage_type[] = {
{ IH_TYPE_INVALID, NULL, "Invalid Image", },
{ IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image", },
{ IH_TYPE_FIRMWARE, "firmware", "Firmware", },
{ -1, "", "", },
};
-static table_entry_t uimage_comp[] = {
+static const table_entry_t uimage_comp[] = {
{ IH_COMP_NONE, "none", "uncompressed", },
{ IH_COMP_BZIP2, "bzip2", "bzip2 compressed", },
{ IH_COMP_GZIP, "gzip", "gzip compressed", },
* long entry name if translation succeeds
* msg otherwise
*/
-char *get_table_entry_name (table_entry_t *table, char *msg, int id)
+char *get_table_entry_name(const table_entry_t *table, char *msg, int id)
{
for (; table->id >= 0; ++table) {
if (table->id == id)
* entry id if translation succeeds
* -1 otherwise
*/
-int get_table_entry_id (table_entry_t *table,
+int get_table_entry_id(const table_entry_t *table,
const char *table_name, const char *name)
{
- table_entry_t *t;
+ const table_entry_t *t;
#ifdef USE_HOSTCC
int first = 1;
void inline __show_boot_progress (int val) {}
void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
-#if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY)
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); /* for do_reset() prototype */
-#endif
-
-extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
#if defined(CONFIG_UPDATE_TFTP)
void update_tftp (void);
#endif /* CONFIG_UPDATE_TFTP */
hush_init_var ();
#endif
-#ifdef CONFIG_AUTO_COMPLETE
- install_auto_complete();
-#endif
-
#ifdef CONFIG_PREBOOT
if ((p = getenv ("preboot")) != NULL) {
# ifdef CONFIG_AUTOBOOT_KEYED
return &(devs.list);
}
-struct stdio_dev* stdio_get_by_name(char* name)
+struct stdio_dev* stdio_get_by_name(const char *name)
{
struct list_head *pos;
struct stdio_dev *dev;
* returns 0 if success, -1 if device is assigned and 1 if devname not found
*/
#ifdef CONFIG_SYS_STDIO_DEREGISTER
-int stdio_deregister(char *devname)
+int stdio_deregister(const char *devname)
{
int l;
struct list_head *pos;
# Allow boards to use custom optimize flags on a per dir/file basis
BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%))
+ALL_AFLAGS = $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR))
+ALL_CFLAGS = $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR))
$(obj)%.s: %.S
- $(CPP) $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) \
- -o $@ $<
+ $(CPP) $(ALL_AFLAGS) -o $@ $<
$(obj)%.o: %.S
- $(CC) $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) \
- -o $@ $< -c
+ $(CC) $(ALL_AFLAGS) -o $@ $< -c
$(obj)%.o: %.c
- $(CC) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ $< -c
+ $(CC) $(ALL_CFLAGS) -o $@ $< -c
$(obj)%.i: %.c
- $(CPP) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ $< -c
+ $(CPP) $(ALL_CFLAGS) -o $@ $< -c
$(obj)%.s: %.c
- $(CC) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ $< -c -S
+ $(CC) $(ALL_CFLAGS) -o $@ $< -c -S
#########################################################################
--- /dev/null
+Summary
+=======
+The README is for the boot procedure used for TI's OMAP-L138 based
+hawkboard. The hawkboard comes with a 128MiB Nand flash and a 128MiB
+DDR SDRAM along with a host of other controllers.
+
+The hawkboard is booted in three stages. The initial bootloader which
+executes upon reset is the Rom Boot Loader(RBL) which sits in the
+internal ROM of the omap. The RBL initialises the memory and the nand
+controller, and copies the image stored at a predefined location(block
+1) of the nand flash. The image loaded by the RBL to the memory is the
+AIS signed nand_spl image. This, in turns copies the u-boot binary
+from the nand flash to the memory and jumps to the u-boot entry point.
+
+AIS is an image format defined by TI for the images that are to be
+loaded to memory by the RBL. The image is divided into a series of
+sections and the image's entry point is specified. Each section comes
+with meta data like the target address the section is to be copied to
+and the size of the section, which is used by the RBL to load the
+image. At the end of the image the RBL jumps to the image entry
+point.
+
+The secondary stage bootloader(nand_spl) which is loaded by the RBL
+then loads the u-boot from a predefined location in the nand to the
+memory and jumps to the u-boot entry point.
+
+The reason a secondary stage bootloader is used is because the ECC
+layout expected by the RBL is not the same as that used by
+u-boot/linux. This also implies that for flashing the nand_spl image,
+we need to use the u-boot which uses the ECC layout expected by the
+RBL[1]. Booting u-boot over UART(UART boot) is explained here[2].
+
+
+Compilation
+===========
+Three images might be needed
+
+* nand_spl - This is the secondary bootloader which boots the u-boot
+ binary.
+
+ hawkboard_nand_config
+
+ The nand_spl ELF gets generated under nand_spl/u-boot-spl. This
+ needs to be processed with the AISGen tool for generating the AIS
+ signed image to be flashed. Steps for generating the AIS image are
+ explained here[3].
+
+* u-boot binary - This is the image flashed to the nand and copied to
+ the memory by the nand_spl.
+
+ hawkboard_config
+
+* u-boot for uart boot - This is same as the u-boot binary generated
+ above, with the sole difference of the CONFIG_SYS_TEXT_BASE being
+ 0xc1080000, as expected by the RBL.
+
+ hawkboard_uart_config
+
+
+Flashing the images to Nand
+===========================
+The nand_spl AIS image needs to be flashed to the block 1 of the
+Nand flash, as that is the location the RBL expects the image[4]. For
+flashing the nand_spl, boot over the u-boot specified in [1], and
+flash the image
+
+=> tftpboot 0xc0700000 <nand_spl_ais.bin>
+=> nand erase 0x20000 0x20000
+=> nand write.e 0xc0700000 0x20000 <nand_spl_size>
+
+The u-boot binary is flashed at location 0xe0000(block 6) of the nand
+flash. The nand_spl loader expects the u-boot at this location. For
+flashing the u-boot binary
+
+=> tftpboot 0xc0700000 u-boot.bin
+=> nand erase 0xe0000 0x40000
+=> nand write.e 0xc0700000 0xe0000 <u-boot-size>
+
+
+Links
+=====
+
+[1]
+ http://code.google.com/p/hawkboard/downloads/detail?name=u-boot_uart_ais_v1.bin
+
+[2]
+ http://elinux.org/Hawkboard#Booting_u-boot_over_UART
+
+[3]
+ http://elinux.org/Hawkboard#Signing_u-boot_for_UART_boot
+
+[4]
+ http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program#RBL_booting_from_NAND_and_ECC.2FBad_blocks
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
+ if (*fn->abort)
+ (*fn->abort) (cookie);
return FPGA_FAIL;
}
} while (!(*fn->init) (cookie));
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
+ if (*fn->abort)
+ (*fn->abort) (cookie);
return FPGA_FAIL;
}
} while ((*fn->init) (cookie));
while DONE is low (inactive) */
if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
puts ("** CRC error during FPGA load.\n");
+ if (*fn->abort)
+ (*fn->abort) (cookie);
return (FPGA_FAIL);
}
val = data [bytecount ++];
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
+COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
COBJS-$(CONFIG_S5P) += s5p_gpio.o
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#ifdef CONFIG_ARMADA100
+#include <asm/arch/armada100.h>
+#else
+#error Unsupported SoC...
+#endif
+
+/*
+ * mfp_config
+ *
+ * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
+ * configuration registers to configure each GPIO/Function pin on the
+ * SoC.
+ *
+ * This function reads the array of values for
+ * MFPR_X registers and programms them into respective
+ * Multi-Function Pin registers.
+ * It supports - Alternate Function Selection programming.
+ *
+ * Whereas,
+ * The Configureation value is constructed using MFP()
+ * array consists of 32bit values as defined in MFP(xx,xx..) macro
+ */
+void mfp_config(u32 *mfp_cfgs)
+{
+ u32 *p_mfpr = NULL;
+ u32 cfg_val, val;
+
+ do {
+ cfg_val = *mfp_cfgs++;
+ /* exit if End of configuration table detected */
+ if (cfg_val == MFP_EOC)
+ break;
+
+ p_mfpr = (u32 *)(MV_MFPR_BASE
+ + MFP_REG_GET_OFFSET(cfg_val));
+
+ /* Write a mfg register as per configuration */
+ val = 0;
+ if (cfg_val & MFP_AF_FLAG)
+ /* Abstract and program Afternate-Func Selection */
+ val |= cfg_val & MFP_AF_MASK;
+ if (cfg_val & MFP_EDGE_FLAG)
+ /* Abstract and program Edge configuration */
+ val |= cfg_val & MFP_LPM_EDGE_MASK;
+ if (cfg_val & MFP_DRIVE_FLAG)
+ /* Abstract and program Drive configuration */
+ val |= cfg_val & MFP_DRIVE_MASK;
+ if (cfg_val & MFP_PULL_FLAG)
+ /* Abstract and program Pullup/down configuration */
+ val |= cfg_val & MFP_PULL_MASK;
+
+ writel(val, p_mfpr);
+ } while (1);
+ /*
+ * perform a read-back of any MFPR register to make sure the
+ * previous writings are finished
+ */
+ readl(p_mfpr);
+}
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#endif
+/*
+ * 0xffff is an undefined value for the configuration register. When
+ * this value is returned, the configuration register shall not be
+ * written at all (default mode).
+ */
+static u16 cfi_flash_config_reg(int i)
+{
+#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
+ return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i];
+#else
+ return 0xffff;
+#endif
+}
+
#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
#endif
{
int k;
int size;
- volatile unsigned long *flash;
+ u32 *flash;
/*
* Check if whole sector is erased
*/
size = flash_sector_size(info, i);
- flash = (volatile unsigned long *) info->start[i];
+ flash = (u32 *)info->start[i];
/* divide by 4 for longword access */
size = size >> 2;
for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff)
+ if (flash_read32(flash++) != 0xffffffff)
return 0; /* not erased */
}
#endif
};
+ /*
+ * Flash needs to be in status register read mode for
+ * flash_full_status_check() to work correctly
+ */
+ flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
if ((retcode =
flash_full_status_check (info, sector, info->erase_blk_tout,
prot ? "protect" : "unprotect")) == 0) {
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_EXTENDED:
case CFI_CMDSET_INTEL_STANDARD:
+ /*
+ * Set flash to read-id mode. Otherwise
+ * reading protected status is not
+ * guaranteed.
+ */
+ flash_write_cmd(info, sect_cnt, 0,
+ FLASH_CMD_READ_ID);
info->protect[sect_cnt] =
flash_isset (info, sect_cnt,
FLASH_OFFSET_PROTECT,
flash_verbose = v;
}
+static void cfi_flash_set_config_reg(u32 base, u16 val)
+{
+#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
+ /*
+ * Only set this config register if really defined
+ * to a valid value (0xffff is invalid)
+ */
+ if (val == 0xffff)
+ return;
+
+ /*
+ * Set configuration register. Data is "encrypted" in the 16 lower
+ * address bits.
+ */
+ flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1)));
+ flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1)));
+
+ /*
+ * Finally issue reset-command to bring device back to
+ * read-array mode
+ */
+ flash_write16(FLASH_CMD_RESET, (void *)base);
+#endif
+}
+
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
+ /* Optionally write flash configuration register */
+ cfi_flash_set_config_reg(cfi_flash_bank_addr(i),
+ cfi_flash_config_reg(i));
+
if (!flash_detect_legacy(cfi_flash_bank_addr(i), i))
flash_get_size(cfi_flash_bank_addr(i), i);
size += flash_info[i].size;
{
struct nand_chip *chip = mtd->priv;
u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ u32 time_start;
- reset_timer();
+ time_start = get_timer(0);
/* wait until command is processed or timeout occures */
- while (get_timer(0) < timeo) {
+ while (get_timer(time_start) < timeo) {
if (chip->dev_ready)
if (chip->dev_ready(mtd))
break;
{
unsigned long timeo;
int state = this->state;
+ u32 time_start;
if (state == FL_ERASING)
timeo = (CONFIG_SYS_HZ * 400) / 1000;
else
this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
- reset_timer();
+ time_start = get_timer(0);
while (1) {
- if (get_timer(0) > timeo) {
+ if (get_timer(time_start) > timeo) {
printf("Timeout!");
return 0x01;
}
}
}
#ifdef PPCHAMELON_NAND_TIMER_HACK
- reset_timer();
- while (get_timer(0) < 10);
+ time_start = get_timer(0);
+ while (get_timer(time_start) < 10)
+ ;
#endif /* PPCHAMELON_NAND_TIMER_HACK */
return this->read_byte(mtd);
/*
* Get the flash and manufacturer id and lookup if the type is supported
*/
-static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
+static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
struct nand_chip *chip,
int busw, int *maf_id)
{
- struct nand_flash_dev *type = NULL;
+ const struct nand_flash_dev *type = NULL;
int i, dev_id, maf_idx;
int tmp_id, tmp_manf;
{
int i, busw, nand_maf_id;
struct nand_chip *chip = mtd->priv;
- struct nand_flash_dev *type;
+ const struct nand_flash_dev *type;
/* Get buswidth to select the correct functions */
busw = chip->options & NAND_BUSWIDTH_16;
+ 256 256 Byte page size
* 512 512 Byte page size
*/
-struct nand_flash_dev nand_flash_ids[] = {
+const struct nand_flash_dev nand_flash_ids[] = {
#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
{"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
/*
* Manufacturer ID list
*/
-struct nand_manufacturers nand_manuf_ids[] = {
+const struct nand_manufacturers nand_manuf_ids[] = {
{NAND_MFR_TOSHIBA, "Toshiba"},
{NAND_MFR_SAMSUNG, "Samsung"},
{NAND_MFR_FUJITSU, "Fujitsu"},
COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o
COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
+COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o
COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o
COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o
COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
--- /dev/null
+/*
+ * (C) Copyright 2010, ucRobotics Inc.
+ * Author: Chong Huang <chuang@ucrobotics.com>
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#include "spi_flash_internal.h"
+
+/* EN25Q128-specific commands */
+#define CMD_EN25Q128_WREN 0x06 /* Write Enable */
+#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */
+#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */
+#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */
+#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */
+#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_EN25Q128_PP 0x02 /* Page Program */
+#define CMD_EN25Q128_SE 0x20 /* Sector Erase */
+#define CMD_EN25Q128_BE 0xd8 /* Block Erase */
+#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */
+#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
+
+#define EON_ID_EN25Q128 0x18
+
+#define EON_SR_WIP (1 << 0) /* Write-in-Progress */
+
+struct eon_spi_flash_params {
+ u8 idcode1;
+ u16 page_size;
+ u16 pages_per_sector;
+ u16 sectors_per_block;
+ u16 nr_sectors;
+ const char *name;
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct eon_spi_flash {
+ struct spi_flash flash;
+ const struct eon_spi_flash_params *params;
+};
+
+static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash)
+{
+ return container_of(flash, struct eon_spi_flash, flash);
+}
+
+static const struct eon_spi_flash_params eon_spi_flash_table[] = {
+ {
+ .idcode1 = EON_ID_EN25Q128,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_sectors = 4096,
+ .name = "EN25Q128",
+ },
+};
+
+static int eon_wait_ready(struct spi_flash *flash, unsigned long timeout)
+{
+ struct spi_slave *spi = flash->spi;
+ unsigned long timebase;
+ int ret;
+ u8 cmd = CMD_EN25Q128_RDSR;
+ u8 status;
+
+ ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
+ if (ret) {
+ debug("SF: Failed to send command %02x: %d\n", cmd, ret);
+ return ret;
+ }
+
+ timebase = get_timer(0);
+ do {
+ ret = spi_xfer(spi, 8, NULL, &status, 0);
+ if (ret)
+ return -1;
+
+ if ((status & EON_SR_WIP) == 0)
+ break;
+
+ } while (get_timer(timebase) < timeout);
+
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
+
+ if ((status & EON_SR_WIP) == 0)
+ return 0;
+
+ /* Timed out */
+ return -1;
+}
+
+static int eon_read_fast(struct spi_flash *flash,
+ u32 offset, size_t len, void *buf)
+{
+ struct eon_spi_flash *eon = to_eon_spi_flash(flash);
+ unsigned long page_addr;
+ unsigned long page_size;
+ u8 cmd[5];
+
+ page_size = eon->params->page_size;
+ page_addr = offset / page_size;
+
+ cmd[0] = CMD_READ_ARRAY_FAST;
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr;
+ cmd[3] = offset % page_size;
+ cmd[4] = 0x00;
+
+ return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
+}
+
+static int eon_write(struct spi_flash *flash,
+ u32 offset, size_t len, const void *buf)
+{
+ struct eon_spi_flash *eon = to_eon_spi_flash(flash);
+ unsigned long page_addr;
+ unsigned long byte_addr;
+ unsigned long page_size;
+ size_t chunk_len;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ page_size = eon->params->page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = 0;
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[0] = CMD_EN25Q128_PP;
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ debug
+ ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
+ if (ret < 0) {
+ debug("SF: Enabling Write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ debug("SF: EON Page Program failed\n");
+ break;
+ }
+
+ ret = eon_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret < 0) {
+ debug("SF: EON page programming timed out\n");
+ break;
+ }
+
+ page_addr++;
+ byte_addr = 0;
+ }
+
+ debug("SF: EON: Successfully programmed %u bytes @ 0x%x\n",
+ len, offset);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+int eon_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ /* block erase */
+ struct eon_spi_flash *eon = to_eon_spi_flash(flash);
+ unsigned long block_size;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+
+ block_size = eon->params->page_size * eon->params->pages_per_sector
+ * eon->params->sectors_per_block;
+
+ if (offset % block_size || len % block_size) {
+ debug("SF: Erase offset/length not multiple of block size\n");
+ return -1;
+ }
+
+ len /= block_size;
+ cmd[0] = CMD_EN25Q128_BE;
+ cmd[2] = 0x00;
+ cmd[3] = 0x00;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = 0;
+ for (actual = 0; actual < len; actual++) {
+ cmd[1] = (offset / block_size) + actual;
+ ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
+ if (ret < 0) {
+ debug("SF: Enabling Write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0);
+ if (ret < 0) {
+ debug("SF: EON page erase failed\n");
+ break;
+ }
+
+ ret = eon_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+ if (ret < 0) {
+ debug("SF: EON page erase timed out\n");
+ break;
+ }
+ }
+
+ debug("SF: EON: Successfully erased %u bytes @ 0x%x\n",
+ len * block_size, offset);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode)
+{
+ const struct eon_spi_flash_params *params;
+ struct eon_spi_flash *eon;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) {
+ params = &eon_spi_flash_table[i];
+ if (params->idcode1 == idcode[2])
+ break;
+ }
+
+ if (i == ARRAY_SIZE(eon_spi_flash_table)) {
+ debug("SF: Unsupported EON ID %02x\n", idcode[1]);
+ return NULL;
+ }
+
+ eon = malloc(sizeof(*eon));
+ if (!eon) {
+ debug("SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ eon->params = params;
+ eon->flash.spi = spi;
+ eon->flash.name = params->name;
+
+ eon->flash.write = eon_write;
+ eon->flash.erase = eon_erase;
+ eon->flash.read = eon_read_fast;
+ eon->flash.size = params->page_size * params->pages_per_sector
+ * params->nr_sectors;
+
+ debug("SF: Detected %s with page size %u, total %u bytes\n",
+ params->name, params->page_size, eon->flash.size);
+
+ return &eon->flash;
+}
#ifdef CONFIG_SPI_FLASH_ATMEL
{ 0, 0x1f, spi_flash_probe_atmel, },
#endif
+#ifdef CONFIG_SPI_FLASH_EON
+ { 0, 0x1c, spi_flash_probe_eon, },
+#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX
{ 0, 0xc2, spi_flash_probe_macronix, },
#endif
/* Manufacturer-specific probe functions */
struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
#define CMD_W25_DP 0xb9 /* Deep Power-down */
#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */
-#define WINBOND_ID_W25X16 0x3015
-#define WINBOND_ID_W25X32 0x3016
-#define WINBOND_ID_W25X64 0x3017
-#define WINBOND_ID_W25Q64 0x4017
-
#define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */
struct winbond_spi_flash_params {
uint8_t l2_page_size;
uint16_t pages_per_sector;
uint16_t sectors_per_block;
- uint8_t nr_blocks;
+ uint16_t nr_blocks;
const char *name;
};
static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
{
- .id = WINBOND_ID_W25X16,
+ .id = 0x3015,
.l2_page_size = 8,
.pages_per_sector = 16,
.sectors_per_block = 16,
.name = "W25X16",
},
{
- .id = WINBOND_ID_W25X32,
+ .id = 0x3016,
.l2_page_size = 8,
.pages_per_sector = 16,
.sectors_per_block = 16,
.name = "W25X32",
},
{
- .id = WINBOND_ID_W25X64,
+ .id = 0x3017,
.l2_page_size = 8,
.pages_per_sector = 16,
.sectors_per_block = 16,
.name = "W25X64",
},
{
- .id = WINBOND_ID_W25Q64,
+ .id = 0x4015,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 32,
+ .name = "W25Q16",
+ },
+ {
+ .id = 0x4016,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 64,
+ .name = "W25Q32",
+ },
+ {
+ .id = 0x4017,
.l2_page_size = 8,
.pages_per_sector = 16,
.sectors_per_block = 16,
.nr_blocks = 128,
.name = "W25Q64",
},
+ {
+ .id = 0x4018,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 256,
+ .name = "W25Q128",
+ },
};
static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout)
{
u_int16_t tmp;
- if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04))
+ if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
+ (tmp & 0x04)) {
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ davinci_eth_phy_read(phy_addr, PHY_ANLPAR, &tmp);
+
+ /* Speed doesn't matter, there is no setting for it in EMAC. */
+ if (tmp & (PHY_ANLPAR_TXFD | PHY_ANLPAR_10FD)) {
+ /* set EMAC for Full Duplex */
+ writel(EMAC_MACCONTROL_MIIEN_ENABLE |
+ EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
+ &adap_emac->MACCONTROL);
+ } else {
+ /*set EMAC for Half Duplex */
+ writel(EMAC_MACCONTROL_MIIEN_ENABLE,
+ &adap_emac->MACCONTROL);
+ }
+
+ if (tmp & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
+ writel(readl(&adap_emac->MACCONTROL) |
+ EMAC_MACCONTROL_RMIISPEED_100,
+ &adap_emac->MACCONTROL);
+ else
+ writel(readl(&adap_emac->MACCONTROL) &
+ ~EMAC_MACCONTROL_RMIISPEED_100,
+ &adap_emac->MACCONTROL);
+#endif
return(1);
+ }
return(0);
}
}
#endif
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
+ adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
+ adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
+#endif
rx_desc = emac_rx_desc;
writel(1, &adap_emac->TXCONTROL);
writel(0, &adap_ewrap->EWCTL);
#endif
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
+ adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
+ adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
+#endif
debug_emac("- emac_close\n");
}
return i2c_read(chip_no, reg, 1, val, 1);
}
+static int twl6030_gpadc_read_channel(u8 channel_no)
+{
+ u8 lsb = 0;
+ u8 msb = 0;
+ int ret = 0;
+
+ ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &lsb,
+ GPCH0_LSB + channel_no * 2);
+ if (ret)
+ return ret;
+
+ ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &msb,
+ GPCH0_MSB + channel_no * 2);
+ if (ret)
+ return ret;
+
+ return (msb << 8) | lsb;
+}
+
+static int twl6030_gpadc_sw2_trigger(void)
+{
+ u8 val;
+ int ret = 0;
+
+ ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2_SP2, CTRL_P2);
+ if (ret)
+ return ret;
+
+ /* Waiting until the SW1 conversion ends*/
+ val = CTRL_P2_BUSY;
+
+ while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) {
+ ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &val, CTRL_P2);
+ if (ret)
+ return ret;
+ udelay(1000);
+ }
+
+ return 0;
+}
+
+void twl6030_stop_usb_charging(void)
+{
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, 0, CONTROLLER_CTRL1);
+
+ return;
+}
+
void twl6030_start_usb_charging(void)
{
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VICHRG_1500,
CHARGERUSB_INT_MASK);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VOREG_4P0,
CHARGERUSB_VOREG);
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_100,
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_400,
CHARGERUSB_CTRL2);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TERM, CHARGERUSB_CTRL1);
/* Enable USB charging */
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1_EN_CHARGER,
CONTROLLER_CTRL1);
return;
}
+int twl6030_get_battery_current(void)
+{
+ int battery_current = 0;
+ u8 msb = 0;
+ u8 lsb = 0;
+
+ twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &msb, FG_REG_11);
+ twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &lsb, FG_REG_10);
+ battery_current = ((msb << 8) | lsb);
+
+ /* convert 10 bit signed number to 16 bit signed number */
+ if (battery_current >= 0x2000)
+ battery_current = (battery_current - 0x4000);
+
+ battery_current = battery_current * 3000 / 4096;
+ printf("Battery Current: %d mA\n", battery_current);
+
+ return battery_current;
+}
+
+int twl6030_get_battery_voltage(void)
+{
+ int battery_volt = 0;
+ int ret = 0;
+
+ /* Start GPADC SW conversion */
+ ret = twl6030_gpadc_sw2_trigger();
+ if (ret) {
+ printf("Failed to convert battery voltage\n");
+ return ret;
+ }
+
+ /* measure Vbat voltage */
+ battery_volt = twl6030_gpadc_read_channel(7);
+ if (battery_volt < 0) {
+ printf("Failed to read battery voltage\n");
+ return ret;
+ }
+ battery_volt = (battery_volt * 25 * 1000) >> (10 + 2);
+ printf("Battery Voltage: %d mV\n", battery_volt);
+
+ return battery_volt;
+}
+
void twl6030_init_battery_charging(void)
{
- twl6030_start_usb_charging();
+ u8 stat1 = 0;
+ int battery_volt = 0;
+ int ret = 0;
+
+ /* Enable VBAT measurement */
+ twl6030_i2c_write_u8(TWL6030_CHIP_PM, VBAT_MEAS, MISC1);
+
+ /* Enable GPADC module */
+ ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, FGS | GPADCS, TOGGLE1);
+ if (ret) {
+ printf("Failed to enable GPADC\n");
+ return;
+ }
+
+ battery_volt = twl6030_get_battery_voltage();
+ if (battery_volt < 0)
+ return;
+
+ if (battery_volt < 3000)
+ printf("Main battery voltage too low!\n");
+
+ /* Check for the presence of USB charger */
+ twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &stat1, CONTROLLER_STAT1);
+
+ /* check for battery presence indirectly via Fuel gauge */
+ if ((stat1 & VBUS_DET) && (battery_volt < 3300))
+ twl6030_start_usb_charging();
+
return;
}
COBJS-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
COBJS-$(CONFIG_RTC_PCF8563) += pcf8563.o
COBJS-$(CONFIG_RTC_PL031) += pl031.o
+COBJS-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
COBJS-$(CONFIG_RTC_RS5C372A) += rs5c372.o
COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o
COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
--- /dev/null
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file provides Date & Time support (no alarms) for PT7C4338 chip.
+ *
+ * This file is based on drivers/rtc/ds1337.c
+ *
+ * PT7C4338 chip is manufactured by Pericom Technology Inc.
+ * It is a serial real-time clock which provides
+ * 1)Low-power clock/calendar.
+ * 2)Programmable square-wave output.
+ * It has 56 bytes of nonvolatile RAM.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+
+/* RTC register addresses */
+#define RTC_SEC_REG_ADDR 0x0
+#define RTC_MIN_REG_ADDR 0x1
+#define RTC_HR_REG_ADDR 0x2
+#define RTC_DAY_REG_ADDR 0x3
+#define RTC_DATE_REG_ADDR 0x4
+#define RTC_MON_REG_ADDR 0x5
+#define RTC_YR_REG_ADDR 0x6
+#define RTC_CTL_STAT_REG_ADDR 0x7
+
+/* RTC second register address bit */
+#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
+
+/* RTC control and status register bits */
+#define RTC_CTL_STAT_BIT_RS0 0x1 /* Rate select 0 */
+#define RTC_CTL_STAT_BIT_RS1 0x2 /* Rate select 1 */
+#define RTC_CTL_STAT_BIT_SQWE 0x10 /* Square Wave Enable */
+#define RTC_CTL_STAT_BIT_OSF 0x20 /* Oscillator Stop Flag */
+#define RTC_CTL_STAT_BIT_OUT 0x80 /* Output Level Control */
+
+/* RTC reset value */
+#define RTC_PT7C4338_RESET_VAL \
+ (RTC_CTL_STAT_BIT_RS0 | RTC_CTL_STAT_BIT_RS1 | RTC_CTL_STAT_BIT_OUT)
+
+/****** Helper functions ****************************************/
+static u8 rtc_read(u8 reg)
+{
+ return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg);
+}
+
+static void rtc_write(u8 reg, u8 val)
+{
+ i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+}
+/****************************************************************/
+
+/* Get the current time from the RTC */
+int rtc_get(struct rtc_time *tmp)
+{
+ int ret = 0;
+ u8 sec, min, hour, mday, wday, mon, year, ctl_stat;
+
+ ctl_stat = rtc_read(RTC_CTL_STAT_REG_ADDR);
+ sec = rtc_read(RTC_SEC_REG_ADDR);
+ min = rtc_read(RTC_MIN_REG_ADDR);
+ hour = rtc_read(RTC_HR_REG_ADDR);
+ wday = rtc_read(RTC_DAY_REG_ADDR);
+ mday = rtc_read(RTC_DATE_REG_ADDR);
+ mon = rtc_read(RTC_MON_REG_ADDR);
+ year = rtc_read(RTC_YR_REG_ADDR);
+ debug("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
+ "hr: %02x min: %02x sec: %02x control_status: %02x\n",
+ year, mon, mday, wday, hour, min, sec, ctl_stat);
+
+ if (ctl_stat & RTC_CTL_STAT_BIT_OSF) {
+ printf("### Warning: RTC oscillator has stopped\n");
+ /* clear the OSF flag */
+ rtc_write(RTC_CTL_STAT_REG_ADDR,
+ rtc_read(RTC_CTL_STAT_REG_ADDR)\
+ & ~RTC_CTL_STAT_BIT_OSF);
+ ret = -1;
+ }
+
+ tmp->tm_sec = bcd2bin(sec & 0x7F);
+ tmp->tm_min = bcd2bin(min & 0x7F);
+ tmp->tm_hour = bcd2bin(hour & 0x3F);
+ tmp->tm_mday = bcd2bin(mday & 0x3F);
+ tmp->tm_mon = bcd2bin(mon & 0x1F);
+ tmp->tm_year = bcd2bin(year) + 2000;
+ tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
+ tmp->tm_yday = 0;
+ tmp->tm_isdst = 0;
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ return ret;
+}
+
+/* Set the RTC */
+int rtc_set(struct rtc_time *tmp)
+{
+ debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ rtc_write(RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
+ rtc_write(RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
+ rtc_write(RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
+ rtc_write(RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
+ rtc_write(RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
+ rtc_write(RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
+ rtc_write(RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
+
+ return 0;
+}
+
+/* Reset the RTC */
+void rtc_reset(void)
+{
+ rtc_write(RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
+ rtc_write(RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL);
+}
#define serial_in(y) readb(y)
#endif
+#ifndef CONFIG_SYS_NS16550_IER
+#define CONFIG_SYS_NS16550_IER 0x00
+#endif /* CONFIG_SYS_NS16550_IER */
+
void NS16550_init (NS16550_t com_port, int baud_divisor)
{
- serial_out(0x00, &com_port->ier);
+ serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
void NS16550_reinit (NS16550_t com_port, int baud_divisor)
{
- serial_out(0x00, &com_port->ier);
+ serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
serial_out(0, &com_port->dll);
serial_out(0, &com_port->dlm);
#endif
#ifdef CONFIG_KIRKWOOD
#include <asm/arch/kirkwood.h>
-#endif
-#ifdef CONFIG_ORION5X
+#elif defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
+#elif defined(CONFIG_ARMADA100)
+#include <asm/arch/armada100.h>
#endif
#if defined (CONFIG_SERIAL_MULTI)
unsigned int baudrate = CONFIG_BAUDRATE;
DECLARE_GLOBAL_DATA_PTR;
+static struct pl01x_regs *pl01x_get_regs(int portnum)
+{
+ return (struct pl01x_regs *) port[portnum];
+}
+
#ifdef CONFIG_PL010_SERIAL
int serial_init (void)
{
+ struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int divisor;
/* First, disable everything */
- writel(0x0, port[CONSOLE_PORT] + UART_PL010_CR);
+ writel(0, ®s->pl010_cr);
/* Set baud rate */
switch (baudrate) {
divisor = UART_PL010_BAUD_38400;
}
- writel(((divisor & 0xf00) >> 8), port[CONSOLE_PORT] + UART_PL010_LCRM);
- writel((divisor & 0xff), port[CONSOLE_PORT] + UART_PL010_LCRL);
+ writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
+ writel(divisor & 0xff, ®s->pl010_lcrl);
/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
- writel((UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN),
- port[CONSOLE_PORT] + UART_PL010_LCRH);
+ writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh);
/* Finally, enable the UART */
- writel((UART_PL010_CR_UARTEN), port[CONSOLE_PORT] + UART_PL010_CR);
+ writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
return 0;
}
int serial_init (void)
{
+ struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int temp;
unsigned int divider;
unsigned int remainder;
unsigned int fraction;
/* First, disable everything */
- writel(0x0, port[CONSOLE_PORT] + UART_PL011_CR);
+ writel(0, ®s->pl011_cr);
/*
* Set baud rate
temp = (8 * remainder) / baudrate;
fraction = (temp >> 1) + (temp & 1);
- writel(divider, port[CONSOLE_PORT] + UART_PL011_IBRD);
- writel(fraction, port[CONSOLE_PORT] + UART_PL011_FBRD);
+ writel(divider, ®s->pl011_ibrd);
+ writel(fraction, ®s->pl011_fbrd);
/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
- writel((UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN),
- port[CONSOLE_PORT] + UART_PL011_LCRH);
+ writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN,
+ ®s->pl011_lcrh);
/* Finally, enable the UART */
- writel((UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE),
- port[CONSOLE_PORT] + UART_PL011_CR);
+ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
+ ®s->pl011_cr);
return 0;
}
static void pl01x_putc (int portnum, char c)
{
+ struct pl01x_regs *regs = pl01x_get_regs(portnum);
+
/* Wait until there is space in the FIFO */
- while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF)
+ while (readl(®s->fr) & UART_PL01x_FR_TXFF)
WATCHDOG_RESET();
/* Send the character */
- writel(c, port[portnum] + UART_PL01x_DR);
+ writel(c, ®s->dr);
}
static int pl01x_getc (int portnum)
{
+ struct pl01x_regs *regs = pl01x_get_regs(portnum);
unsigned int data;
/* Wait until there is data in the FIFO */
- while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE)
+ while (readl(®s->fr) & UART_PL01x_FR_RXFE)
WATCHDOG_RESET();
- data = readl(port[portnum] + UART_PL01x_DR);
+ data = readl(®s->dr);
/* Check for an error flag */
if (data & 0xFFFFFF00) {
/* Clear the error */
- writel(0xFFFFFFFF, port[portnum] + UART_PL01x_ECR);
+ writel(0xFFFFFFFF, ®s->ecr);
return -1;
}
static int pl01x_tstc (int portnum)
{
+ struct pl01x_regs *regs = pl01x_get_regs(portnum);
+
WATCHDOG_RESET();
- return !(readl(port[portnum] + UART_PL01x_FR) &
- UART_PL01x_FR_RXFE);
+ return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
}
* Definitions common to both PL010 & PL011
*
*/
-#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */
-#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */
-#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */
-#define UART_PL01x_FR 0x18 /* Flag register (Read only). */
+
+#ifndef __ASSEMBLY__
+/*
+ * We can use a combined structure for PL010 and PL011, because they overlap
+ * only in common registers.
+ */
+struct pl01x_regs {
+ u32 dr; /* 0x00 Data register */
+ u32 ecr; /* 0x04 Error clear register (Write) */
+ u32 pl010_lcrh; /* 0x08 Line control register, high byte */
+ u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
+ u32 pl010_lcrl; /* 0x10 Line control register, low byte */
+ u32 pl010_cr; /* 0x14 Control register */
+ u32 fr; /* 0x18 Flag register (Read only) */
+ u32 reserved;
+ u32 ilpr; /* 0x20 IrDA low-power counter register */
+ u32 pl011_ibrd; /* 0x24 Integer baud rate register */
+ u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
+ u32 pl011_lcrh; /* 0x2C Line control register */
+ u32 pl011_cr; /* 0x30 Control register */
+};
+#endif
#define UART_PL01x_RSR_OE 0x08
#define UART_PL01x_RSR_BE 0x04
* PL010 definitions
*
*/
-#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */
-#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */
-#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */
-#define UART_PL010_CR 0x14 /* Control register. */
-#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */
-#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */
-#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */
-
#define UART_PL010_CR_LPE (1 << 7)
#define UART_PL010_CR_RTIE (1 << 6)
#define UART_PL010_CR_TIE (1 << 5)
* PL011 definitions
*
*/
-#define UART_PL011_IBRD 0x24
-#define UART_PL011_FBRD 0x28
-#define UART_PL011_LCRH 0x2C
-#define UART_PL011_CR 0x30
-#define UART_PL011_IMSC 0x38
-#define UART_PL011_PERIPH_ID0 0xFE0
-
#define UART_PL011_LCRH_SPS (1 << 7)
#define UART_PL011_LCRH_WLEN_8 (3 << 5)
#define UART_PL011_LCRH_WLEN_7 (2 << 5)
COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
+COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS := $(COBJS-y)
--- /dev/null
+/*
+ * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
+ *
+ * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Parts taken from linux/drivers/spi/omap2_mcspi.c
+ * Copyright (C) 2005, 2006 Nokia Corporation
+ *
+ * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include "omap3_spi.h"
+
+#define WORD_LEN 8
+#define SPI_WAIT_TIMEOUT 3000000;
+
+static void spi_reset(struct omap3_spi_slave *ds)
+{
+ unsigned int tmp;
+
+ writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &ds->regs->sysconfig);
+ do {
+ tmp = readl(&ds->regs->sysstatus);
+ } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
+
+ writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
+ OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
+ OMAP3_MCSPI_SYSCONFIG_SMARTIDLE,
+ &ds->regs->sysconfig);
+
+ writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable);
+}
+
+void spi_init()
+{
+ /* do nothing */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct omap3_spi_slave *ds;
+
+ ds = malloc(sizeof(struct omap3_spi_slave));
+ if (!ds) {
+ printf("SPI error: malloc of SPI structure failed\n");
+ return NULL;
+ }
+
+ /*
+ * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
+ * with different number of chip selects (CS, channels):
+ * McSPI1 has 4 CS (bus 0, cs 0 - 3)
+ * McSPI2 has 2 CS (bus 1, cs 0 - 1)
+ * McSPI3 has 2 CS (bus 2, cs 0 - 1)
+ * McSPI4 has 1 CS (bus 3, cs 0)
+ */
+
+ switch (bus) {
+ case 0:
+ ds->regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
+ break;
+ case 1:
+ ds->regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
+ break;
+ case 2:
+ ds->regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
+ break;
+ case 3:
+ ds->regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
+ break;
+ default:
+ printf("SPI error: unsupported bus %i. \
+ Supported busses 0 - 3\n", bus);
+ return NULL;
+ }
+ ds->slave.bus = bus;
+
+ if (((bus == 0) && (cs > 3)) ||
+ ((bus == 1) && (cs > 1)) ||
+ ((bus == 2) && (cs > 1)) ||
+ ((bus == 3) && (cs > 0))) {
+ printf("SPI error: unsupported chip select %i \
+ on bus %i\n", cs, bus);
+ return NULL;
+ }
+ ds->slave.cs = cs;
+
+ if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
+ printf("SPI error: unsupported frequency %i Hz. \
+ Max frequency is 48 Mhz\n", max_hz);
+ return NULL;
+ }
+ ds->freq = max_hz;
+
+ if (mode > SPI_MODE_3) {
+ printf("SPI error: unsupported SPI mode %i\n", mode);
+ return NULL;
+ }
+ ds->mode = mode;
+
+ return &ds->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+
+ free(ds);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+ unsigned int conf, div = 0;
+
+ /* McSPI global module configuration */
+
+ /*
+ * setup when switching from (reset default) slave mode
+ * to single-channel master mode
+ */
+ spi_reset(ds);
+ conf = readl(&ds->regs->modulctrl);
+ conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
+ conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
+ writel(conf, &ds->regs->modulctrl);
+
+ /* McSPI individual channel configuration */
+
+ /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
+ if (ds->freq) {
+ while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
+ > ds->freq)
+ div++;
+ } else
+ div = 0xC;
+
+ conf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+
+ /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
+ * REVISIT: this controller could support SPI_3WIRE mode.
+ */
+ conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
+ conf |= OMAP3_MCSPI_CHCONF_DPE0;
+
+ /* wordlength */
+ conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
+ conf |= (WORD_LEN - 1) << 7;
+
+ /* set chipselect polarity; manage with FORCE */
+ if (!(ds->mode & SPI_CS_HIGH))
+ conf |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
+ else
+ conf &= ~OMAP3_MCSPI_CHCONF_EPOL;
+
+ /* set clock divisor */
+ conf &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
+ conf |= div << 2;
+
+ /* set SPI mode 0..3 */
+ if (ds->mode & SPI_CPOL)
+ conf |= OMAP3_MCSPI_CHCONF_POL;
+ else
+ conf &= ~OMAP3_MCSPI_CHCONF_POL;
+ if (ds->mode & SPI_CPHA)
+ conf |= OMAP3_MCSPI_CHCONF_PHA;
+ else
+ conf &= ~OMAP3_MCSPI_CHCONF_PHA;
+
+ /* Transmit & receive mode */
+ conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+
+ writel(conf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+
+ /* Reset the SPI hardware */
+ spi_reset(ds);
+}
+
+int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
+ unsigned long flags)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+ int i;
+ int timeout = SPI_WAIT_TIMEOUT;
+ int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+
+ if (flags & SPI_XFER_BEGIN)
+ writel(OMAP3_MCSPI_CHCTRL_EN,
+ &ds->regs->channel[ds->slave.cs].chctrl);
+
+ chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+ chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
+ chconf |= OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ for (i = 0; i < len; i++) {
+ /* wait till TX register is empty (TXS == 1) */
+ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ OMAP3_MCSPI_CHSTAT_TXS)) {
+ if (--timeout <= 0) {
+ printf("SPI TXS timed out, status=0x%08x\n",
+ readl(&ds->regs->channel[ds->slave.cs].chstat));
+ return -1;
+ }
+ }
+ /* Write the data */
+ writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
+ }
+
+ if (flags & SPI_XFER_END) {
+ /* wait to finish of transfer */
+ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ OMAP3_MCSPI_CHSTAT_EOT));
+
+ chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ }
+ return 0;
+}
+
+int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
+ unsigned long flags)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+ int i;
+ int timeout = SPI_WAIT_TIMEOUT;
+ int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+
+ if (flags & SPI_XFER_BEGIN)
+ writel(OMAP3_MCSPI_CHCTRL_EN,
+ &ds->regs->channel[ds->slave.cs].chctrl);
+
+ chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+ chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
+ chconf |= OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ writel(0, &ds->regs->channel[ds->slave.cs].tx);
+
+ for (i = 0; i < len; i++) {
+ /* Wait till RX register contains data (RXS == 1) */
+ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ OMAP3_MCSPI_CHSTAT_RXS)) {
+ if (--timeout <= 0) {
+ printf("SPI RXS timed out, status=0x%08x\n",
+ readl(&ds->regs->channel[ds->slave.cs].chstat));
+ return -1;
+ }
+ }
+ /* Read the data */
+ rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
+ }
+
+ if (flags & SPI_XFER_END) {
+ chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ }
+
+ return 0;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+ unsigned int len;
+ const u8 *txp = dout;
+ u8 *rxp = din;
+ int ret = -1;
+
+ if (bitlen % 8)
+ return -1;
+
+ len = bitlen / 8;
+
+ if (bitlen == 0) { /* only change CS */
+ int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+
+ if (flags & SPI_XFER_BEGIN) {
+ writel(OMAP3_MCSPI_CHCTRL_EN,
+ &ds->regs->channel[ds->slave.cs].chctrl);
+ chconf |= OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf,
+ &ds->regs->channel[ds->slave.cs].chconf);
+ }
+ if (flags & SPI_XFER_END) {
+ chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf,
+ &ds->regs->channel[ds->slave.cs].chconf);
+ writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ }
+ ret = 0;
+ } else {
+ if (dout != NULL)
+ ret = omap3_spi_write(slave, len, txp, flags);
+
+ if (din != NULL)
+ ret = omap3_spi_read(slave, len, rxp, flags);
+ }
+ return ret;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+}
--- /dev/null
+/*
+ * Register definitions for the OMAP3 McSPI Controller
+ *
+ * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
+ *
+ * Parts taken from linux/drivers/spi/omap2_mcspi.c
+ * Copyright (C) 2005, 2006 Nokia Corporation
+ *
+ * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP3_SPI_H_
+#define _OMAP3_SPI_H_
+
+#define OMAP3_MCSPI1_BASE 0x48098000
+#define OMAP3_MCSPI2_BASE 0x4809A000
+#define OMAP3_MCSPI3_BASE 0x480B8000
+#define OMAP3_MCSPI4_BASE 0x480BA000
+
+#define OMAP3_MCSPI_MAX_FREQ 48000000
+
+/* OMAP3 McSPI registers */
+struct mcspi_channel {
+ unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
+ unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
+ unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
+ unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
+ unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
+};
+
+struct mcspi {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned int irqstatus; /* 0x18 */
+ unsigned int irqenable; /* 0x1C */
+ unsigned int wakeupenable; /* 0x20 */
+ unsigned int syst; /* 0x24 */
+ unsigned int modulctrl; /* 0x28 */
+ struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
+ /* channel1: 0x40 - 0x50, bus 0 & 1 */
+ /* channel2: 0x54 - 0x64, bus 0 & 1 */
+ /* channel3: 0x68 - 0x78, bus 0 */
+};
+
+/* per-register bitmasks */
+#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
+
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
+
+#define OMAP3_MCSPI_MODULCTRL_SINGLE (1 << 0)
+#define OMAP3_MCSPI_MODULCTRL_MS (1 << 2)
+#define OMAP3_MCSPI_MODULCTRL_STEST (1 << 3)
+
+#define OMAP3_MCSPI_CHCONF_PHA (1 << 0)
+#define OMAP3_MCSPI_CHCONF_POL (1 << 1)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
+#define OMAP3_MCSPI_CHCONF_EPOL (1 << 6)
+#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
+#define OMAP3_MCSPI_CHCONF_DMAW (1 << 14)
+#define OMAP3_MCSPI_CHCONF_DMAR (1 << 15)
+#define OMAP3_MCSPI_CHCONF_DPE0 (1 << 16)
+#define OMAP3_MCSPI_CHCONF_DPE1 (1 << 17)
+#define OMAP3_MCSPI_CHCONF_IS (1 << 18)
+#define OMAP3_MCSPI_CHCONF_TURBO (1 << 19)
+#define OMAP3_MCSPI_CHCONF_FORCE (1 << 20)
+
+#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0)
+#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1)
+#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
+
+#define OMAP3_MCSPI_CHCTRL_EN (1 << 0)
+
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0)
+
+struct omap3_spi_slave {
+ struct spi_slave slave;
+ struct mcspi *regs;
+ unsigned int freq;
+ unsigned int mode;
+};
+
+static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct omap3_spi_slave, slave);
+}
+
+int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
+ unsigned long flags);
+int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
+ unsigned long flags);
+
+#endif /* _OMAP3_SPI_H_ */
}
-int ext2fs_ls (char *dirname) {
+int ext2fs_ls (const char *dirname) {
ext2fs_node_t dirnode;
int status;
}
-int ext2fs_open (char *filename) {
+int ext2fs_open (const char *filename) {
ext2fs_node_t fdiro = NULL;
int status;
int len;
extern int cmd_usage(cmd_tbl_t *cmdtp);
#ifdef CONFIG_AUTO_COMPLETE
-extern void install_auto_complete(void);
+extern int var_complete(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
#endif
* void function (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
*/
-typedef void command_t (cmd_tbl_t *, int, int, char *[]);
-
#if defined(CONFIG_CMD_MEMORY) \
|| defined(CONFIG_CMD_I2C) \
|| defined(CONFIG_CMD_ITEST) \
extern int cmd_get_data_size(char* arg, int default_size);
#endif
+#ifdef CONFIG_CMD_BOOTD
+extern int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+extern int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
#endif /* __ASSEMBLY__ */
/*
#define Struct_Section __attribute__ ((unused,section (".u_boot_cmd")))
-#ifdef CONFIG_SYS_LONGHELP
+#ifdef CONFIG_AUTO_COMPLETE
+# define _CMD_COMPLETE(x) x,
+#else
+# define _CMD_COMPLETE(x)
+#endif
+#ifdef CONFIG_SYS_LONGHELP
+# define _CMD_HELP(x) x,
+#else
+# define _CMD_HELP(x)
+#endif
-#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
-cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help}
+#define U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
+ {#name, maxargs, rep, cmd, usage, _CMD_HELP(help) _CMD_COMPLETE(comp)}
#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \
-{#name, maxargs, rep, cmd, usage, help}
+ U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
-#else /* no long help info */
+#define U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
+ cmd_tbl_t __u_boot_cmd_##name Struct_Section = \
+ U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp)
#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
-cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage}
-
-#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \
-{#name, maxargs, rep, cmd, usage}
-
-#endif /* CONFIG_SYS_LONGHELP */
+ U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
/* common/console.c */
int console_init_f(void); /* Before relocation; uses the serial stuff */
int console_init_r(void); /* After relocation; uses the console stuff */
-int console_assign (int file, char *devname); /* Assign the console */
+int console_assign(int file, const char *devname); /* Assign the console */
int ctrlc (void);
int had_ctrlc (void); /* have we had a Control-C since last clear? */
void clear_ctrlc (void); /* clear the Control-C condition */
* run from RAM instead of Flash.
*/
#define CONFIG_SYS_TEXT_BASE 0x08000000
+#define CONFIG_SYS_LDSCRIPT "board/amirix/ap1000/u-boot.lds"
#define CONFIG_PCI 1
#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+#define CONFIG_SYS_LDSCRIPT "board/esd/dasa_sim/u-boot.lds"
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_ML2 1 /* ...on a ML2 board */
#define CONFIG_SYS_TEXT_BASE 0x18000000
+#define CONFIG_SYS_LDSCRIPT "board/ml2/u-boot.lds"
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_MOUSSE 1
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#define CONFIG_SYS_LDSCRIPT "board/mousse/u-boot.lds"
#define CONFIG_SYS_ADDR_MAP_B 1
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFF800000
#endif
+#define CONFIG_SYS_LDSCRIPT "board/matrix_vision/mvsmr/u-boot.lds"
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
/* On a Cameron or on a FO300 board or ... */
-#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300)
+#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
+ && !defined(CONFIG_FO300)
#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
#endif
/* switch is open */
#endif /* CONFIG_FO300 */
-#ifdef CONFIG_STK52XX
+#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-#ifdef CONFIG_STK52XX
+#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_ISO_PARTITION
/* USB */
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
+ defined(CONFIG_STK52XX)
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#define CONFIG_USB_STORAGE
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#endif
-#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
+ defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#endif
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
+ defined(CONFIG_STK52XX)
#define CONFIG_CFG_USB
#define CONFIG_CFG_FAT
#endif
"fdt_addr=FC100000\0" \
"kernel_addr=FC140000\0" \
"ramdisk_addr=FC600000\0"
+#elif defined(CONFIG_CHARON)
+#define ENV_FLASH_LAYOUT \
+ "fdt_addr=FDFC0000\0" \
+ "kernel_addr=FC0A0000\0" \
+ "ramdisk_addr=FC200000\0"
#else /* !CONFIG_TQM5200_B */
#define ENV_FLASH_LAYOUT \
"fdt_addr=FC0A0000\0" \
":${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} " \
"console=${console},${baudrate}\0" \
- "flash_self_old=sete console ttyS0; run ramargs addip addcons;" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "flash_self_old=sete console ttyS0; " \
+ "run ramargs addip addcons addmtd; " \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"sete console ttyS0; run nfsargs addip addcons;bootm\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addcons; " \
+ "run nfsargs addip addcons addmtd; " \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
CUSTOM_ENV_SETTINGS \
"load=tftp 200000 ${u-boot}\0" \
/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define MTDIDS_DEFAULT "nor0=TQM5200-0"
+#define MTDIDS_DEFAULT "nor0=fc000000.flash"
-#ifdef CONFIG_STK52XX
+#if defined(CONFIG_STK52XX)
# if defined(CONFIG_TQM5200_B)
# if defined(CONFIG_SYS_LOWBOOT)
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
"256k(dtb)," \
"2304k(kernel)," \
"2560k(small-fs)," \
"8m(misc)," \
"16m(big-fs)"
# else /* highboot */
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:2560k(kernel)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
"3584k(small-fs)," \
"2m(initrd)," \
"8m(misc)," \
"1m(firmware)"
# endif /* CONFIG_SYS_LOWBOOT */
# else /* !CONFIG_TQM5200_B */
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
"128k(dtb)," \
"2304k(kernel)," \
"2m(initrd)," \
"15m(big-fs)"
# endif /* CONFIG_TQM5200_B */
#elif defined (CONFIG_CAM5200)
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
"1792k(kernel)," \
"5632k(rootfs)," \
"24m(home)"
+#elif defined (CONFIG_CHARON)
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
+ "1408k(kernel)," \
+ "2m(initrd)," \
+ "4m(small-fs)," \
+ "24320k(big-fs)," \
+ "256k(dts)"
#elif defined (CONFIG_FO300)
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
"1408k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
* use PSC1: Bits 29-31 (mask: 0x00000007):
* 100 -> UART (on all boards).
*/
+#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
#if defined (CONFIG_MINIFAP)
# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
#elif defined (CONFIG_STK52XX)
#else /* TMQ5200 Inbetriebnahme-Board */
# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
#endif
+#endif
/*
* RTC configuration
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_ASPENITE_H
+#define __CONFIG_ASPENITE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-Aspenite DB"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
+#define CONFIG_ARMADA100 1 /* SOC Family Name */
+#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
+#define CONFIG_MACH_ASPENITE /* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#define CONFIG_ENV_SIZE 0x20000 /* 64k */
+
+#endif /* __CONFIG_ASPENITE_H */
--- /dev/null
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_CHARON_H
+#define __CONFIG_CHARON_H
+
+#define CONFIG_CHARON
+#define CONFIG_HOSTNAME charon
+
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x81550414
+
+/* include common defines/options for TQM52xx boards */
+#include "TQM5200.h"
+
+/* defines special on charon board */
+#undef CONFIG_RTC_MPC5200
+#undef CONFIG_CMD_DATE
+
+#undef CUSTOM_ENV_SETTINGS
+#define CUSTOM_ENV_SETTINGS \
+ "bootfile=/tftpboot/charon/uImage\0" \
+ "fdt_file=/tftpboot/charon/charon.dtb\0" \
+ "u-boot=/tftpboot/charon/u-boot.bin\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"
+
+
+/* additional features on charon board */
+#define CONFIG_RESET_PHY_R
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_I2C_MULTI_BUS
+
+#define CONFIG_SYS_TFP410_ADDR 0x38
+#define CONFIG_SYS_TFP410_BUS 0
+
+/*
+ * FPGA configuration
+ */
+#define CONFIG_SYS_CS3_START 0xE8000000
+#define CONFIG_SYS_CS3_SIZE 0x80000 /* 512 KByte */
+
+/*
+ * CS3 Config Register Init:
+ * CS3 Enabled
+ * AddrBus: 8bits
+ * DataBus: 4bytes
+ * Multiplexed: Yes
+ * MuxBank: 00
+ */
+#define CONFIG_SYS_CS3_CFG 0x00009310
+
+#endif /* __CONFIG_CHARON_H */
* Board
*/
#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_SPIFLASH
/*
* SoC Configuration
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
/*
* I2C Configuration
*/
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 25000
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
/*
* Flash & Environment
#define CONFIG_NET_MULTI
#endif
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (64 << 10)
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/*
* U-Boot general configuration
*/
#define CONFIG_CMD_UBIFS
#endif
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SAVEENV
+#endif
+
#if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
--- /dev/null
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_SPIFLASH
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0xc1080000
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 0
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (8 << 10)
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "ea20 > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_SYS_USE_NAND 1
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_HAWK
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_UART_U_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0xc1080000
+#else
+#define CONFIG_SYS_TEXT_BASE 0xc1180000
+#endif
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE
+#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
+#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 -\
+ GENERATED_GBL_DATA_SIZE)
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Network & Ethernet Configuration
+ */
+#define CONFIG_EMAC_MDIO_PHY_NUM 0x7
+#if !defined(CONFIG_NAND_SPL)
+#define CONFIG_DRIVER_TI_EMAC
+#endif
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+
+/*
+ * Nand Flash
+ */
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_CLE_MASK 0x10
+#define CONFIG_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CFG_DAVINCI_STD_NAND_LAYOUT
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, }
+#define NAND_MAX_CHIPS 1
+/* Block 0--not used by bootcode */
+#define CONFIG_ENV_OFFSET 0x0
+
+#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xe0000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1180000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
+ CONFIG_SYS_NAND_U_BOOT_SIZE - \
+ CONFIG_SYS_MALLOC_LEN - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 24, 25, 26, 27, 28, \
+ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+ 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+ CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
+ CONFIG_SYS_NAND_ECCSTEPS)
+#endif /* CONFIG_SYS_USE_NAND */
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "hawkboard > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS \
+ "mem=128M console=ttyS2,115200n8 root=/dev/ram0 rw initrd=0xc1180000,"\
+ "4M ip=static"
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#endif
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#endif /* __CONFIG_H */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */
#endif
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
+#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
+
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
/* Update size in "reg" property of NOR FLASH device tree nodes */
#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+#define CONFIG_FIT /* enable FIT image support */
+
#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
#define CONFIG_PREBOOT "setenv bootdelay 15"
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
-/* USB */
-#ifdef CONFIG_440EPX
-#define CONFIG_USB_OHCI
+/*
+ * USB/EHCI
+ */
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
+#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
+#define CONFIG_EHCI_DCACHE /* with dcache handling support */
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
#define CONFIG_USB_STORAGE
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-#endif /* CONFIG_440EPX */
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_MARVELL 1
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+/* ====> Kirkwood Platform Common Definations */
#if defined(CONFIG_KIRKWOOD)
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */
-/*
- * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0x00600000
-#endif /* CONFIG_SYS_TEXT_BASE */
+/* Kirkwood has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX 2
#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
-#define MV_UART0_BASE KW_UART0_BASE
+#define MV_UART_CONSOLE_BASE KW_UART0_BASE
#define MV_SATA_BASE KW_SATA_BASE
#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
+/* ====> ARMADA100 Platform Common Definations */
+#elif defined (CONFIG_ARMADA100)
+
+#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
+#define MV_MFPR_BASE ARMD1_MFPR_BASE
+#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
+#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
+ represents UART Unit Enable */
+/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX 2
+
#else
-#error "Unsupported SoC"
+#error "Unsupported SoC Platform..."
#endif
+/*
+ * Custom CONFIG_SYS_TEXT_BASE can be done in <board>.h
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x00600000
+#endif /* CONFIG_SYS_TEXT_BASE */
+
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* Kirkwood has 2k of Security SRAM, use it for SP */
-#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
/*
* CLKs configurations
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 MV_UART0_BASE
+#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
/*
* Serial Port configuration
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#ifndef CONFIG_ARMADA100 /* will be removed latter */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#endif /* CONFIG_ARMADA100 */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
-#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
+#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/*
+ * DRAM Banks configuration, Custom config can be done in <board>.h
+ */
+#ifndef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS CONFIG_NR_DRAM_BANKS_MAX
+#else
+#if (CONFIG_NR_DRAM_BANKS > CONFIG_NR_DRAM_BANKS_MAX)
+#error CONFIG_NR_DRAM_BANKS Configurated more than available
+#endif
+#endif /* CONFIG_NR_DRAM_BANKS */
+
/*
* Ethernet Driver configuration
*/
#define CONFIG_CMD_MII
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
-#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
/*
* File system
*/
+#ifndef CONFIG_ARMADA100 /* will be removed latter */
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_FAT
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
+#endif /* CONFIG_ARMADA100 */
#endif /* _MV_COMMON_H */
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+#define CONFIG_OMAP3_SPI
+
#endif /* __CONFIG_H */
/* TWL6030 */
#define CONFIG_TWL6030_POWER 1
+#define CONFIG_CMD_BAT 1
/* MMC */
#define CONFIG_GENERIC_MMC 1
#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_SYS_TEXT_BASE 0xff000000
+#define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds"
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
+#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+ (CONFIG_SYS_FPGA1_BASE + 0x01000000) }
+#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \
+ 0xbddf } /* set async read mode */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/
"ramdisk_addr=fc200000\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \
+ "unlock=yes\0" \
""
/*
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#endif
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
#include "manroland/common.h"
#include "manroland/mpc5200-common.h"
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS
/*Misc*/
#define CONFIG_BOOTDELAY 5/* autoboot after 5 seconds */
unsigned char data[ENV_SIZE]; /* Environment data */
} env_t;
+#ifndef DO_DEPS_ONLY
+
+#include <search.h>
+
+extern struct hsearch_data env_htab;
+
/* Function that returns a character from the environment */
unsigned char env_get_char (int);
/* Import from binary representation into hash table */
int env_import(const char *buf, int check);
+#endif
+
#endif /* _ENVIRONMENT_H_ */
void __udelay(unsigned long);
unsigned long get_timer(unsigned long);
int vprintf(const char *, va_list);
-void do_reset (void);
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
char *getenv (char *name);
int setenv (char *varname, char *varvalue);
extern int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part);
-extern int ext2fs_ls (char *dirname);
-extern int ext2fs_open (char *filename);
+extern int ext2fs_ls (const char *dirname);
+extern int ext2fs_open (const char *filename);
extern int ext2fs_read (char *buf, unsigned len);
extern int ext2fs_mount (unsigned part_length);
extern int ext2fs_close(void);
* entry that matches the given short name. If a matching entry is
* found, it's id is returned to the caller.
*/
-int get_table_entry_id (table_entry_t *table,
+int get_table_entry_id(const table_entry_t *table,
const char *table_name, const char *name);
/*
* get_table_entry_name() scans the translation table trying to find
* an entry that matches the given id. If a matching entry is found,
* its long name is returned to the caller.
*/
-char *get_table_entry_name (table_entry_t *table, char *msg, int id);
+char *get_table_entry_name(const table_entry_t *table, char *msg, int id);
const char *genimg_get_os_name (uint8_t os);
const char *genimg_get_arch_name (uint8_t arch);
int iomux_doenv(const int, const char *);
void iomux_printdevs(const int);
-struct stdio_dev *search_device(int, char *);
+struct stdio_dev *search_device(int, const char *);
#endif /* _IO_MUX_H */
#define _X 0x40 /* hex digit */
#define _SP 0x80 /* hard space (0x20) */
-extern unsigned char _ctype[];
+extern const unsigned char _ctype[];
#define __ismask(x) (_ctype[(int)(unsigned char)(x)])
#define NAND_CMD_SEQIN 0x80
#define NAND_CMD_RNDIN 0x85
#define NAND_CMD_READID 0x90
+#define NAND_CMD_PARAM 0xec
#define NAND_CMD_ERASE2 0xd0
#define NAND_CMD_RESET 0xff
char * name;
};
-extern struct nand_flash_dev nand_flash_ids[];
-extern struct nand_manufacturers nand_manuf_ids[];
+extern const struct nand_flash_dev nand_flash_ids[];
+extern const struct nand_manufacturers nand_manuf_ids[];
extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
#define FLASH_CMD_ERASE_CONFIRM 0xD0
#define FLASH_CMD_WRITE 0x40
#define FLASH_CMD_PROTECT 0x60
+#define FLASH_CMD_SETUP 0x60
+#define FLASH_CMD_SET_CR_CONFIRM 0x03
#define FLASH_CMD_PROTECT_SET 0x01
#define FLASH_CMD_PROTECT_CLEAR 0xD0
#define FLASH_CMD_CLEAR_STATUS 0x50
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __MVMFP_H
+#define __MVMFP_H
+
+/*
+ * Header file for MultiFunctionPin (MFP) Configururation framework
+ *
+ * Processors Supported:
+ * 1. Marvell ARMADA100 Processors
+ *
+ * processor to be supported should be added here
+ */
+
+/*
+ * MFP configuration is represented by a 32-bit unsigned integer
+ */
+#define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \
+ /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \
+ /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \
+ /* bit 12 - Unused */ \
+ /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \
+ /* bit 09 - Pull State flag */ (((_pF) & 0x1) << 9) | \
+ /* bit 08 - Drv-strength flag */ (((_dF) & 0x1) << 8) | \
+ /* bit 07 - Edge-det flag */ (((_eF) & 0x1) << 7) | \
+ /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \
+ /* bits 03..00 - Alt-fun flag */ (((_aF) & 0x1) << 3) | \
+ /* bits Alternate-fun select */ ((_afn) & 0x7))
+
+/*
+ * to facilitate the definition, the following macros are provided
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+#define MFP_OFFSET_MASK MFP(0xffff, 0,0, 0,0, 0,0, 0,0)
+#define MFP_REG(x) MFP(x, 0,0, 0,0, 0,0, 0,0)
+#define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16)
+
+#define MFP_AF_FLAG MFP(0x0000, 0,0, 0,0, 0,0, 0,1)
+#define MFP_DRIVE_FLAG MFP(0x0000, 0,0, 0,1, 0,0, 0,0)
+#define MFP_EDGE_FLAG MFP(0x0000, 0,0, 0,0, 0,1, 0,0)
+#define MFP_PULL_FLAG MFP(0x0000, 0,1, 0,0, 0,0, 0,0)
+
+#define MFP_AF0 MFP(0x0000, 0,0, 0,0, 0,0, 0,1)
+#define MFP_AF1 MFP(0x0000, 0,0, 0,0, 0,0, 1,1)
+#define MFP_AF2 MFP(0x0000, 0,0, 0,0, 0,0, 2,1)
+#define MFP_AF3 MFP(0x0000, 0,0, 0,0, 0,0, 3,1)
+#define MFP_AF4 MFP(0x0000, 0,0, 0,0, 0,0, 4,1)
+#define MFP_AF5 MFP(0x0000, 0,0, 0,0, 0,0, 5,1)
+#define MFP_AF6 MFP(0x0000, 0,0, 0,0, 0,0, 6,1)
+#define MFP_AF7 MFP(0x0000, 0,0, 0,0, 0,0, 7,1)
+#define MFP_AF_MASK MFP(0x0000, 0,0, 0,0, 0,0, 7,0)
+
+#define MFP_LPM_EDGE_NONE MFP(0x0000, 0,0, 0,0, 0,1, 0,0)
+#define MFP_LPM_EDGE_RISE MFP(0x0000, 0,0, 0,0, 1,1, 0,0)
+#define MFP_LPM_EDGE_FALL MFP(0x0000, 0,0, 0,0, 2,1, 0,0)
+#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0,0, 0,0, 3,1, 0,0)
+#define MFP_LPM_EDGE_MASK MFP(0x0000, 0,0, 0,0, 3,0, 0,0)
+
+#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0,0, 0,1, 0,0, 0,0)
+#define MFP_DRIVE_SLOW MFP(0x0000, 0,0, 1,1, 0,0, 0,0)
+#define MFP_DRIVE_MEDIUM MFP(0x0000, 0,0, 2,1, 0,0, 0,0)
+#define MFP_DRIVE_FAST MFP(0x0000, 0,0, 3,1, 0,0, 0,0)
+#define MFP_DRIVE_MASK MFP(0x0000, 0,0, 3,0, 0,0, 0,0)
+
+#define MFP_PULL_NONE MFP(0x0000, 0,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_LOW MFP(0x0000, 1,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_HIGH MFP(0x0000, 2,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_BOTH MFP(0x0000, 3,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_FLOAT MFP(0x0000, 4,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_MASK MFP(0x0000, 7,0, 0,0, 0,0, 0,0)
+
+#define MFP_EOC 0xffffffff /* indicates end-of-conf */
+
+/* Functions */
+void mfp_config(u32 *mfp_cfgs);
+
+#endif /* __MVMFP_H */
extern void ip_to_string (IPaddr_t x, char *s);
/* Convert a string to ip address */
-extern IPaddr_t string_to_ip(char *s);
+extern IPaddr_t string_to_ip(const char *s);
/* Convert a VLAN id to a string */
extern void VLAN_to_string (ushort x, char *s);
/* Convert a string to a vlan id */
-extern ushort string_to_VLAN(char *s);
+extern ushort string_to_VLAN(const char *s);
/* read a VLAN id from an environment variable */
extern ushort getenv_VLAN(char *);
/* copy a filename (allow for "..." notation, limit length) */
-extern void copy_filename (char *dst, char *src, int size);
+extern void copy_filename (char *dst, const char *src, int size);
/* get a random source port */
extern unsigned int random_port(void);
#define __set_errno(val) do { errno = val; } while (0)
-/*
- * Prototype structure for a linked-list data structure.
- * This is the type used by the `insque' and `remque' functions.
- */
-
-/* For use with hsearch(3). */
-typedef int (*__compar_fn_t) (__const void *, __const void *);
-typedef __compar_fn_t comparison_fn_t;
-
/* Action which shall be performed in the call the hsearch. */
typedef enum {
FIND,
};
/* Create a new hashing table which will at most contain NEL elements. */
-extern int hcreate(size_t __nel);
extern int hcreate_r(size_t __nel, struct hsearch_data *__htab);
/* Destroy current internal hashing table. */
-extern void hdestroy(void);
extern void hdestroy_r(struct hsearch_data *__htab);
/*
* NULL. If ACTION is `ENTER' replace existing data (if any) with
* ITEM.data.
* */
-extern ENTRY *hsearch(ENTRY __item, ACTION __action);
extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval,
struct hsearch_data *__htab);
/* Search and delete entry matching ITEM.key in internal hash table. */
-extern int hdelete(const char *__key);
extern int hdelete_r(const char *__key, struct hsearch_data *__htab);
-extern ssize_t hexport(const char __sep, char **__resp, size_t __size);
extern ssize_t hexport_r(struct hsearch_data *__htab,
const char __sep, char **__resp, size_t __size);
-extern int himport(const char *__env, size_t __size, const char __sep,
- int __flag);
extern int himport_r(struct hsearch_data *__htab,
const char *__env, size_t __size, const char __sep,
int __flag);
-/* Flags for himport() / himport_r() */
+/* Flags for himport_r() */
#define H_NOCLEAR 1 /* do not clear hash table before importing */
#endif /* search.h */
Xilinx_wr_fn wr;
Xilinx_post_fn post;
Xilinx_bwr_fn bwr; /* block write function */
+ Xilinx_abort_fn abort;
} Xilinx_Spartan3_Slave_Serial_fns;
/* Device Image Sizes
int stdio_init (void);
void stdio_print_current_devices(void);
#ifdef CONFIG_SYS_STDIO_DEREGISTER
-int stdio_deregister(char *devname);
+int stdio_deregister(const char *devname);
#endif
struct list_head* stdio_get_list(void);
-struct stdio_dev* stdio_get_by_name(char* name);
+struct stdio_dev* stdio_get_by_name(const char* name);
struct stdio_dev* stdio_clone(struct stdio_dev *dev);
#ifdef CONFIG_ARM_DCC_MULTI
#define TWL6030_CHIP_CHARGER 0x49
#define TWL6030_CHIP_PWM 0x49
+/* Slave Address 0x48 */
+#define VUSB_CFG_STATE 0xA2
+
+#define MISC1 0xE4
+#define VAC_MEAS (1 << 2)
+#define VBAT_MEAS (1 << 1)
+#define BB_MEAS (1 << 0)
+
+#define MISC2 0xE5
+
+/* Slave Address 0x49 */
+
/* Battery CHARGER REGISTERS */
#define CONTROLLER_INT_MASK 0xE0
#define CONTROLLER_CTRL1 0xE1
#define CHARGERUSB_VOREG_4P0 0x19
#define CHARGERUSB_VOREG_4P2 0x23
#define CHARGERUSB_VOREG_4P76 0x3F
+/* CHARGERUSB_CTRL1 */
+#define SUSPEND_BOOT (1 << 7)
+#define OPA_MODE (1 << 6)
+#define HZ_MODE (1 << 5)
+#define TERM (1 << 4)
/* CHARGERUSB_CTRL2 */
#define CHARGERUSB_CTRL2_VITERM_50 (0 << 5)
#define CHARGERUSB_CTRL2_VITERM_100 (1 << 5)
#define CHARGERUSB_CTRL2_VITERM_150 (2 << 5)
+#define CHARGERUSB_CTRL2_VITERM_400 (7 << 5)
/* CONTROLLER_CTRL1 */
#define CONTROLLER_CTRL1_EN_CHARGER (1 << 4)
#define CONTROLLER_CTRL1_SEL_CHARGER (1 << 3)
+/* CONTROLLER_STAT1 */
+#define CHRG_EXTCHRG_STATZ (1 << 7)
+#define CHRG_DET_N (1 << 5)
+#define VAC_DET (1 << 3)
+#define VBUS_DET (1 << 2)
-#define VUSB_CFG_STATE 0xA2
-#define MISC2 0xE5
+#define FG_REG_10 0xCA
+#define FG_REG_11 0xCB
+
+#define TOGGLE1 0x90
+#define FGS (1 << 5)
+#define FGR (1 << 4)
+#define GPADCS (1 << 1)
+#define GPADCR (1 << 0)
+
+#define CTRL_P2 0x34
+#define CTRL_P2_SP2 (1 << 2)
+#define CTRL_P2_EOCP2 (1 << 1)
+#define CTRL_P2_BUSY (1 << 0)
+
+#define GPCH0_LSB 0x57
+#define GPCH0_MSB 0x58
void twl6030_init_battery_charging(void);
void twl6030_usb_device_settings(void);
+void twl6030_start_usb_charging(void);
+void twl6030_stop_usb_charging(void);
+int twl6030_get_battery_voltage(void);
+int twl6030_get_battery_current(void);
#include <linux/ctype.h>
-unsigned char _ctype[] = {
+const unsigned char _ctype[] = {
_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */
_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */
_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */
* [Knuth] The Art of Computer Programming, part 3 (6.4)
*/
-/*
- * The non-reentrant version use a global space for storing the hash table.
- */
-static struct hsearch_data htab;
-
/*
* The reentrant version has no static variables to maintain the state.
* Instead the interface of all functions is extended to take an argument
return number % div != 0;
}
-int hcreate(size_t nel)
-{
- return hcreate_r(nel, &htab);
-}
-
/*
* Before using the hash table we must allocate memory for it.
* Test for an existing table are done. We allocate one element
* The contents of the table is zeroed, especially the field used
* becomes zero.
*/
+
int hcreate_r(size_t nel, struct hsearch_data *htab)
{
/* Test for correct arguments. */
/*
* hdestroy()
*/
-void hdestroy(void)
-{
- hdestroy_r(&htab);
-}
/*
* After using the hash table it has to be destroyed. The used memory can
* be freed and the local static variable can be marked as not used.
*/
+
void hdestroy_r(struct hsearch_data *htab)
{
int i;
* example for functions like hdelete().
*/
-ENTRY *hsearch(ENTRY item, ACTION action)
-{
- ENTRY *result;
-
- (void) hsearch_r(item, action, &result, &htab);
-
- return result;
-}
-
int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval,
struct hsearch_data *htab)
{
* do that.
*/
-int hdelete(const char *key)
-{
- return hdelete_r(key, &htab);
-}
-
int hdelete_r(const char *key, struct hsearch_data *htab)
{
ENTRY e, *ep;
* bytes in the string will be '\0'-padded.
*/
-ssize_t hexport(const char sep, char **resp, size_t size)
-{
- return hexport_r(&htab, sep, resp, size);
-}
-
static int cmpkey(const void *p1, const void *p2)
{
ENTRY *e1 = *(ENTRY **) p1;
* '\0' and '\n' have really been tested.
*/
-int himport(const char *env, size_t size, const char sep, int flag)
-{
- return himport_r(&htab, env, size, sep, flag);
-}
-
int himport_r(struct hsearch_data *htab,
const char *env, size_t size, const char sep, int flag)
{
#include <common.h>
-IPaddr_t string_to_ip(char *s)
+IPaddr_t string_to_ip(const char *s)
{
IPaddr_t addr;
char *e;
#include <common.h>
#if !defined (CONFIG_PANIC_HANG)
#include <command.h>
-/*cmd_boot.c*/
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
#include <div64.h>
--- /dev/null
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_NAND_SPL = y
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+
+SOBJS = start.o _udivsi3.o _divsi3.o
+COBJS = cpu.o davinci_nand.o ns16550.o div0.o davinci_pinmux.o psc.o \
+ misc.o hawkboard_nand_spl.o nand_boot.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin \
+ $(nandobj)u-boot-spl-16k.bin
+
+all: $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+$(nandobj)u-boot.lds: $(LDSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+# create symbolic links for common files
+
+# from board directory
+$(obj)davinci_pinmux.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/board/davinci/common/davinci_pinmux.c $@
+
+# from drivers/mtd/nand directory
+$(obj)davinci_nand.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/drivers/mtd/nand/davinci_nand.c $@
+
+# from nand_spl directory
+$(obj)nand_boot.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@
+
+# from drivers/serial directory
+$(obj)ns16550.c:
+ @rm -f $@
+ @ln -sf $(TOPDIR)/drivers/serial/ns16550.c $@
+
+# from cpu directory
+$(obj)start.S:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/start.S $@
+
+# from lib directory
+$(obj)_udivsi3.S:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/lib/_udivsi3.S $@
+
+# from lib directory
+$(obj)_divsi3.S:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/lib/_divsi3.S $@
+
+# from lib directory
+$(obj)div0.c:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/lib/div0.c $@
+
+# from SoC directory
+$(obj)cpu.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/cpu.c $@
+
+# from board directory
+$(obj)hawkboard_nand_spl.c:
+ @rm -f $@
+ ln -s $(TOPDIR)/board/davinci/da8xxevm/hawkboard_nand_spl.c $@
+
+# from board directory
+$(obj)misc.c:
+ @rm -f $@
+ ln -s $(TOPDIR)/board/davinci/common/misc.c $@
+
+$(obj)psc.c:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/psc.c $@
+
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0xc1080000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ start.o (.text)
+ cpu.o (.text)
+ nand_boot.o (.text)
+
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data)
+ __datarel_start = .;
+ *(.data.rel)
+ __datarelrolocal_start = .;
+ *(.data.rel.ro.local)
+ __datarellocal_start = .;
+ *(.data.rel.local)
+ __datarelro_start = .;
+ *(.data.rel.ro)
+ }
+
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ __rel_dyn_end = .;
+ __dynsym_start = .;
+
+ __got_start = .;
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __got_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
*(.sdata*)
_GOT2_TABLE_ = .;
KEEP(*(.got2))
- __got2_entries = (. - _GOT2_TABLE_) >> 2;
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
}
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
. = ALIGN(8);
__bss_start = .;
*(.sdata*)
_GOT2_TABLE_ = .;
KEEP(*(.got2))
- __got2_entries = (. - _GOT2_TABLE_) >> 2;
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
}
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
. = ALIGN(8);
__bss_start = .;
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o cpu_init.o lowlevel_init.o
-COBJS = nand_boot.o nand_ecc.o s3c64xx.o
+COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@rm -f $@
@ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@
+$(obj)smdk6400_nand_spl.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/board/samsung/smdk6400/smdk6400_nand_spl.c $@
+
#########################################################################
$(obj)%.o: $(obj)%.S
*(.sdata*)
_GOT2_TABLE_ = .;
*(.got2)
- __got2_entries = (. - _GOT2_TABLE_) >> 2;
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
}
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
. = ALIGN(8);
__bss_start = .;
return 0;
}
-#if defined(CONFIG_ARM)
-void board_init_f (ulong bootflag)
-{
- relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
- CONFIG_SYS_TEXT_BASE);
-}
-#endif
-
/*
* The main entry for NAND booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
/*
* Init board specific nand support
*/
+ nand_chip.select_chip = NULL;
nand_info.priv = &nand_chip;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
nand_chip.dev_ready = NULL; /* preset to NULL */
ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2);
}
-void copy_filename (char *dst, char *src, int size)
+void copy_filename (char *dst, const char *src, int size)
{
if (*src && (*src == '"')) {
++src;
sprintf(s, "%d", x & VLAN_IDMASK);
}
-ushort string_to_VLAN(char *s)
+ushort string_to_VLAN(const char *s)
{
ushort id;
* are transmitted. The configurable test parameters are:
* MIN_PACKET_LENGTH - minimum size of packet to transmit
* MAX_PACKET_LENGTH - maximum size of packet to transmit
- * TEST_NUM - number of tests
+ * CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
+ * is tested with a different frame length. Starting with
+ * MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
+ * Defaults to 10 and can be overriden in the board config header.
*/
#include <post.h>
#endif
#define MIN_PACKET_LENGTH 64
-#define MAX_PACKET_LENGTH 256
-#define TEST_NUM 1
+#define MAX_PACKET_LENGTH 1514
+#ifndef CONFIG_SYS_POST_ETH_LOOPS
+#define CONFIG_SYS_POST_ETH_LOOPS 10
+#endif
+#define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
+ CONFIG_SYS_POST_ETH_LOOPS)
static volatile mal_desc_t tx __cacheline_aligned;
static volatile mal_desc_t rx __cacheline_aligned;
return 0;
}
+ char packet_send[MAX_PACKET_LENGTH];
+ char packet_recv[MAX_PACKET_LENGTH];
static int test_ctlr (int devnum, int hw_addr)
{
int res = -1;
- char packet_send[MAX_PACKET_LENGTH];
- char packet_recv[MAX_PACKET_LENGTH];
int length;
- int i;
int l;
ether_post_init (devnum, hw_addr);
- for (i = 0; i < TEST_NUM; i++) {
- for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
- packet_fill (packet_send, l);
+ for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
+ l -= PACKET_INCR) {
+ packet_fill (packet_send, l);
- ether_post_send (devnum, hw_addr, packet_send, l);
+ ether_post_send (devnum, hw_addr, packet_send, l);
- length = ether_post_recv (devnum, hw_addr, packet_recv,
- sizeof (packet_recv));
+ length = ether_post_recv (devnum, hw_addr, packet_recv,
+ sizeof (packet_recv));
- if (length != l || packet_check (packet_recv, length) < 0) {
- goto Done;
- }
+ if (length != l || packet_check (packet_recv, length) < 0) {
+ goto Done;
}
}
projects / u-boot / commitdiff