*/
 #include <phy.h>
 
+#define AR803x_PHY_DEBUG_ADDR_REG      0x1d
+#define AR803x_PHY_DEBUG_DATA_REG      0x1e
+
+#define AR803x_DEBUG_REG_5             0x5
+#define AR803x_RGMII_TX_CLK_DLY                0x100
+
+#define AR803x_DEBUG_REG_0             0x0
+#define AR803x_RGMII_RX_CLK_DLY                0x8000
+
 static int ar8021_config(struct phy_device *phydev)
 {
        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
        return 0;
 }
 
+static int ar8031_config(struct phy_device *phydev)
+{
+       if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+           phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
+               phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+                         AR803x_DEBUG_REG_5);
+               phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+                         AR803x_RGMII_TX_CLK_DLY);
+       }
+
+       if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+           phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
+               phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+                         AR803x_DEBUG_REG_0);
+               phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+                         AR803x_RGMII_RX_CLK_DLY);
+       }
+
+       phydev->supported = phydev->drv->features;
+
+       genphy_config_aneg(phydev);
+       genphy_restart_aneg(phydev);
+
+       return 0;
+}
+
 static int ar8035_config(struct phy_device *phydev)
 {
        int regval;
        .uid = 0x4dd074,
        .mask = 0xffffffef,
        .features = PHY_GBIT_FEATURES,
-       .config = ar8035_config,
+       .config = ar8031_config,
        .startup = genphy_startup,
        .shutdown = genphy_shutdown,
 };