These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
config TARGET_DIGSY_MTC
bool "Support digsy_mtc"
-config TARGET_HMI1001
- bool "Support hmi1001"
-
-config TARGET_MUCMC52
- bool "Support mucmc52"
-
-config TARGET_UC101
- bool "Support uc101"
-
config TARGET_PCM030
bool "Support pcm030"
source "board/intercontrol/digsy_mtc/Kconfig"
source "board/ipek01/Kconfig"
source "board/jupiter/Kconfig"
-source "board/manroland/hmi1001/Kconfig"
-source "board/manroland/mucmc52/Kconfig"
-source "board/manroland/uc101/Kconfig"
source "board/motionpro/Kconfig"
source "board/munices/Kconfig"
source "board/phytec/pcm030/Kconfig"
/* All sample codes do that... */
*(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
-#if defined(CONFIG_UC101)
- /* Configure and reset host */
- *(vu_long *) MPC5XXX_ATA_HOST_CONFIG =
- MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
- udelay (10);
- *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0;
-#else
/* Configure and reset host */
*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
udelay (10);
*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
-#endif
/* Disable prefetch on Commbus */
psdma->PtdCntrl |= 1;
config TARGET_ELPT860
bool "Support ELPT860"
-config TARGET_UC100
- bool "Support uc100"
-
config TARGET_TQM823L
bool "Support TQM823L"
source "board/kup/kup4k/Kconfig"
source "board/kup/kup4x/Kconfig"
source "board/lwmon/Kconfig"
-source "board/manroland/uc100/Kconfig"
source "board/netvia/Kconfig"
source "board/r360mpi/Kconfig"
source "board/spd8xx/Kconfig"
+++ /dev/null
-if TARGET_HMI1001
-
-config SYS_BOARD
- default "hmi1001"
-
-config SYS_VENDOR
- default "manroland"
-
-config SYS_CONFIG_NAME
- default "hmi1001"
-
-endif
+++ /dev/null
-HMI1001 BOARD
-#M: -
-S: Maintained
-F: board/manroland/hmi1001/
-F: include/configs/hmi1001.h
-F: configs/hmi1001_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := hmi1001.o
+++ /dev/null
-/*
- * (C) Copyright 2003-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <malloc.h>
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
- uint svr, pvr;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
- __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
- * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
- *
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
- * parameters."
- */
- svr = get_svr();
- pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) &&
- (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
- *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
- __asm__ volatile ("sync");
- }
-
-/* return dramsize + dramsize2; */
- return dramsize;
-}
-
-int checkboard (void)
-{
- puts ("Board: HMI1001\n");
- return 0;
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-#define S1_ROT 0xf0
-#define S2_Q 0x40
-#define S2_M 0x20
-
-struct kbd_data_t {
- char s1;
- char s2;
-};
-
-struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
-{
- kbd_data->s1 = *((volatile uchar*)(CONFIG_SYS_STATUS1_BASE));
- kbd_data->s2 = *((volatile uchar*)(CONFIG_SYS_STATUS2_BASE));
-
- return kbd_data;
-}
-
-static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
-{
- char s1 = str[0];
- char s2;
-
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (((S1_ROT & kbd_data->s1) >> 4) != s1)
- return -1;
-
- s2 = (S2_Q | S2_M) & kbd_data->s2;
-
- switch (str[1]) {
- case 'q':
- case 'Q':
- if (s2 == S2_Q)
- return -1;
- break;
- case 'm':
- case 'M':
- if (s2 == S2_M)
- return -1;
- break;
- case '\0':
- if (s2 == (S2_Q | S2_M))
- return 0;
- default:
- return -1;
- }
-
- if (str[2])
- return -1;
-
- return 0;
-}
-
-static char *key_match (const struct kbd_data_t *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- char *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can be appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys; *suffix ||
- suffix == kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = getenv (cmd_name);
-
- return (cmd);
- }
- }
-
- return (NULL);
-}
-
-#endif /* CONFIG_PREBOOT */
-
-int misc_init_r (void)
-{
-#ifdef CONFIG_PREBOOT
- struct kbd_data_t kbd_data;
- /* Decode keys */
- char *str = strdup (key_match (get_keys (&kbd_data)));
- /* Set or delete definition */
- setenv ("preboot", str);
- free (str);
-#endif /* CONFIG_PREBOOT */
-
- return 0;
-}
-
-int board_early_init_r (void)
-{
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
- *(vu_long *)MPC5XXX_BOOTCS_START =
- *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
- *(vu_long *)MPC5XXX_BOOTCS_STOP =
- *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
- return 0;
-}
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
+++ /dev/null
-if TARGET_MUCMC52
-
-config SYS_BOARD
- default "mucmc52"
-
-config SYS_VENDOR
- default "manroland"
-
-config SYS_CONFIG_NAME
- default "mucmc52"
-
-endif
+++ /dev/null
-MUCMC52 BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/manroland/mucmc52/
-F: include/configs/mucmc52.h
-F: configs/mucmc52_defconfig
+++ /dev/null
-#
-# (C) Copyright 2008
-# Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mucmc52.o
+++ /dev/null
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <malloc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_EMODE));
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE,
- (SDRAM_MODE | 0x04000000));
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
- __asm__ volatile ("sync");
-
- /* auto refresh */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
- __asm__ volatile ("sync");
-
- /* set mode register */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_MODE));
- __asm__ volatile ("sync");
-
- /* normal operation */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | hi_addr_bit));
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
- uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0x0000001c); /* 512MB at 0x0 */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);/* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- out_be32 ((unsigned __iomem *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start (0);
- test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- sdram_start(1);
- test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- if (test1 > test2) {
- sdram_start (0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG,
- (0x13 + __builtin_ffs(dramsize >> 20) - 1));
- } else {
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, (dramsize + 0x0000001c));/*512MB*/
-
- /* find RAM size using SDRAM CS1 only */
- if (!dramsize)
- sdram_start (0);
- test2 = test1 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
- if (!dramsize) {
- sdram_start (1);
- test2 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
- }
- if (test1 > test2) {
- sdram_start (0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG,
- (dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
- } else {
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
- * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
- *
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
- * parameters."
- */
- svr = get_svr();
- pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) &&
- (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
- __asm__ volatile ("sync");
- }
-
- return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
- puts ("Board: MUC.MC-52 HW WDT ");
-#if defined(CONFIG_HW_WATCHDOG)
- puts ("enabled\n");
-#else
- puts ("disabled\n");
-#endif
- return 0;
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-#define S1_ROT 0xf0
-#define S2_Q 0x40
-#define S2_M 0x20
-
-struct kbd_data_t {
- char s1;
- char s2;
-};
-
-struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
-{
- kbd_data->s1 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS1_BASE);
- kbd_data->s2 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS2_BASE);
-
- return kbd_data;
-}
-
-static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
-{
- char s1 = str[0];
- char s2;
-
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (((S1_ROT & kbd_data->s1) >> 4) != s1)
- return -1;
-
- s2 = (S2_Q | S2_M) & kbd_data->s2;
-
- switch (str[1]) {
- case 'q':
- case 'Q':
- if (s2 == S2_Q)
- return -1;
- break;
- case 'm':
- case 'M':
- if (s2 == S2_M)
- return -1;
- break;
- case '\0':
- if (s2 == (S2_Q | S2_M))
- return 0;
- default:
- return -1;
- }
-
- if (str[2])
- return -1;
-
- return 0;
-}
-
-static char *key_match (const struct kbd_data_t *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- char *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can be appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys; *suffix ||
- suffix == kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = getenv (cmd_name);
-
- return (cmd);
- }
- }
-
- return (NULL);
-}
-
-#endif /* CONFIG_PREBOOT */
-
-int misc_init_r (void)
-{
-#ifdef CONFIG_PREBOOT
- struct kbd_data_t kbd_data;
- /* Decode keys */
- char *str = strdup (key_match (get_keys (&kbd_data)));
- /* Set or delete definition */
- setenv ("preboot", str);
- free (str);
-#endif /* CONFIG_PREBOOT */
-
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), ' ');
-
- return 0;
-}
-
-int board_early_init_r (void)
-{
- out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1);
- out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_FLASH_BASE));
- out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_FLASH_BASE));
- out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP,
- STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
- out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP,
- STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
- return 0;
-}
-
-int last_stage_init (void)
-{
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), 'M');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), 'U');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), 'C');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), '.');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), 'M');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), 'C');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), '5');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), '2');
-
- return 0;
-}
-
-#if defined(CONFIG_HW_WATCHDOG)
-#define GPT_OUT_0 0x00000027
-#define GPT_OUT_1 0x00000037
-void hw_watchdog_reset (void)
-{
- /* Trigger HW Watchdog with TIMER_0 */
- out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_1);
- out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_0);
-}
-#endif
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init (struct pci_controller *);
-
-void pci_init_board (void)
-{
- pci_mpc5xxx_init (&hose);
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+++ /dev/null
-if TARGET_UC100
-
-config SYS_BOARD
- default "uc100"
-
-config SYS_VENDOR
- default "manroland"
-
-config SYS_CONFIG_NAME
- default "uc100"
-
-endif
+++ /dev/null
-UC100 BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/manroland/uc100/
-F: include/configs/uc100.h
-F: configs/uc100_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = uc100.o pcmcia.o
+++ /dev/null
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if (defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "UC100"
-
-/*
- * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board.
- * This leads to board-hangup! (sr, 8 Dez. 2004)
- */
-static void cfg_ports (void)
-{
- volatile immap_t *immap;
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
-
- /*
- * Configure Port A for MAX1602 PC-Card Power-Interface Switch
- */
- immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */
- immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */
-
- debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n",
- immap->im_ioport.iop_papar, immap->im_ioport.iop_padir,
- immap->im_ioport.iop_padat);
-}
-
-int pcmcia_hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
- cfg_ports ();
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-
- if ((reg & mask) == mask)
- puts (" 5.0V card found: ");
- else
- puts (" 3.3V card found: ");
-
- /* switch VCC on */
- immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */
-
- udelay(10000);
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /* switch VCC off */
- immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- u_long reg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
- debug ("PCMCIA power OFF\n");
- cfg_ports (); /* Enables switch, but all in Hi-Z */
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* CONFIG_PCMCIA */
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-
-int fec8xx_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
-
-/*********************************************************************/
-/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
-/*********************************************************************/
-const uint sdram_init_upm_table[] = {
- /* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
- /* NOP - Precharge - AutoRefr - NOP - NOP */
- /* NOP - AutoRefr - NOP */
- /* NOP - NOP - LoadModeR - NOP - Active */
- /* Position of Single Read */
- 0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
- 0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
-
- /* Burst Read. (offset 8 in UPMA RAM) */
- /* Cycle lent for Initialisation WV */
- 0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Single Write. (offset 18 in UPMA RAM) */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Burst Write. (offset 20 in UPMA RAM) */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Refresh (offset 30 in UPMA RAM) */
- 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
- 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Exception. (offset 3c in UPMA RAM) */
- 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-};
-
-/*********************************************************************/
-/* UPMA initilization table. */
-/*********************************************************************/
-const uint sdram_upm_table[] = {
- /* single read. (offset 0 in UPMA RAM) */
- 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */
-
- /* Burst Read. (offset 8 in UPMA RAM) */
- 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
- 0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Single Write. (offset 18 in UPMA RAM) */
- 0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
- 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Burst Write. (offset 20 in UPMA RAM) */
- 0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
- 0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Refresh (offset 30 in UPMA RAM) */
- 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
- 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Exception. (offset 3c in UPMA RAM) */
- 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
-};
-
-/*********************************************************************/
-/* UPMB initilization table. */
-/*********************************************************************/
-const uint mpm_upm_table[] = {
- /* single read. (offset 0 in upm RAM) */
- 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
- 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* burst read. (Offset 8 in upm RAM) */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* single write. (Offset 0x18 in upm RAM) */
- 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
- 0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* burst write. (Offset 0x20 in upm RAM) */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Refresh cycle, offset 0x30 */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Exception, 0ffset 0x3C */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-};
-
-
-int board_switch(void)
-{
- volatile pcmconf8xx_t *pcmp;
-
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- return ((pcmp->pcmc_pipr >> 24) & 0xf);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming UC100");
- } else {
- puts(str);
- }
-
- printf (" (SWITCH=%1X)\n", board_switch());
-
- return 0;
-}
-
-
-/*
- * Initialize SDRAM
- */
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /*---------------------------------------------------------------------*/
- /* Initialize the UPMA/UPMB registers with the appropriate table. */
- /*---------------------------------------------------------------------*/
- upmconfig (UPMA, (uint *) sdram_init_upm_table,
- sizeof (sdram_init_upm_table) / sizeof (uint));
- upmconfig (UPMB, (uint *) mpm_upm_table,
- sizeof (mpm_upm_table) / sizeof (uint));
-
- /*---------------------------------------------------------------------*/
- /* Memory Periodic Timer Prescaler: divide by 16 */
- /*---------------------------------------------------------------------*/
- memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
- memctl->memc_mbmr = CONFIG_SYS_MBMR_VAL;
-
- /*---------------------------------------------------------------------*/
- /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */
- /* for SDRAM */
- /* */
- /* NOTE: The refresh rate in MAMR reg is set according to the lowest */
- /* clock rate (16.67MHz) to allow proper operation for all ADS */
- /* clock frequencies. */
- /*---------------------------------------------------------------------*/
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- /*-------------------------------------------------------------------*/
- /* Wait at least 200 usec for DRAM to stabilize, this magic number */
- /* obtained from the init code. */
- /*-------------------------------------------------------------------*/
- udelay(200);
-
- memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
-
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
-
- /*---------------------------------------------------------------------*/
- /* run MRS command in location 5-8 of UPMB. */
- /*---------------------------------------------------------------------*/
- memctl->memc_mar = 0x88;
- /* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
-
- memctl->memc_mcr = 0x80002100;
- /* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
-
- udelay(200);
-
- /*---------------------------------------------------------------------*/
- /* Initialisation for normal access WV */
- /*---------------------------------------------------------------------*/
-
- /*---------------------------------------------------------------------*/
- /* Initialize the UPMA register with the appropriate table. */
- /*---------------------------------------------------------------------*/
- upmconfig (UPMA, (uint *) sdram_upm_table,
- sizeof (sdram_upm_table) / sizeof (uint));
-
- /*---------------------------------------------------------------------*/
- /* rerstore MBMR value (4-beat refresh burst.) */
- /*---------------------------------------------------------------------*/
- memctl->memc_mamr = CONFIG_SYS_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
-
- udelay(200);
-
- return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
-}
-
-
-int misc_init_r (void)
-{
- uchar val;
-
- /*
- * Make sure that RTC has clock output enabled (triggers watchdog!)
- */
- val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, 0x0D);
- val |= 0x80;
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, 0x0D, val);
-
- /*
- * Configure PHY to setup LED's correctly and use 100MBit, FD
- */
- mii_init();
-
- /* disable auto-negotiation, 100mbit, full-duplex */
- fec8xx_miiphy_write(NULL, 0, MII_BMCR, 0x2100);
-
- /* set LED's to Link, Transmit, Receive */
- fec8xx_miiphy_write(NULL, 0, MII_NWAYTEST, 0x4122);
-
- return 0;
-}
+++ /dev/null
-if TARGET_UC101
-
-config SYS_BOARD
- default "uc101"
-
-config SYS_VENDOR
- default "manroland"
-
-config SYS_CONFIG_NAME
- default "uc101"
-
-endif
+++ /dev/null
-UC101 BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/manroland/uc101/
-F: include/configs/uc101.h
-F: configs/uc101_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := uc101.o
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <malloc.h>
-
-/* some SIMPLE GPIO Pins */
-#define GPIO_USB_8 (31-12)
-#define GPIO_USB_7 (31-13)
-#define GPIO_USB_6 (31-14)
-#define GPIO_USB_0 (31-15)
-#define GPIO_PSC3_7 (31-18)
-#define GPIO_PSC3_6 (31-19)
-#define GPIO_PSC3_1 (31-22)
-#define GPIO_PSC3_0 (31-23)
-
-/* some simple Interrupt GPIO Pins */
-#define GPIO_PSC3_8 2
-#define GPIO_USB1_9 3
-
-#define GPT_OUT_0 0x00000027
-#define GPT_OUT_1 0x00000037
-#define GPT_DISABLE 0x00000000 /* GPT pin disabled */
-
-#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \
- pgpio->simple_ddr |= (1 << n); \
- pgpio->simple_gpioe |= (1 << n); \
- }
-
-#define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \
- pgpio->simple_gpioe |= (1 << n); \
- }
-
-#define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \
- (pgpio->simple_dvo | (1 << n)) : \
- (pgpio->simple_dvo & ~(1 << n)) )
-
-#define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1)
-#define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1)
-
-#define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \
- (pgpio->sint_dvo | (1 << n)) : \
- (pgpio->sint_dvo & ~(1 << n)) )
-
-#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \
- pgpio->sint_ddr |= (1 << n); \
- GP_SINT_SET_O(n, v); \
- pgpio->sint_gpioe |= (1 << n); \
- }
-
-#define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \
- pgpio->sint_gpioe |= (1 << n); \
- }
-
-#define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1)
-#define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1)
-
-#define GP_TIMER_ENABLE_O(n, v) ( \
- ((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \
- GPT_OUT_1 : \
- GPT_OUT_0 )
-
-#define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v)
-
-#define GP_TIMER_GET_O(n, v) ( \
- (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4)
-
-#define GP_TIMER_GET_I(n, v) ( \
- (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
- __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/* return dramsize + dramsize2; */
- return dramsize;
-}
-
-int checkboard (void)
-{
- puts ("Board: MAN UC101\n");
- /* clear the Display */
- *(char *)(CONFIG_SYS_DISP_CWORD) = 0x80;
- return 0;
-}
-
-static void init_ports (void)
-{
- volatile struct mpc5xxx_gpio *pgpio =
- (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
- GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */
- GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */
- GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */
- GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */
- GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */
- GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */
- GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */
- GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */
- GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */
- GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */
- GP_TIMER_ENABLE_O(4, 0); /* LED H4 */
- GP_TIMER_ENABLE_O(5, 0); /* LED H5 */
- GP_TIMER_ENABLE_O(3, 0); /* LED HB */
- GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-struct kbd_data_t {
- char s1;
-};
-
-struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
-{
- volatile struct mpc5xxx_gpio *pgpio =
- (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
- kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \
- GP_SIMP_GET_I(GPIO_USB_7) << 2 | \
- GP_SIMP_GET_I(GPIO_USB_6) << 1 | \
- GP_SIMP_GET_I(GPIO_USB_0) << 0;
- return kbd_data;
-}
-
-static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
-{
- char s1 = str[0];
-
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (s1 != kbd_data->s1) return -1;
- return 0;
-}
-
-static char *key_match (const struct kbd_data_t *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- char *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can be appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys; *suffix ||
- suffix == kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = getenv (cmd_name);
-
- return (cmd);
- }
- }
-
- return (NULL);
-}
-
-#endif /* CONFIG_PREBOOT */
-
-int misc_init_r (void)
-{
- /* Init the I/O ports */
- init_ports ();
-
-#ifdef CONFIG_PREBOOT
- struct kbd_data_t kbd_data;
- /* Decode keys */
- char *str = strdup (key_match (get_keys (&kbd_data)));
- /* Set or delete definition */
- setenv ("preboot", str);
- free (str);
-#endif /* CONFIG_PREBOOT */
- return 0;
-}
-
-int board_early_init_r (void)
-{
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
- *(vu_long *)MPC5XXX_BOOTCS_START =
- *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
- *(vu_long *)MPC5XXX_BOOTCS_STOP =
- *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
- /* Interbus enable it here ?? */
- *(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
- return 0;
-}
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
- /* Trigger HW Watchdog with TIMER_0 */
- *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1;
- *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0;
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_HMI1001=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MUCMC52=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_UC100=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_UC101=y
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+hmi1001 powerpc mpc5xxx - -
+mucmc52 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
+uc101 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
+uc100 powerpc mpc8xx - - Stefan Roese <sr@denx.de>
FPS850L powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
FPS860L powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
NSCU powerpc mpc8xx - -
miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
udelay(1000);
-#if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52)
- /* Set the LED configuration Register for the UC101
- and MUCMC52 Board */
- miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
-#endif
if (fec->xcv_type == MII10) {
/*
* Force 10Base-T, FDX operation
};
static char SMI_MCR[] = {
0x60, 0x01, 0x61, 0x00,
-#ifdef CONFIG_HMI1001
- 0x62, 0x74, /* Memory type is not configured by pins on HMI1001 */
-#endif
};
static char SMI_HCR[] = {
+++ /dev/null
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_HMI1001 1 /* HMI1001 board */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-#define CONFIG_DOS_PARTITION
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DISPLAY
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-#define CONFIG_MISC_INIT_R 1
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-
-#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x4000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_DISPLAY_BASE 0x80600000
-#define CONFIG_SYS_STATUS1_BASE 0x80600200
-#define CONFIG_SYS_STATUS2_BASE 0x80600300
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_DDR 1
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x714f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
-
-#ifdef CONFIG_POST
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR 0x00
-#define CONFIG_MII 1 /* MII PHY management */
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x01051004
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-/* 8Mbit SRAM @0x80100000 */
-#define CONFIG_SYS_CS1_START 0x80100000
-#define CONFIG_SYS_CS1_SIZE 0x00100000
-#define CONFIG_SYS_CS1_CFG 0x19B00
-
-/* FRAM 32Kbyte @0x80700000 */
-#define CONFIG_SYS_CS2_START 0x80700000
-#define CONFIG_SYS_CS2_SIZE 0x00008000
-#define CONFIG_SYS_CS2_CFG 0x19800
-
-/* Display H1, Status Inputs, EPLD @0x80600000 */
-#define CONFIG_SYS_CS3_START 0x80600000
-#define CONFIG_SYS_CS3_SIZE 0x00100000
-#define CONFIG_SYS_CS3_CFG 0x00019800
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-
-#define CONFIG_IDE_PREINIT 1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#define CONFIG_ATAPI 1
-
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_LOGO
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
-
-/*---------------------------------------------------------------------*/
-/* Display addresses */
-/*---------------------------------------------------------------------*/
-
-#define CONFIG_PDSP188x
-#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
-#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MUCMC52 1 /* MUCMC52 board */
-#define CONFIG_HOSTNAME mucmc52
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#include "manroland/common.h"
-#include "manroland/mpc5200-common.h"
-
-#define CONFIG_LAST_STAGE_INIT
-/*
- * Serial console configuration
- */
-#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
-
-#define CONFIG_CMD_PCI
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 67
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_SECT_SIZE 0x20000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_STATUS1_BASE 0x80600200
-#define CONFIG_SYS_STATUS2_BASE 0x80600300
-#define CONFIG_SYS_PMI_UNI_BASE 0x80800000
-#define CONFIG_SYS_PMI_BROAD_BASE 0x80810000
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-#define CONFIG_SYS_MEMTEST_END 0x00f00000
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000
-
-#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
-
-/* 8Mbit SRAM @0x80100000 */
-#define CONFIG_SYS_CS1_SIZE 0x00100000
-#define CONFIG_SYS_CS1_CFG 0x00019B00
-
-#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
-
-/* FRAM 32Kbyte @0x80700000 */
-#define CONFIG_SYS_CS2_START 0x80700000
-#define CONFIG_SYS_CS2_SIZE 0x00008000
-#define CONFIG_SYS_CS2_CFG 0x00019800
-
-/* Display H1, Status Inputs, EPLD @0x80600000 */
-#define CONFIG_SYS_CS3_START 0x80600000
-#define CONFIG_SYS_CS3_SIZE 0x00100000
-#define CONFIG_SYS_CS3_CFG 0x00019800
-
-/* PMI Unicast 32Kbyte @0x80800000 */
-#define CONFIG_SYS_CS6_START CONFIG_SYS_PMI_UNI_BASE
-#define CONFIG_SYS_CS6_SIZE 0x00008000
-#define CONFIG_SYS_CS6_CFG 0xFFFFF930
-
-/* PMI Broadcast 32Kbyte @0x80810000 */
-#define CONFIG_SYS_CS7_START CONFIG_SYS_PMI_BROAD_BASE
-#define CONFIG_SYS_CS7_SIZE 0x00008000
-#define CONFIG_SYS_CS7_CFG 0xFF00F930
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
-
-/*---------------------------------------------------------------------*/
-/* Display addresses */
-/*---------------------------------------------------------------------*/
-
-#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
-#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1
-#define CONFIG_MPC860T 1
-#define CONFIG_MPC862 1 /* enable 862 since the */
-#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */
-
-#define CONFIG_UC100 1 /* ...on a UC100 module */
-
-#define CONFIG_SYS_TEXT_BASE 0x40700000
-
-#define MPC8XX_FACT 4 /* Multiply by 4 */
-#define MPC8XX_XIN 25000000 /* 25.0 MHz in */
-#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
- /* define if cant' use get_gclk_freq */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/uc100/uImage\0" \
- "kernel_addr=40000000\0" \
- "ramdisk_addr=40100000\0" \
- "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \
- "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \
- "cp.b 100000 40700000 ${filesize};" \
- "setenv filesize;saveenv\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#undef CONFIG_STATUS_LED /* no status-led */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_RTC_MPC8xx
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
-#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
-
-/*
- * Power On Self Test support
- */
-#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_SPR )
-#undef CONFIG_POST
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_NETCONSOLE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if 0
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*-----------------------------------------------------------------------
- * Address accessed to reset the board - must not be mapped/assigned
- */
-#define CONFIG_SYS_RESET_ADDRESS 0x90000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK 0x00000000
-#define CONFIG_SYS_SCCR (SCCR_EBDF11)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (0x00000d24)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
-#define CONFIG_SYS_OR1_PRELIM 0xfc000a00
-#define CONFIG_SYS_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
-#define CONFIG_SYS_OR2_PRELIM 0xfff00d24
-#define CONFIG_SYS_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
-#define CONFIG_SYS_OR3_PRELIM 0xffff8f44
-#define CONFIG_SYS_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
-#define CONFIG_SYS_OR4_PRELIM 0xffff0300
-#define CONFIG_SYS_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
-#define CONFIG_SYS_OR5_PRELIM 0xffff8db0
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- * 100 Mhz => 100.000.000 / Divider = 195
- */
-
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-#define CONFIG_SYS_MAMR_PTA 98
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#define CONFIG_SYS_MAMR_VAL 0x30904114 /* for SDRAM */
-#define CONFIG_SYS_MBMR_VAL 0xff001111 /* for Interbus-MPM */
-
-/*-----------------------------------------------------------------------
- * I2C stuff
- */
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (24C164)
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-
-#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
-#define FEC_ENET
-#define CONFIG_MII
-#define CONFIG_MII_INIT 1
-#define CONFIG_SYS_DISCOVER_PHY 1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2003-2009
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_UC101 1 /* UC101 board */
-#define CONFIG_HOSTNAME uc101
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
-
-#include "manroland/common.h"
-#include "manroland/mpc5200-common.h"
-
-/*
- * Serial console configuration
- */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 140
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_IB_MASTER 0xc0510000 /* CS 6 */
-#define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */
-
-/* SRAM */
-#define CONFIG_SYS_SRAM_SIZE 0x200000
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x4d558044
-
-#define CONFIG_SYS_MEMTEST_START 0x00300000
-#define CONFIG_SYS_MEMTEST_END 0x00f00000
-
-#define CONFIG_SYS_LOAD_ADDR 0x300000
-
-#define CONFIG_SYS_BOOTCS_CFG 0x00045D00
-
-/* 8Mbit SRAM @0x80100000 */
-#define CONFIG_SYS_CS1_SIZE 0x00200000
-#define CONFIG_SYS_CS1_CFG 0x21D00
-
-/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
-#define CONFIG_SYS_CS3_START CONFIG_SYS_DISPLAY_BASE
-#define CONFIG_SYS_CS3_SIZE 0x00000100
-#define CONFIG_SYS_CS3_CFG 0x00081802
-
-/* Interbus Master 16 Bit */
-#define CONFIG_SYS_CS6_START CONFIG_SYS_IB_MASTER
-#define CONFIG_SYS_CS6_SIZE 0x00010000
-#define CONFIG_SYS_CS6_CFG 0x00FF3500
-
-/* Interbus EPLD 8 Bit */
-#define CONFIG_SYS_CS7_START CONFIG_SYS_IB_EPLD
-#define CONFIG_SYS_CS7_SIZE 0x00010000
-#define CONFIG_SYS_CS7_CFG 0x00081800
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus*/
-
-/*---------------------------------------------------------------------*/
-/* Display addresses */
-/*---------------------------------------------------------------------*/
-#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
-#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
-
-#endif /* __CONFIG_H */
# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
# define CONFIG_PCMCIA_SLOT_A
-#elif defined(CONFIG_UC100) /* The UC100 use SLOT_B */
-# define CONFIG_PCMCIA_SLOT_B
#else
# error "PCMCIA Slot not configured"
#endif
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