]> git.sur5r.net Git - u-boot/commitdiff
tegra: Add SDMMC support to funcmux
authorSimon Glass <sjg@chromium.org>
Wed, 11 Jan 2012 12:42:25 +0000 (12:42 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 12 Feb 2012 09:11:22 +0000 (10:11 +0100)
This adds support for SDMMC ports to the funcmux. Only one
option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit
wide SDIO interface where available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/cpu/armv7/tegra2/funcmux.c
arch/arm/include/asm/arch-tegra2/funcmux.h

index 4fe6e06531ccd55737755222adf3b6bb30341a3f..c1d2dfec5f02dea5c8631ca9222c3d7be13cb486 100644 (file)
@@ -106,6 +106,69 @@ int funcmux_select(enum periph_id id, int config)
                }
                break;
 
+       case PERIPH_ID_SDMMC2:
+               if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
+                       pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
+                       pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
+
+                       pinmux_tristate_disable(PINGRP_DTA);
+                       pinmux_tristate_disable(PINGRP_DTD);
+               }
+               break;
+
+       case PERIPH_ID_SDMMC3:
+               switch (config) {
+               case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
+                       pinmux_set_func(PINGRP_SLXA, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PINGRP_SLXC, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PINGRP_SLXD, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PINGRP_SLXK, PMUX_FUNC_SDIO3);
+
+                       pinmux_tristate_disable(PINGRP_SLXA);
+                       pinmux_tristate_disable(PINGRP_SLXC);
+                       pinmux_tristate_disable(PINGRP_SLXD);
+                       pinmux_tristate_disable(PINGRP_SLXK);
+                       /* fall through */
+
+               case FUNCMUX_SDMMC3_SDB_4BIT:
+                       pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
+
+                       pinmux_tristate_disable(PINGRP_SDB);
+                       pinmux_tristate_disable(PINGRP_SDC);
+                       pinmux_tristate_disable(PINGRP_SDD);
+                       bad_config = 0;
+                       break;
+               }
+               break;
+
+       case PERIPH_ID_SDMMC4:
+               switch (config) {
+               case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
+                       pinmux_set_func(PINGRP_ATC, PMUX_FUNC_SDIO4);
+                       pinmux_set_func(PINGRP_ATD, PMUX_FUNC_SDIO4);
+
+                       pinmux_tristate_disable(PINGRP_ATC);
+                       pinmux_tristate_disable(PINGRP_ATD);
+                       break;
+
+               case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
+                       pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
+                       pinmux_tristate_disable(PINGRP_GME);
+                       /* fall through */
+
+               case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
+                       pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
+                       pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+
+                       pinmux_tristate_disable(PINGRP_ATB);
+                       pinmux_tristate_disable(PINGRP_GMA);
+                       bad_config = 0;
+                       break;
+               }
+               break;
+
        default:
                debug("%s: invalid periph_id %d", __func__, id);
                return -1;
index d1845238009b291389bf2d129b7bba3344ad85e9..ae73c72ebe20c317f2951f740c5d621f54af492e 100644 (file)
@@ -39,6 +39,14 @@ enum {
        FUNCMUX_I2C2_DDC = 0,
        FUNCMUX_I2C2_PTA,
        FUNCMUX_I2C3_DTF = 0,
+
+       /* SDMMC configs */
+       FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0,
+       FUNCMUX_SDMMC3_SDB_4BIT = 0,
+       FUNCMUX_SDMMC3_SDB_SLXA_8BIT,
+       FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0,
+       FUNCMUX_SDMMC4_ATB_GMA_4_BIT,
+       FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT,
 };
 
 /**