This adds drivers model support of serial port to Lager board,
and migrate serial port to drivers model.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 #include <common.h>
 #include <malloc.h>
 #include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
        val |= 0x02;
        i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 }
+
+static const struct sh_serial_platdata serial_platdata = {
+       .base = SCIF0_BASE,
+       .type = PORT_SCIF,
+       .clk = 14745600,
+       .clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(lager_serials) = {
+       .name = "serial_sh",
+       .platdata = &serial_platdata,
+};
 
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_LAGER=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
 
 
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE
-#define CONFIG_CONS_SCIF0
-#define CONFIG_SCIF_USE_EXT_CLK
 
 /* SPI */
 #define CONFIG_SPI
 #define CONFIG_PLL1_DIV2_CLK_FREQ      (CONFIG_PLL1_CLK_FREQ / 2)
 #define CONFIG_MP_CLK_FREQ     (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
 #define CONFIG_HP_CLK_FREQ     (CONFIG_PLL1_CLK_FREQ / 12)
-#define CONFIG_SH_SCIF_CLK_FREQ        14745600 /* External Clock */
 
 #define CONFIG_SYS_TMU_CLK_DIV 4