Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init

Passing fewer arguments is better and mem_iv_size is never
used. Let's keep only one argument and make it cleaner.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c
index cca925e42c34cc805dc9055bed79857501c33139..9b6ee69f4671e5beed37625fb896e46f22543be1 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/dmc_common.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
@@ -162,7 +162,7 @@ void mem_ctrl_init(int reset)
 
        /* If there are any other memory variant, add their init call below */
        if (param->mem_type == DDR_MODE_DDR3) {
-               ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
+               ret = ddr3_mem_ctrl_init(mem, reset);
                if (ret) {
                        /* will hang if failed to init memory control */
                        while (1)

diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 487e6f423fc2401d780841db940750ccd7f858e8..4481ab46bffd88b7783ef854c4dce4d22cf8fee0 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -28,8 +28,7 @@ static void reset_phy_ctrl(void)
        writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-                      int reset)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 {
        unsigned int val;
        struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
@@ -221,8 +220,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 #endif
 
 #ifdef CONFIG_EXYNOS5420
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-                      int reset)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 {
        struct exynos5420_clock *clk =
                (struct exynos5420_clock *)samsung_get_base_clock();
@@ -244,7 +242,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
        tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
        tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
                                                        + DMC_OFFSET);
-
        /* Enable PAUSE for DREX */
        setbits_le32(&clk->pause, ENABLE_BIT);
 

diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 53b0ace6e3f7966699b6dda8cf0268a2dcaf703c..314d6f4e57b8b20de748c9fde8f06f9b23ee08fb 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -890,16 +890,11 @@ enum {
 /*
  * Memory variant specific initialization code for DDR3
  *
- * @param mem          Memory timings for this memory type.
- * @param mem_iv_size  Memory interleaving size is a configurable parameter
- *                     which the DMC uses to decide how to split a memory
- *                     chunk into smaller chunks to support concurrent
- *                     accesses; may vary across boards.
+ * @param mem          Memory timings for this memory type.
  * @param reset         Reset DDR PHY during initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-                       int reset);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
 
 /* Memory variant specific initialization code for LPDDR3 */
 void lpddr3_mem_ctrl_init(void);