sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMA

Make sure definitions for NAND clock and DMA gate bits are the same
across boards.

Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 63c33190b8cd5a036d799a4265c90a13e866f7cc..58aff1687af357eca4439d1c55243def8cc8dc56 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -39,7 +39,7 @@ struct sunxi_ccm_reg {
        u32 apb0_gate;          /* 0x68 apb0 module clock gating */
        u32 apb1_gate;          /* 0x6c apb1 module clock gating */
        u8 res4[0x10];
-       u32 nand_sclk_cfg;      /* 0x80 nand sub clock control */
+       u32 nand0_clk_cfg;      /* 0x80 nand sub clock control */
        u32 ms_sclk_cfg;        /* 0x84 memory stick sub clock control */
        u32 sd0_clk_cfg;        /* 0x88 sd0 clock control */
        u32 sd1_clk_cfg;        /* 0x8c sd1 clock control */
@@ -177,7 +177,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_ACE            16
 #define AHB_GATE_OFFSET_DLL            15
 #define AHB_GATE_OFFSET_SDRAM          14
-#define AHB_GATE_OFFSET_NAND           13
+#define AHB_GATE_OFFSET_NAND0          13
 #define AHB_GATE_OFFSET_MS             12
 #define AHB_GATE_OFFSET_MMC3           11
 #define AHB_GATE_OFFSET_MMC2           10

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 6465f215e8a01252239bc2ce027e983424e9d285..8a26b9fc51ab280f2e2870aa9419d8b070755a1f 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -215,11 +215,14 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB0           24
 #define AHB_GATE_OFFSET_MCTL           14
 #define AHB_GATE_OFFSET_GMAC           17
+#define AHB_GATE_OFFSET_NAND0          13
+#define AHB_GATE_OFFSET_NAND1          12
 #define AHB_GATE_OFFSET_MMC3           11
 #define AHB_GATE_OFFSET_MMC2           10
 #define AHB_GATE_OFFSET_MMC1           9
 #define AHB_GATE_OFFSET_MMC0           8
 #define AHB_GATE_OFFSET_MMC(n)         (AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_DMA            6
 #define AHB_GATE_OFFSET_SS             5
 
 /* ahb_gate1 offsets */

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index c506b0a98f4f927cffea964929906a0c1e4164ee..a61934fb366173ca2682d880d9386091a5123c2f 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -42,7 +42,7 @@ struct sunxi_ccm_reg {
        u32 clk_output_b;       /* 0x184 clk_output_a */
        u8 reserved5[0x278];    /* 0x188 */
 
-       u32 nand0_clk_cfg0;     /* 0x400 nand0 clock configuration0 */
+       u32 nand0_clk_cfg;      /* 0x400 nand0 clock configuration0 */
        u32 nand0_clk_cfg1;     /* 0x404 nand1 clock configuration */
        u8 reserved6[0x08];     /* 0x408 */
        u32 sd0_clk_cfg;        /* 0x410 sd0 clock configuration */
@@ -113,8 +113,12 @@ struct sunxi_ccm_reg {
 
 /* ahb_gate0 fields */
 /* On sun9i all sdc-s share their ahb gate, so ignore (x) */
+#define AHB_GATE_OFFSET_NAND0          13
 #define AHB_GATE_OFFSET_MMC(x)         8
 
+/* ahb gate1 field */
+#define AHB_GATE_OFFSET_DMA            24
+
 /* apb1_gate fields */
 #define APB1_GATE_UART_SHIFT           16
 #define APB1_GATE_UART_MASK            (0xff << APB1_GATE_UART_SHIFT)