Add first draft of the MPC8641HPCN doc/README.

Signed-off-by: Jon Loeliger <jdl@jdl.com>

diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn
new file mode 100644 (file)
index 0000000..907a911
--- /dev/null
+++ b/doc/README.mpc8641hpcn
@@ -0,0 +1,123 @@
+Freescale MPC8641HPCN board
+===========================
+
+Created 05/24/2006 Haiying Wang
+-------------------------------
+
+1. Building U-Boot
+------------------
+The 86xx HPCN code base is known to compile using:
+    Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
+
+    $ make MPC8641HPCN_config
+    Configuring for MPC8641HPCN board...
+
+    $ make
+
+
+2. Switch and Jumper Setting
+----------------------------
+Jumpers:
+       J14 Pins 1-2 (near plcc32 socket)
+
+Switches:
+       SW1(1-5) = 01100        CFG_COREPLL     = 01000 :: CORE =   2:1
+                                                 01100 :: CORE = 2.5:1
+                                                 10000 :: CORE =   3:1
+                                                 11100 :: CORE = 3.5:1
+                                                 10100 :: CORE =   4:1
+                                                 01110 :: CORE = 4.5:1
+       SW1(6-8) = 001          CFG_SYSCLK      = 000   :: SYSCLK = 33MHz
+                                                 001   :: SYSCLK = 40MHz
+
+       SW2(1-4) = 1100         CFG_CCBPLL      = 0010  :: 2X 
+                                                 0100  :: 4X
+                                                 0110  :: 6X
+                                                 1000  :: 8X
+                                                 1010  :: 10X
+                                                 1100  :: 12X
+                                                 1110  :: 14X
+                                                 0000  :: 16X
+       SW2(5-8) = 1110         CFG_BOOTLOC     = 1110  :: boot 16-bit localbus
+
+       SW3(1-7) = 0011000      CFG_VID         = 0011000 :: VCORE = 1.2V
+                                                 0100000 :: VCORE = 1.11V
+       SW3(8)   = 0            VCC_PLAT        = 0     :: VCC_PLAT = 1.2V
+                                                 1     :: VCC_PLAT = 1.0V
+
+       SW4(1-2) = 11           CFG_HOSTMODE    = 11    :: both prots host/root
+       SW4(3-4) = 11           CFG_BOOTSEQ     = 11    :: no boot seq
+       SW4(5-8) = 0011         CFG_IOPORT      = 0011  :: both PEX
+
+       SW5(1)   = 1            CFG_FLASHMAP    = 1     :: boot from flash
+                                                 0     :: boot from PromJet
+       SW5(2)   = 1            CFG_FLASHBANK   = 1     :: swap upper/lower
+                                                        halves (virtual banks)
+                                                 0     :: normal
+       SW5(3)   = 0            CFG_FLASHWP     = 0     :: not protected
+       SW5(4)   = 0            CFG_PORTDIV     = 1     :: 2:1 for PD4
+                                                          1:1 for PD6
+       SW5(5-6) = 11           CFG_PIXISOPT    = 11    :: s/w determined
+       SW5(7-8) = 11           CFG_LADOPT      = 11    :: s/w determined
+
+       SW6(1)   = 1            CFG_CPUBOOT     = 1     :: no boot holdoff
+       SW6(2)   = 1            CFG_BOOTADDR    = 1     :: no traslation
+       SW6(3-5) = 000          CFG_REFCLKSEL   = 000   :: 100MHZ
+       SW6(6)   = 1            CFG_SERROM_ADDR= 1      ::
+       SW6(7)   = 1            CFG_MEMDEBUG    = 1     ::
+       SW6(8)   = 1            CFG_DDRDEBUG    = 1     ::
+
+       SW8(1)   = 1            ACZ_SYNC        = 1     :: 48MHz on TP49
+       SW8(2)   = 1            ACB_SYNC        = 1     :: THRMTRIP disabled
+       SW8(3)   = 1            ACZ_SDOUT       = 1     :: p4 mode
+       SW8(4)   = 1            ACB_SDOUT       = 1     :: PATA freq. = 133MHz
+       SW8(5)   = 0            SUSLED          = 0     :: SouthBridge Mode
+       SW8(6)   = 0            SPREAD          = 0     :: REFCLK SSCG Disabled
+       SW8(7)   = 1            ACPWR           = 1     :: non-battery
+       SW8(8)   = 0            CFG_IDWP        = 0     :: write enable
+
+
+3. Flash U-Boot
+---------------
+The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
+It is possible to use either half to boot using u-boot.  Switch 5 bit 2
+is used for this purpose.
+
+0xFF800000 to 0xFFBFFFFF - 4MB
+0xFFC00000 to 0xFFFFFFFF - 4MB
+When this bit is 0, U-Boot is at 0xFFF00000.
+When this bit is 1, U-Boot is at 0xFFB00000.
+
+Use the above mentioned flash commands to program the other half, and
+use switch 5, bit 2 to alternate between the halves.  Note: The booting
+version of U-Boot will always be at 0xFFF00000.
+
+To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
+
+       tftp 1000000 u-boot.bin
+       protect off all
+       erase fff00000 ffffffff
+       cp.b 1000000 fff00100 80000
+
+To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
+
+       tftp 1000000 u-boot.bin
+       erase ffb00000 ffbfffff
+       cp.b 1000000 ffb00100 80000
+
+
+4. Memory Map
+-------------
+
+       Memory Range                    Device          Size            
+       ------------                    ------          ----
+       0x0000_0000     0x7fff_ffff     DDR             2G
+       0x8000_0000     0x9fff_ffff     PCI1/PEX1 MEM   512M
+       0xa000_0000     0xafff_ffff     PCI2/PEX2 MEM   512M
+       0xf800_0000     0xf80f_ffff     CCSR            1M
+       0xf810_0000     0xf81f_ffff     PIXIS           1M
+       0xf840_0000     0xf840_3fff     Stack space     32K
+       0xe200_0000     0xe2ff_ffff     PCI1/PEX1 IO    512M
+       0xe300_0000     0xe3ff_ffff     PCI2/PEX2 IO    512M
+       0xfe00_0000     0xfeff_ffff     Flash(alternate)16M
+       0xff00_0000     0xffff_ffff     Flash(boot bank)16M