]> git.sur5r.net Git - u-boot/commitdiff
powerpc/p4080: Add support for the P4080DS board
authorKumar Gala <galak@kernel.crashing.org>
Thu, 15 Jul 2010 21:49:03 +0000 (16:49 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Sun, 1 Aug 2010 16:18:40 +0000 (11:18 -0500)
Add support for the P4080DS board, with the following features:

* 36-bit only
* Boots from NOR flash
* FMAN drivers NOT supported
* SPD DDR initialization

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Ashish Kalra <Ashish.Kalra@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Lan Chunhe-B25806 <b25806@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
12 files changed:
MAKEALL
board/freescale/common/Makefile
board/freescale/corenet_ds/Makefile [new file with mode: 0644]
board/freescale/corenet_ds/config.mk [new file with mode: 0644]
board/freescale/corenet_ds/corenet_ds.c [new file with mode: 0644]
board/freescale/corenet_ds/ddr.c [new file with mode: 0644]
board/freescale/corenet_ds/law.c [new file with mode: 0644]
board/freescale/corenet_ds/pci.c [new file with mode: 0644]
board/freescale/corenet_ds/tlb.c [new file with mode: 0644]
boards.cfg
include/configs/P4080DS.h [new file with mode: 0644]
include/configs/corenet_ds.h [new file with mode: 0644]

diff --git a/MAKEALL b/MAKEALL
index 2133559e82a0fd3f059d673eb7f147e6c063e4fe..b34ae3328844e7bb569a874f0bff5f6767e9d189 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -428,6 +428,7 @@ LIST_85xx="         \
        P2020RDB_NAND   \
        P2020RDB_SDCARD \
        P2020RDB_SPIFLASH       \
+       P4080DS         \
        PM854           \
        PM856           \
        sbc8540         \
index 2d48d7ea32839f956c26c2f80bf3ff91b2a47aac..f93045ff980b783f1cf014b8b9640d5705d4e093 100644 (file)
@@ -46,6 +46,7 @@ COBJS-$(CONFIG_MPC8536DS)     += ics307_clk.o
 COBJS-$(CONFIG_MPC8572DS)      += ics307_clk.o
 COBJS-$(CONFIG_P1022DS)                += ics307_clk.o
 COBJS-$(CONFIG_P2020DS)                += ics307_clk.o
+COBJS-$(CONFIG_P4080DS)                += ics307_clk.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
new file mode 100644 (file)
index 0000000..8aa7255
--- /dev/null
@@ -0,0 +1,55 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS-y        += $(BOARD).o
+COBJS-$(CONFIG_DDR_SPD)        += ddr.o
+COBJS-$(CONFIG_PCI)    += pci.o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+       rm -f $(OBJS) $(SOBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk
new file mode 100644 (file)
index 0000000..72db24e
--- /dev/null
@@ -0,0 +1,30 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# P4080DS board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
+
+RESET_VECTOR_ADDRESS = 0xeffffffc
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
new file mode 100644 (file)
index 0000000..3cdefb3
--- /dev/null
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+extern void pci_of_setup(void *blob, bd_t *bd);
+
+#include "../common/ngpixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+int checkboard (void)
+{
+       u8 sw;
+       struct cpu_type *cpu = gd->cpu;
+
+       printf("Board: %sDS, ", cpu->name);
+       printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+               in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+       sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+       sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+       if (sw < 0x8)
+               printf("vBank: %d\n", sw);
+       else if (sw == 0x8)
+               puts("Promjet\n");
+       else if (sw == 0x9)
+               puts("NAND\n");
+       else
+               printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
+
+#ifdef CONFIG_PHYS_64BIT
+       puts("36-bit Addressing\n");
+#endif
+
+       /* Display the actual SERDES reference clocks as configured by the
+        * dip switches on the board.  Note that the SWx registers could
+        * technically be set to force the reference clocks to match the
+        * values that the SERDES expects (or vice versa).  For now, however,
+        * we just display both values and hope the user notices when they
+        * don't match.
+        */
+       puts("SERDES Reference Clocks: ");
+       sw = in_8(&PIXIS_SW(3));
+       printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
+       printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
+       printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
+
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+       /*
+        * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
+        * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
+        * the noise introduced by these unterminated and unused clock pairs.
+        */
+       setbits_be32(&gur->ddrclkdr, 0x001B001B);
+
+       return 0;
+}
+
+int board_early_init_r(void)
+{
+       const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+       const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+       /*
+        * Remap Boot flash + PROMJET region to caching-inhibited
+        * so that flash can be erased properly.
+        */
+
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+       flush_dcache();
+       invalidate_icache();
+
+       /* invalidate existing TLB entry for flash + promjet */
+       disable_tlb(flash_esel);
+
+       set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+                       0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
+
+       set_liodns();
+       setup_portals();
+
+#ifdef CONFIG_SRIO1
+       if (is_serdes_configured(SRIO1)) {
+               set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M,
+                               LAW_TRGT_IF_RIO_1);
+       } else {
+               printf ("    SRIO1: disabled\n");
+       }
+#else
+       setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */
+#endif
+
+#ifdef CONFIG_SRIO2
+       if (is_serdes_configured(SRIO2)) {
+               set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M,
+                               LAW_TRGT_IF_RIO_2);
+       } else {
+               printf ("    SRIO2: disabled\n");
+       }
+#else
+       setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */
+#endif
+
+       return 0;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+       switch(clock) {
+       case SRDS_PLLCR0_RFCK_SEL_100:
+               return "100";
+       case SRDS_PLLCR0_RFCK_SEL_125:
+               return "125";
+       case SRDS_PLLCR0_RFCK_SEL_156_25:
+               return "156.25";
+       default:
+               return "???";
+       }
+}
+
+#define NUM_SRDS_BANKS 3
+
+int misc_init_r(void)
+{
+       serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+       u32 actual[NUM_SRDS_BANKS];
+       unsigned int i;
+       u8 sw3;
+
+       /* Warn if the expected SERDES reference clocks don't match the
+        * actual reference clocks.  This needs to be done after calling
+        * p4080_erratum_serdes8(), since that function may modify the clocks.
+        */
+       sw3 = in_8(&PIXIS_SW(3));
+       actual[0] = (sw3 & 0x40) ?
+               SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
+       actual[1] = (sw3 & 0x20) ?
+               SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+       actual[2] = (sw3 & 0x10) ?
+               SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+
+       for (i = 0; i < NUM_SRDS_BANKS; i++) {
+               u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+               if (expected != actual[i]) {
+                       printf("Warning: SERDES bank %u expects reference clock"
+                              " %sMHz, but actual is %sMHz\n", i + 1,
+                              serdes_clock_to_string(expected),
+                              serdes_clock_to_string(actual[i]));
+               }
+       }
+
+       return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+       phys_size_t dram_size;
+
+       puts("Initializing....\n");
+
+       dram_size = fsl_ddr_sdram();
+
+       setup_ddr_tlbs(dram_size / 0x100000);
+
+       puts("    DDR: ");
+       return dram_size;
+}
+
+#ifdef CONFIG_MP
+void board_lmb_reserve(struct lmb *lmb)
+{
+       cpu_mp_lmb_reserve(lmb);
+}
+#endif
+
+void ft_srio_setup(void *blob)
+{
+#ifdef CONFIG_SRIO1
+       if (!is_serdes_configured(SRIO1)) {
+               fdt_del_node_and_alias(blob, "rio0");
+       }
+#else
+       fdt_del_node_and_alias(blob, "rio0");
+#endif
+#ifdef CONFIG_SRIO2
+       if (!is_serdes_configured(SRIO2)) {
+               fdt_del_node_and_alias(blob, "rio1");
+       }
+#else
+       fdt_del_node_and_alias(blob, "rio1");
+#endif
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       phys_addr_t base;
+       phys_size_t size;
+
+       ft_cpu_setup(blob, bd);
+
+       ft_srio_setup(blob);
+
+       base = getenv_bootm_low();
+       size = getenv_bootm_size();
+
+       fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+       pci_of_setup(blob, bd);
+#endif
+
+       fdt_fixup_liodn(blob);
+}
+
+int board_eth_init(bd_t *bis)
+{
+       return pci_eth_init(bis);
+}
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
new file mode 100644 (file)
index 0000000..82b2b4f
--- /dev/null
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+       int ret;
+
+       ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+       if (ret) {
+               debug("DDR: failed to read SPD from address %u\n", i2c_address);
+               memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
+       }
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+       return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+                     unsigned int ctrl_num)
+{
+       unsigned int i;
+       unsigned int i2c_address = 0;
+
+       for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+               if (ctrl_num == 0 && i == 0)
+                       i2c_address = SPD_EEPROM_ADDRESS1;
+               else if (ctrl_num == 1 && i == 0)
+                       i2c_address = SPD_EEPROM_ADDRESS2;
+
+               get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+       }
+}
+
+typedef struct {
+       u32 datarate_mhz_low;
+       u32 datarate_mhz_high;
+       u32 n_ranks;
+       u32 clk_adjust;
+       u32 cpo;
+       u32 write_data_delay;
+       u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+
+
+/* XXX: these values need to be checked for all interleaving modes.  */
+/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
+ *      seem reliable, but errors will appear when memory intensive
+ *      program is run. */
+/* XXX: Single rank at 800 MHz is OK.  */
+const board_specific_parameters_t board_specific_parameters[][20] = {
+       {
+       /*      memory controller 0                     */
+       /*        lo|  hi|  num|  clk| cpo|wrdata|2T    */
+       /*       mhz| mhz|ranks|adjst|    | delay|      */
+               {  0, 333,    2,    6,   7,    3,  0},
+               {334, 400,    2,    6,   9,    3,  0},
+               {401, 549,    2,    6,  11,    3,  0},
+               {550, 680,    2,    1,  10,    5,  0},
+               {681, 850,    2,    1,  12,    5,  0},
+               {851, 1050,   2,    1,  12,    5,  0},
+               {1051, 1250,  2,    1,  15,    4,  0},
+               {1251, 1350,  2,    1,  15,    4,  0},
+               {  0, 333,    1,    6,   7,    3,  0},
+               {334, 400,    1,    6,   9,    3,  0},
+               {401, 549,    1,    6,  11,    3,  0},
+               {550, 680,    1,    1,  10,    5,  0},
+               {681, 850,    1,    1,  12,    5,  0}
+       },
+
+       {
+       /*      memory controller 1                     */
+       /*        lo|  hi|  num|  clk| cpo|wrdata|2T    */
+       /*       mhz| mhz|ranks|adjst|    | delay|      */
+               {  0, 333,    2,     6,  7,    3,  0},
+               {334, 400,    2,     6,  9,    3,  0},
+               {401, 549,    2,     6, 11,    3,  0},
+               {550, 680,    2,     1, 11,    6,  0},
+               {681, 850,    2,     1, 13,    6,  0},
+               {851, 1050,   2,     1, 13,    6,  0},
+               {1051, 1250,  2,     1, 15,    4,  0},
+               {1251, 1350,  2,     1, 15,    4,  0},
+               {  0, 333,    1,     6,  7,    3,  0},
+               {334, 400,    1,     6,  9,    3,  0},
+               {401, 549,    1,     6, 11,    3,  0},
+               {550, 680,    1,     1, 11,    6,  0},
+               {681, 850,    1,     1, 13,    6,  0}
+       }
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+                               dimm_params_t *pdimm,
+                               unsigned int ctrl_num)
+{
+       const board_specific_parameters_t *pbsp =
+                               &(board_specific_parameters[ctrl_num][0]);
+       u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+                               sizeof(board_specific_parameters[0][0]);
+       u32 i;
+       ulong ddr_freq;
+
+       /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+        * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+        * there are two dimms in the controller, set odt_rd_cfg to 3 and
+        * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+        */
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               if (i&1) {      /* odd CS */
+                       popts->cs_local_opts[i].odt_rd_cfg = 0;
+                       popts->cs_local_opts[i].odt_wr_cfg = 1;
+               } else {        /* even CS */
+                       if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+                               popts->cs_local_opts[i].odt_rd_cfg = 0;
+                               popts->cs_local_opts[i].odt_wr_cfg = 1;
+                       } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+                       popts->cs_local_opts[i].odt_rd_cfg = 3;
+                       popts->cs_local_opts[i].odt_wr_cfg = 3;
+                       }
+               }
+       }
+
+       /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+        * freqency and n_banks specified in board_specific_parameters table.
+        */
+       ddr_freq = get_ddr_freq(0) / 1000000;
+       for (i = 0; i < num_params; i++) {
+               if (ddr_freq >= pbsp->datarate_mhz_low &&
+                   ddr_freq <= pbsp->datarate_mhz_high &&
+                   pdimm->n_ranks == pbsp->n_ranks) {
+                       popts->cpo_override = 0xff; /* force auto CPO calibration */
+                       popts->write_data_delay = 2;
+                       popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */
+                       popts->twoT_en = pbsp->force_2T;
+               }
+               pbsp++;
+       }
+
+       /*
+        * Factors to consider for half-strength driver enable:
+        *      - number of DIMMs installed
+        */
+       popts->half_strength_driver_enable = 0;
+       /*
+        * Write leveling override
+        */
+       popts->wrlvl_override = 1;
+       popts->wrlvl_sample = 0xa;
+       popts->wrlvl_start = 0x7;
+       /*
+        * Rtt and Rtt_WR override
+        */
+       popts->rtt_override = 1;
+       popts->rtt_override_value = DDR3_RTT_120_OHM;
+       popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
+
+       /* Enable ZQ calibration */
+       popts->zq_en = 1;
+}
diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c
new file mode 100644 (file)
index 0000000..43b4b97
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+       SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+       SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+       SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+       SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+       SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c
new file mode 100644 (file)
index 0000000..2994e36
--- /dev/null
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+void pci_init_board(void)
+{
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       struct fsl_pci_info pci_info[3];
+       u32 devdisr;
+       int first_free_busno = 0;
+       int num = 0;
+
+       int pcie_ep, pcie_configured;
+
+       devdisr = in_be32(&gur->devdisr);
+
+       debug ("   pci_init_board: devdisr=%x\n", devdisr);
+
+#ifdef CONFIG_PCIE1
+       pcie_configured = is_serdes_configured(PCIE1);
+
+       if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) {
+               set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M,
+                               LAW_TRGT_IF_PCIE_1);
+               set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
+                               LAW_TRGT_IF_PCIE_1);
+               SET_STD_PCIE_INFO(pci_info[num], 1);
+               pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+               printf("    PCIE1 connected to Slot 1 as %s (base addr %lx)\n",
+                               pcie_ep ? "End Point" : "Root Complex",
+                               pci_info[num].regs);
+               first_free_busno = fsl_pci_init_port(&pci_info[num++],
+                               &pcie1_hose, first_free_busno);
+       } else {
+               printf ("    PCIE1: disabled\n");
+       }
+#else
+       setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+       pcie_configured = is_serdes_configured(PCIE2);
+
+       if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) {
+               set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M,
+                               LAW_TRGT_IF_PCIE_2);
+               set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
+                               LAW_TRGT_IF_PCIE_2);
+               SET_STD_PCIE_INFO(pci_info[num], 2);
+               pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+               printf("    PCIE2 connected to Slot 3 as %s (base addr %lx)\n",
+                               pcie_ep ? "End Point" : "Root Complex",
+                               pci_info[num].regs);
+               first_free_busno = fsl_pci_init_port(&pci_info[num++],
+                               &pcie2_hose, first_free_busno);
+       } else {
+               printf ("    PCIE2: disabled\n");
+       }
+#else
+       setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE3
+       pcie_configured = is_serdes_configured(PCIE3);
+
+       if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) {
+               set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
+                               LAW_TRGT_IF_PCIE_3);
+               set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
+                               LAW_TRGT_IF_PCIE_3);
+               SET_STD_PCIE_INFO(pci_info[num], 3);
+               pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
+               printf("    PCIE3 connected to Slot 2 as %s (base addr %lx)\n",
+                               pcie_ep ? "End Point" : "Root Complex",
+                               pci_info[num].regs);
+               first_free_busno = fsl_pci_init_port(&pci_info[num++],
+                               &pcie3_hose, first_free_busno);
+       } else {
+               printf ("    PCIE3: disabled\n");
+       }
+#else
+       setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
+#endif
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+       FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
new file mode 100644 (file)
index 0000000..1ae0416
--- /dev/null
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+       /* TLB 0 - for temp stack in cache */
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+
+       SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+
+       /* TLB 1 */
+       /* *I*** - Covers boot page */
+       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+
+       /* *I*G* - CCSRBAR */
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 1, BOOKE_PAGESZ_16M, 1),
+
+       /* *I*G* - Flash, localbus */
+       /* This will be changed to *I*G* after relocation to RAM. */
+       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+                     MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+                     0, 2, BOOKE_PAGESZ_256M, 1),
+
+       /* *I*G* - PCI */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 3, BOOKE_PAGESZ_1G, 1),
+
+       /* *I*G* - PCI */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+                     CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 4, BOOKE_PAGESZ_256M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+                     CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 5, BOOKE_PAGESZ_256M, 1),
+
+       /* *I*G* - PCI I/O */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 6, BOOKE_PAGESZ_256K, 1),
+
+       /* Bman/Qman */
+       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 9, BOOKE_PAGESZ_1M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+                     CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_1M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 11, BOOKE_PAGESZ_1M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+                     CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 12, BOOKE_PAGESZ_1M, 1),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+       SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
index b82f530f46a76164ff71d1c5bba538065cd4df2d..a70f541bd4b178199adf8f4cd00c8294aa38df9e 100644 (file)
@@ -343,6 +343,7 @@ MPC8540ADS  powerpc mpc85xx         mpc8540ads      freescale
 MPC8544DS      powerpc mpc85xx         mpc8544ds       freescale
 MPC8560ADS     powerpc mpc85xx         mpc8560ads      freescale
 MPC8568MDS     powerpc mpc85xx         mpc8568mds      freescale
+P4080DS                powerpc mpc85xx         corenet_ds      freescale
 XPEDITE5200    powerpc mpc85xx         xpedite5200     xes
 XPEDITE5370    powerpc mpc85xx         xpedite5370     xes
 P1022DS                powerpc mpc85xx         p1022ds         freescale
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
new file mode 100644 (file)
index 0000000..87703c9
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P4080 DS board configuration file
+ */
+#define CONFIG_P4080DS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P4080
+#define CONFIG_SYS_NUM_FMAN            2
+#define CONFIG_SYS_NUM_FM1_DTSEC       4
+#define CONFIG_SYS_NUM_FM2_DTSEC       4
+#define CONFIG_SYS_NUM_FM1_10GEC       1
+#define CONFIG_SYS_NUM_FM2_10GEC       1
+#define CONFIG_NUM_DDR_CONTROLLERS     2
+
+#define CONFIG_SYS_P4080_ERRATUM_CPU22
+#define CONFIG_SYS_P4080_ERRATUM_SERDES8
+
+#include "corenet_ds.h"
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
new file mode 100644 (file)
index 0000000..dd609da
--- /dev/null
@@ -0,0 +1,653 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/freescale/common/ics307_clk.h"
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500                    /* BOOKE e500 family */
+#define CONFIG_E500MC                  /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
+#define CONFIG_MPC85xx                 /* MPC85xx/PQ3 platform */
+#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
+#define CONFIG_MP                      /* support multiple processors */
+
+#define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC             CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
+#define CONFIG_PCI                     /* Enable PCI/PCIE */
+#define CONFIG_PCIE1                   /* PCIE controler 1 */
+#define CONFIG_PCIE2                   /* PCIE controler 2 */
+#define CONFIG_PCIE3                   /* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
+#define CONFIG_SYS_HAS_SERDES          /* has SERDES */
+
+#define CONFIG_SRIO1                   /* SRIO port 1 */
+#define CONFIG_SRIO2                   /* SRIO port 2 */
+
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#endif
+
+#define CONFIG_SYS_CLK_FREQ    get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_ICS307_REFCLK_HZ        33333000  /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
+#define CONFIG_BTB                     /* toggle branch predition */
+//#define      CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP                64      /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END         0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG      /* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000      /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR             0xfe000000      /* relocated CCSRBAR */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS                0xffe000000ull  /* physical addr of CCSRBAR */
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS        CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
+#endif
+#define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR             0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS                0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM      0
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+
+#ifdef CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS1    0x51
+#define SPD_EEPROM_ADDRESS2    0x52
+#else
+#define CONFIG_SYS_SDRAM_SIZE          4096
+
+#define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
+#define CONFIG_SYS_DDR_CS1_BNDS                0x0040007f
+#define CONFIG_SYS_DDR_CS0_CONFIG      0x80014202
+#define CONFIG_SYS_DDR_CS1_CONFIG      0x80014202
+#define CONFIG_SYS_DDR_TIMING_3                0x01031000
+#define CONFIG_SYS_DDR_TIMING_0                0x55440804
+#define CONFIG_SYS_DDR_TIMING_1                0x74713a66
+#define CONFIG_SYS_DDR_TIMING_2                0x0fb8911b
+#define CONFIG_SYS_DDR_MODE_1          0x00421850
+#define CONFIG_SYS_DDR_MODE_2          0x00100000
+#define CONFIG_SYS_DDR_MODE_CTRL       0x00000000
+#define CONFIG_SYS_DDR_INTERVAL                0x10400100
+#define CONFIG_SYS_DDR_DATA_INIT       0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL                0x03000000
+#define CONFIG_SYS_DDR_TIMING_4                0x00220001
+#define CONFIG_SYS_DDR_TIMING_5                0x03401500
+#define CONFIG_SYS_DDR_ZQ_CNTL         0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL      0x8655a608
+#define CONFIG_SYS_DDR_CONTROL         0xc7048000
+#define CONFIG_SYS_DDR_CONTROL2                0x24400011
+#define CONFIG_SYS_DDR_CDR1            0x00000000
+#define CONFIG_SYS_DDR_CDR2            0x00000000
+#define CONFIG_SYS_DDR_ERR_INT_EN      0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS         0x00000000
+#define CONFIG_SYS_DDR_SBE             0x00010000
+#define CONFIG_SYS_DDR_DEBUG_18                0x40100400
+
+#define CONFIG_SYS_DDR2_CS0_BNDS       0x008000bf
+#define CONFIG_SYS_DDR2_CS1_BNDS       0x00C000ff
+#define CONFIG_SYS_DDR2_CS0_CONFIG     CONFIG_SYS_DDR_CS0_CONFIG
+#define CONFIG_SYS_DDR2_CS1_CONFIG     CONFIG_SYS_DDR_CS1_CONFIG
+#define CONFIG_SYS_DDR2_TIMING_3       CONFIG_SYS_DDR_TIMING_3
+#define CONFIG_SYS_DDR2_TIMING_0       CONFIG_SYS_DDR_TIMING_0
+#define CONFIG_SYS_DDR2_TIMING_1       CONFIG_SYS_DDR_TIMING_1
+#define CONFIG_SYS_DDR2_TIMING_2       CONFIG_SYS_DDR_TIMING_2
+#define CONFIG_SYS_DDR2_MODE_1         CONFIG_SYS_DDR_MODE_1
+#define CONFIG_SYS_DDR2_MODE_2         CONFIG_SYS_DDR_MODE_2
+#define CONFIG_SYS_DDR2_MODE_CTRL      CONFIG_SYS_DDR_MODE_CTRL
+#define CONFIG_SYS_DDR2_INTERVAL       CONFIG_SYS_DDR_INTERVAL
+#define CONFIG_SYS_DDR2_DATA_INIT      CONFIG_SYS_DDR_DATA_INIT
+#define CONFIG_SYS_DDR2_CLK_CTRL       CONFIG_SYS_DDR_CLK_CTRL
+#define CONFIG_SYS_DDR2_TIMING_4       CONFIG_SYS_DDR_TIMING_4
+#define CONFIG_SYS_DDR2_TIMING_5       CONFIG_SYS_DDR_TIMING_5
+#define CONFIG_SYS_DDR2_ZQ_CNTL                CONFIG_SYS_DDR_ZQ_CNTL
+#define CONFIG_SYS_DDR2_WRLVL_CNTL     CONFIG_SYS_DDR_WRLVL_CNTL
+#define CONFIG_SYS_DDR2_CONTROL                CONFIG_SYS_DDR_CONTROL
+#define CONFIG_SYS_DDR2_CONTROL2       CONFIG_SYS_DDR_CONTROL2
+#define CONFIG_SYS_DDR2_CDR1           CONFIG_SYS_DDR_CDR1
+#define CONFIG_SYS_DDR2_CDR2           CONFIG_SYS_DDR_CDR2
+#define CONFIG_SYS_DDR2_ERR_INT_EN     CONFIG_SYS_DDR_ERR_INT_EN
+#define CONFIG_SYS_DDR2_ERR_DIS                CONFIG_SYS_DDR_ERR_DIS
+#define CONFIG_SYS_DDR2_SBE            CONFIG_SYS_DDR_SBE
+#define CONFIG_SYS_DDR2_DEBUG_18       CONFIG_SYS_DDR_DEBUG_18
+
+#endif
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of platform clock */
+#define CONFIG_SYS_LBC_LCRR            LCRR_CLKDIV_8
+
+#define CONFIG_SYS_FLASH_BASE          0xe0000000      /* Start of PromJet */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS     0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_BR0_PRELIM \
+       (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
+        BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+                                       | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+
+#define CONFIG_SYS_BR1_PRELIM \
+       (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  0xf8000ff7
+
+#define CONFIG_FSL_NGPIXIS             /* use common ngPIXIS code */
+#define PIXIS_BASE             0xffdf0000      /* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS                0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS                PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM  (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  0xffffeff7      /* 32KB but only 4k mapped */
+
+#define PIXIS_LBMAP_SWITCH     7
+#define PIXIS_LBMAP_MASK       0xf0
+#define PIXIS_LBMAP_SHIFT      4
+#define PIXIS_LBMAP_ALTBANK    0x40
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     2               /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      1024            /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000           /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500             /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE                TEXT_BASE       /* start of monitor */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR       0xfdd00000      /* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+       ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS  CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_END                0x00004000      /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE       128     /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (1024 * 1024)   /* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX      1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3        (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4        (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE     /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                /* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_SYS_I2C_OFFSET          0x118000
+#define CONFIG_SYS_I2C2_OFFSET         0x118100
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_RIO1_MEM_VIRT       0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO1_MEM_PHYS       0xc20000000ull
+#else
+#define CONFIG_SYS_RIO1_MEM_PHYS       0xa0000000
+#endif
+#define CONFIG_SYS_RIO1_MEM_SIZE       0x10000000      /* 256M */
+
+#define CONFIG_SYS_RIO2_MEM_VIRT       0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO2_MEM_PHYS       0xc30000000ull
+#else
+#define CONFIG_SYS_RIO2_MEM_PHYS       0xb0000000
+#endif
+#define CONFIG_SYS_RIO2_MEM_SIZE       0x10000000      /* 256M */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT      0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS    10
+#define CONFIG_SYS_BMAN_MEM_BASE       0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS       0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS       CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE       0x00200000
+#define CONFIG_SYS_QMAN_NUM_PORTALS    10
+#define CONFIG_SYS_QMAN_MEM_BASE       0xf4200000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS       0xff4200000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS       CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE       0x00200000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver */
+#define CONFIG_SYS_FMAN_FW_ADDR                0xEF000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FMAN_FW_ADDR_PHYS   0xFEF000000ULL
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR_PHYS   CONFIG_SYS_FMAN_FW_ADDR
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#endif
+
+#ifdef CONFIG_PCI
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE1_IO_VIRT
+
+/* video */
+#define CONFIG_VIDEO
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#ifndef CONFIG_PCI_PNP
+#define PCI_ENET0_IOADDR               CONFIG_SYS_PCI1_IO_BUS
+#define PCI_ENET0_MEMADDR              CONFIG_SYS_PCI1_IO_BUS
+#define PCI_IDSEL_NUMBER               0x11    /* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE     2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1               CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS         FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2               CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS         FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
+#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
+#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
+#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
+#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
+#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
+#endif
+
+#define CONFIG_SYS_TBIPA_VALUE 8
+#define CONFIG_MII             /* MII PHY management */
+#define CONFIG_ETHPRIME                "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO              /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE   /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                   /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ          1000            /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ   (16 << 20)      /* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM  0x02            /* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2       /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH                /opt/nfsroot
+#define CONFIG_BOOTFILE                uImage
+#define CONFIG_UBOOTPATH       u-boot.bin      /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR                1000000
+
+#define CONFIG_BOOTDELAY       10      /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE        115200
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                               \
+       "netdev=eth0\0"                                         \
+       "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                  \
+       "tftpflash=tftpboot $loadaddr $uboot; "                 \
+       "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
+       "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
+       "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
+       "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
+       "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
+       "consoledev=ttyS0\0"                                    \
+       "ramdiskaddr=2000000\0"                                 \
+       "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
+       "fdtaddr=c00000\0"                                      \
+       "fdtfile=p4080ds/p4080ds.dtb\0"                         \
+       "bdev=sda3\0"                                           \
+       "c=ffe\0"                                               \
+       "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0"
+
+#define CONFIG_HDBOOT                                  \
+       "setenv bootargs root=/dev/$bdev rw "           \
+       "console=$consoledev,$baudrate $othbootargs;"   \
+       "tftp $loadaddr $bootfile;"                     \
+       "tftp $fdtaddr $fdtfile;"                       \
+       "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND                  \
+       "setenv bootargs root=/dev/nfs rw "     \
+       "nfsroot=$serverip:$rootpath "          \
+       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+       "console=$consoledev,$baudrate $othbootargs;"   \
+       "tftp $loadaddr $bootfile;"             \
+       "tftp $fdtaddr $fdtfile;"               \
+       "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND                          \
+       "setenv bootargs root=/dev/ram rw "             \
+       "console=$consoledev,$baudrate $othbootargs;"   \
+       "tftp $ramdiskaddr $ramdiskfile;"               \
+       "tftp $loadaddr $bootfile;"                     \
+       "tftp $fdtaddr $fdtfile;"                       \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND             CONFIG_HDBOOT
+
+#endif /* __CONFIG_H */