mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR

Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.

Signed-off-by: Timur Tabi <timur@freescale.com>

diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
index ed7b71d0861fcd60b9467c1fcc468c4b02cd2bb4..873bdd01cd66527494f9112d222dbeeea436a8b9 100644 (file)
--- a/board/mpc8349emds/mpc8349emds.c
+++ b/board/mpc8349emds/mpc8349emds.c
@@ -63,7 +63,7 @@ int board_early_init_f (void)
 
 long int initdram (int board_type)
 {
-       volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *im = (immap_t *)CFG_IMMR;
        u32 msize = 0;
 
        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
@@ -100,7 +100,7 @@ long int initdram (int board_type)
  ************************************************************************/
 int fixed_sdram(void)
 {
-       volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *im = (immap_t *)CFG_IMMR;
        u32 msize = 0;
        u32 ddr_size;
        u32 ddr_size_log2;
@@ -171,7 +171,7 @@ int checkboard (void)
 
 void sdram_init(void)
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
        volatile lbus83xx_t *lbc= &immap->lbus;
        uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 
@@ -249,7 +249,7 @@ void sdram_init(void)
  */
 void ecc_print_status(void)
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
        volatile ddr83xx_t *ddr = &immap->ddr;
 
        printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
@@ -324,7 +324,7 @@ void ecc_print_status(void)
 
 int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
        volatile ddr83xx_t *ddr = &immap->ddr;
        volatile u32 val;
        u64 *addr, count, val64;

diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c
index 908be5754614d0d3e8ce3d8f390288c89e0e6688..da49a5d80dd26925db7aeee92dae41145894150e 100644 (file)
--- a/board/mpc8349emds/pci.c
+++ b/board/mpc8349emds/pci.c
@@ -146,7 +146,7 @@ pci_init_board(void)
        u32 dev;
        struct  pci_controller * hose;
 
-       immr = (immap_t *)CFG_IMMRBAR;
+       immr = (immap_t *)CFG_IMMR;
        clk = (clk83xx_t *)&immr->clk;
        pci_law = immr->sysconf.pcilaw;
        pci_pot = immr->ios.pot;
@@ -260,8 +260,8 @@ pci_init_board(void)
        hose->region_count = 4;
 
        pci_setup_indirect(hose,
-                          (CFG_IMMRBAR+0x8300),
-                          (CFG_IMMRBAR+0x8304));
+                          (CFG_IMMR+0x8300),
+                          (CFG_IMMR+0x8304));
 
        pci_register_hose(hose);
 
@@ -356,8 +356,8 @@ pci_init_board(void)
        hose->region_count = 4;
 
        pci_setup_indirect(hose,
-                          (CFG_IMMRBAR+0x8380),
-                          (CFG_IMMRBAR+0x8384));
+                          (CFG_IMMR+0x8380),
+                          (CFG_IMMR+0x8384));
 
        pci_register_hose(hose);
 

diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c
index 9fce973df0c9840c02b8340cd7c0a90391a3c5d1..c0e72c93e1272444657c626704c03abb2d182439 100644 (file)
--- a/board/mpc8349itx/mpc8349itx.c
+++ b/board/mpc8349itx/mpc8349itx.c
@@ -47,7 +47,7 @@
  ************************************************************************/
 int fixed_sdram(void)
 {
-       volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *im = (immap_t *) CFG_IMMR;
        u32 ddr_size;           /* The size of RAM, in bytes */
        u32 ddr_size_log2 = 0;
 
@@ -139,7 +139,7 @@ volatile static struct pci_controller hose[] = {
 
 void sdram_init(void)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile lbus83xx_t *lbc = &immap->lbus;
 
 #if defined(CFG_BR2_PRELIM) \
@@ -219,7 +219,7 @@ void sdram_init(void)
 
 long int initdram(int board_type)
 {
-       volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *im = (immap_t *) CFG_IMMR;
        u32 msize = 0;
 #ifdef CONFIG_DDR_ECC
        volatile ddr83xx_t *ddr = &im->ddr;
@@ -328,7 +328,7 @@ int misc_init_f(void)
                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
        };
-       volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile lbus83xx_t *lbus = &immap->lbus;
 
        lbus->bank[3].br = CFG_BR3_PRELIM;

diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c
index b4637bc8cdfd165c53510a4914502ab5aa2f458c..535cc34afc649d8663ac1a2273ff7f3903d04ae9 100644 (file)
--- a/board/mpc8349itx/pci.c
+++ b/board/mpc8349itx/pci.c
@@ -88,7 +88,7 @@ void pci_init_board(void)
        u32 dev;
        struct pci_controller *hose;
 
-       immr = (immap_t *) CFG_IMMRBAR;
+       immr = (immap_t *) CFG_IMMR;
        clk = (clk83xx_t *) & immr->clk;
        pci_law = immr->sysconf.pcilaw;
        pci_pot = immr->ios.pot;
@@ -211,7 +211,7 @@ void pci_init_board(void)
        hose->region_count = 4;
 
        pci_setup_indirect(hose,
-                          (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304));
+                          (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
 
        pci_register_hose(hose);
 
@@ -302,7 +302,7 @@ void pci_init_board(void)
        hose->region_count = 4;
 
        pci_setup_indirect(hose,
-                          (CFG_IMMRBAR + 0x8380), (CFG_IMMRBAR + 0x8384));
+                          (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));
 
        pci_register_hose(hose);
 

diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c
index a9b1d9eb32cc81dba621a770604bfd0494803787..ddc1047c6188d1109bf0a02d1fad8f20ca9c4b12 100644 (file)
--- a/board/mpc8360emds/mpc8360emds.c
+++ b/board/mpc8360emds/mpc8360emds.c
@@ -106,7 +106,7 @@ void sdram_init(void);
 
 long int initdram(int board_type)
 {
-       volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *im = (immap_t *) CFG_IMMR;
        u32 msize = 0;
 
        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
@@ -141,7 +141,7 @@ long int initdram(int board_type)
  ************************************************************************/
 int fixed_sdram(void)
 {
-       volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *im = (immap_t *) CFG_IMMR;
        u32 msize = 0;
        u32 ddr_size;
        u32 ddr_size_log2;
@@ -196,7 +196,7 @@ int checkboard(void)
 
 void sdram_init(void)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile lbus83xx_t *lbc = &immap->lbus;
        uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
 
@@ -267,7 +267,7 @@ void sdram_init(void)
  */
 void ecc_print_status(void)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile ddr83xx_t *ddr = &immap->ddr;
 
        printf("\nECC mode: %s\n\n",
@@ -347,7 +347,7 @@ void ecc_print_status(void)
 
 int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile ddr83xx_t *ddr = &immap->ddr;
        volatile u32 val;
        u64 *addr;

diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c
index c81e7a64edac58e1b9fd0a6649c1b31955f2b505..a013ba3d430ee85fadb11d66f7e2309a8eec34c2 100644 (file)
--- a/board/mpc8360emds/pci.c
+++ b/board/mpc8360emds/pci.c
@@ -63,7 +63,7 @@ void pci_init_board(void)
        volatile pcictrl83xx_t *pci_ctrl;
        volatile pciconf83xx_t *pci_conf;
 
-       immr = (immap_t *) CFG_IMMRBAR;
+       immr = (immap_t *) CFG_IMMR;
        pci_law = immr->sysconf.pcilaw;
        pci_pot = immr->ios.pot;
        pci_ctrl = immr->pci_ctrl;
@@ -89,7 +89,7 @@ void pci_init_board(void)
        hose[0].first_busno = 0;
        hose[0].last_busno = 0xff;
        pci_setup_indirect(&hose[0],
-                          (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304));
+                          (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
        reg16 = 0xff;
 
        pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
@@ -131,7 +131,7 @@ void pci_init_board(void)
        u32 val32;
        u32 dev;
 
-       immr = (immap_t *) CFG_IMMRBAR;
+       immr = (immap_t *) CFG_IMMR;
        clk = (clk83xx_t *) & immr->clk;
        pci_law = immr->sysconf.pcilaw;
        pci_pot = immr->ios.pot;
@@ -274,7 +274,7 @@ void pci_init_board(void)
        hose[0].region_count = 4;
 
        pci_setup_indirect(&hose[0],
-                          (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304));
+                          (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
 
        pci_register_hose(hose);
 

diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c
index d01277f808dc7db3b8641cff11b0955a3dbb0f09..d896f17aad05f4fe388a22b43c936cffb34457d9 100644 (file)
--- a/board/tqm834x/pci.c
+++ b/board/tqm834x/pci.c
@@ -78,7 +78,7 @@ pci_init_board(void)
        u32 reg32;
        struct  pci_controller * hose;
 
-       immr = (immap_t *)CFG_IMMRBAR;
+       immr = (immap_t *)CFG_IMMR;
        clk = (clk83xx_t *)&immr->clk;
        pci_law = immr->sysconf.pcilaw;
        pci_pot = immr->ios.pot;
@@ -186,8 +186,8 @@ pci_init_board(void)
        hose->region_count = 3;
 
        pci_setup_indirect(hose,
-                          (CFG_IMMRBAR+0x8300),
-                          (CFG_IMMRBAR+0x8304));
+                          (CFG_IMMR+0x8300),
+                          (CFG_IMMR+0x8304));
 
        pci_register_hose(hose);
 

diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index 41b34cc6fa461616fcac9d0c02224b43505fcbd2..36d901f094255bec9910916e3972192f7e388fbf 100644 (file)
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -69,7 +69,7 @@ static void set_cs_config(short cs, long config);
 static void set_ddr_config(void);
 
 /* Local variable */
-static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+static volatile immap_t *im = (immap_t *)CFG_IMMR;
 
 /**************************************************************************
  * Board initialzation after relocation to RAM. Used to detect the number
@@ -147,7 +147,7 @@ int checkboard (void)
        volatile immap_t * immr;
        u32 w, f;
 
-       immr = (immap_t *)CFG_IMMRBAR;
+       immr = (immap_t *)CFG_IMMR;
        if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
                printf("PCI:   NOT in host mode..?!\n");
                return 0;

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 3d8ca772c613933327b7ce0ae28267ba02e5e947..0bd05330de40015f04339ec36b885b8bcb40b581 100644 (file)
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -49,7 +49,7 @@ int checkcpu(void)
        u32 spridr;
        char buf[32];
 
-       immr = (immap_t *)CFG_IMMRBAR;
+       immr = (immap_t *)CFG_IMMR;
 
        if ((pvr & 0xFFFF0000) != PVR_83xx) {
                puts("Not MPC83xx Family!!!\n");
@@ -141,7 +141,7 @@ int checkcpu(void)
 void upmconfig (uint upm, uint *table, uint size)
 {
 #if defined(CONFIG_MPC834X)
-       volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile lbus83xx_t *lbus = &immap->lbus;
        volatile uchar *dummy = NULL;
        const u32 msel = (upm + 4) << BR_MSEL_SHIFT;    /* What the MSEL field in BRn should be */
@@ -188,7 +188,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
        ulong addr;
 #endif
 
-       volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
 #ifdef MPC83xx_RESET
        /* Interrupts and MMU off */
@@ -259,7 +259,7 @@ void watchdog_reset (void)
        int re_enable = disable_interrupts();
 
        /* Reset the 83xx watchdog */
-       volatile immap_t *immr = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *immr = (immap_t *) CFG_IMMR;
        immr->wdt.swsrr = 0x556c;
        immr->wdt.swsrr = 0xaa39;
 
@@ -311,7 +311,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
 #if defined(CONFIG_DDR_ECC)
 void dma_init(void)
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
        volatile dma83xx_t *dma = &immap->dma;
        volatile u32 status = swab32(dma->dmasr0);
        volatile u32 dmamr0 = swab32(dma->dmamr0);
@@ -342,7 +342,7 @@ void dma_init(void)
 
 uint dma_check(void)
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
        volatile dma83xx_t *dma = &immap->dma;
        volatile u32 status = swab32(dma->dmasr0);
        volatile u32 byte_count = swab32(dma->dmabcr0);
@@ -361,7 +361,7 @@ uint dma_check(void)
 
 int dma_xfer(void *dest, u32 count, void *src)
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
        volatile dma83xx_t *dma = &immap->dma;
        volatile u32 dmamr0;
 

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index eb8f8c042f113772c2e0c834984d14e26b929830..4f80f4a0944c6d3d60ff83dcba843739305c7796 100644 (file)
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -219,7 +219,7 @@ void cpu_init_f (volatile immap_t * im)
 int cpu_init_r (void)
 {
 #ifdef CONFIG_QE
-       uint qe_base = CFG_IMMRBAR + 0x00100000; /* QE immr base */
+       uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */
        qe_init(qe_base);
        qe_reset();
 #endif

diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c
index 5a0babfcbb994348087feffad744ceff0dd1a0cd..98fccff227524b80aa5c36117fab5cb304222ecf 100644 (file)
--- a/cpu/mpc83xx/interrupts.c
+++ b/cpu/mpc83xx/interrupts.c
@@ -45,7 +45,7 @@ struct irq_action {
 
 int interrupt_init_cpu (unsigned *decrementer_count)
 {
-       volatile immap_t *immr = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
        *decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
 

diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c
index 11cf3722bd04f06507148898c9f89d0dfa86a07e..ebe348711200e70be58b91b1d7a5a2fefc89037f 100644 (file)
--- a/cpu/mpc83xx/qe_io.c
+++ b/cpu/mpc83xx/qe_io.c
@@ -34,7 +34,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
        u32                     pin_2bit_assign;
        u32                     pin_1bit_mask;
        u32                     tmp_val;
-       volatile immap_t        *im = (volatile immap_t *)CFG_IMMRBAR;
+       volatile immap_t        *im = (volatile immap_t *)CFG_IMMR;
        volatile gpio83xx_t     *par_io =(volatile gpio83xx_t *)&im->gpio;
 
        /* Caculate pin location and 2bit mask and dir */

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index b91c6130e7847f4c9b50b893b6c37a6167cc126e..dc8f6790a6e357e39998cd98620e69613ced27d7 100644 (file)
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -112,7 +112,7 @@ static void spd_debug(spd_eeprom_t *spd)
 
 long int spd_sdram()
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
        volatile ddr83xx_t *ddr = &immap->ddr;
        volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
        spd_eeprom_t spd;
@@ -562,7 +562,7 @@ static __inline__ unsigned long get_tbms (void)
 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
 void ddr_enable_ecc(unsigned int dram_size)
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
        volatile ddr83xx_t *ddr= &immap->ddr;
        unsigned long t_start, t_end;
        register u64 *p;

diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 1e082a78685bf4ae605476ea2e6b170ee55c1d60..213e7180a7df619a247e01b2c1283ed17052fb48 100644 (file)
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -94,7 +94,7 @@ corecnf_t corecnf_tab[] = {
  */
 int get_clocks(void)
 {
-       volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
+       volatile immap_t *im = (immap_t *) CFG_IMMR;
        u32 pci_sync_in;
        u8 spmf;
        u8 clkin_div;

diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index c43835c8dcdadbe207ddca384c8c717556e436dd..0f27bb61f8cec196394b61ac00208dbff119b7e2 100644 (file)
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -104,9 +104,9 @@ version_string:
 #ifndef CONFIG_DEFAULT_IMMR
 #error CONFIG_DEFAULT_IMMR must be defined
 #endif /* CFG_DEFAULT_IMMR */
-#ifndef CFG_IMMRBAR
-#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR
-#endif /* CFG_IMMRBAR */
+#ifndef CFG_IMMR
+#define CFG_IMMR CONFIG_DEFAULT_IMMR
+#endif /* CFG_IMMR */
 
 /*
  * After configuration, a system reset exception is executed using the
@@ -152,8 +152,8 @@ boot_cold: /* time t 3 */
        nop
 boot_warm: /* time t 5 */
        mfmsr   r5                      /* save msr contents    */
-       lis     r3, CFG_IMMRBAR@h
-       ori     r3, r3, CFG_IMMRBAR@l
+       lis     r3, CFG_IMMR@h
+       ori     r3, r3, CFG_IMMR@l
        stw     r3, IMMRBAR(r4)
 
        /* Initialise the E300 processor core           */
@@ -226,7 +226,7 @@ in_flash:
        GET_GOT                 /* initialize GOT access        */
 
        /* r3: IMMR */
-       lis     r3, CFG_IMMRBAR@h
+       lis     r3, CFG_IMMR@h
        /* run low-level CPU init code (in Flash)*/
        bl      cpu_init_f
 
@@ -446,7 +446,7 @@ init_e300_core: /* time t 10 */
        mtspr   SRR1, r3                        /* Make SRR1 match MSR */
 
 
-       lis     r3, CFG_IMMRBAR@h
+       lis     r3, CFG_IMMR@h
 #if defined(CONFIG_WATCHDOG)
        /* Initialise the Wathcdog values and reset it (if req) */
        /*------------------------------------------------------*/
@@ -1201,7 +1201,7 @@ map_flash_by_law1:
        /* When booting from ROM (Flash or EPROM), clear the  */
        /* Address Mask in OR0 so ROM appears everywhere      */
        /*----------------------------------------------------*/
-       lis     r3, (CFG_IMMRBAR)@h  /* r3 <= CFG_IMMRBAR    */
+       lis     r3, (CFG_IMMR)@h  /* r3 <= CFG_IMMR    */
        lwz     r4, OR0@l(r3)
        li      r5, 0x7fff        /* r5 <= 0x00007FFFF */
        and     r4, r4, r5

diff --git a/drivers/tsec.h b/drivers/tsec.h
index 4aa331c458b99b4985b191b2cc467de9fa95c35c..cee30037db03dee0fb30b4c4f36605ecf55ac1d5 100644 (file)
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -30,7 +30,7 @@
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
     #define TSEC_BASE_ADDR     (CFG_IMMR + CFG_TSEC1_OFFSET)
 #elif defined(CONFIG_MPC83XX)
-    #define TSEC_BASE_ADDR     (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+    #define TSEC_BASE_ADDR     (CFG_IMMR + CFG_TSEC1_OFFSET)
 #endif
 
 

diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h
index 8afdda2ce22776a239b71ebc58e9cbf0a0700f3c..37847666db1a600a08a065320e9c9ec494adaa91 100644 (file)
--- a/include/asm-ppc/i2c.h
+++ b/include/asm-ppc/i2c.h
@@ -79,19 +79,19 @@ typedef struct i2c
 #endif
 #define I2C_TIMEOUT (CFG_HZ/4)
 
-#ifndef CFG_IMMRBAR
-#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h
+#ifndef CFG_IMMR
+#error CFG_IMMR is not defined in /include/configs/${BOARD}.h
 #endif
 
 #ifndef CFG_I2C_OFFSET
 #error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
 #endif
 
-#define I2C_1 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET))
+#define I2C_1 ((i2c_t*)(CFG_IMMR + CFG_I2C_OFFSET))
 
 /* Optional support for second I2C bus */
 #ifdef CFG_I2C2_OFFSET
-#define I2C_2 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET))
+#define I2C_2 ((i2c_t*)(CFG_IMMR + CFG_I2C2_OFFSET))
 #endif /* CFG_I2C2_OFFSET */
 
 #define I2C_READ  1

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index e68c41accf5c5dd5ab0668dda1484bf7a4f28ef5..4a5b4bc4a7ccfd8c0e9e91bd279c8d7d454cced7 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -73,7 +73,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F              /* call board_pre_init */
 
-#define CFG_IMMRBAR            0xE0000000
+#define CFG_IMMR               0xE0000000
 
 #undef CFG_DRAM_TEST                           /* memory test, takes time */
 #define CFG_MEMTEST_START      0x00000000      /* memtest region */
@@ -311,8 +311,8 @@
 #define CFG_BAUDRATE_TABLE  \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_IMMRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_IMMRBAR+0x4600)
+#define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
@@ -345,9 +345,9 @@
 
 /* TSEC */
 #define CFG_TSEC1_OFFSET 0x24000
-#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
 #define CFG_TSEC2_OFFSET 0x25000
-#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
 
 /* USB */
 #define CFG_USE_MPC834XSYS_USB_PHY     1 /* Use SYS board PHY */
@@ -641,8 +641,8 @@
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CFG_IBAT5L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U     (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L     (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U     (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CFG_IBAT6L     (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index aaf4d101dce96921938e52fac7b1d395723bc62c..c74e63a4d4d6645fe2c9ad69f0921363aee4af4e 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -128,7 +128,7 @@
 #endif
 #endif
 
-#define CFG_IMMRBAR            0xE0000000      /* The IMMR is relocated to here */
+#define CFG_IMMR               0xE0000000      /* The IMMR is relocated to here */
 
 #undef CFG_DRAM_TEST                                   /* memory test, takes time */
 #define CFG_MEMTEST_START       0x00003000      /* memtest region */
@@ -374,8 +374,8 @@
 #define CFG_BAUDRATE_TABLE  \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1       (CFG_IMMRBAR + 0x4500)
-#define CFG_NS16550_COM2       (CFG_IMMRBAR + 0x4600)
+#define CFG_NS16550_COM1       (CFG_IMMR + 0x4500)
+#define CFG_NS16550_COM2       (CFG_IMMR + 0x4600)
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
@@ -653,8 +653,8 @@
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CFG_IBAT5L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U     (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L     (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U     (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CFG_IBAT6L     (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)

diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index feb9cf22f2dc0b8e5a4867c613c6a27e982d95a2..a8f2df911e6c9e20096f6c98fce60b5ce3ce450b 100644 (file)
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -92,7 +92,7 @@
 /*
  * IMMR new address
  */
-#define CFG_IMMRBAR            0xE0000000
+#define CFG_IMMR               0xE0000000
 
 /*
  * DDR Setup
@@ -306,8 +306,8 @@
 #define CFG_BAUDRATE_TABLE  \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1       (CFG_IMMRBAR+0x4500)
-#define CFG_NS16550_COM2       (CFG_IMMRBAR+0x4600)
+#define CFG_NS16550_COM1       (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2       (CFG_IMMR+0x4600)
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
@@ -515,9 +515,9 @@
 #define CFG_DBAT0U     CFG_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CFG_IBAT1L     (CFG_IMMRBAR | BATL_PP_10 | \
+#define CFG_IBAT1L     (CFG_IMMR | BATL_PP_10 | \
                        BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT1U     (CFG_IMMRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT1U     (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 #define CFG_DBAT1L     CFG_IBAT1L
 #define CFG_DBAT1U     CFG_IBAT1U
 

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 727094b203f176cfb0e482d240c2491b91a858de..b0b0673cff033d07e679d5189a64d7c5313203dc 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -41,7 +41,7 @@
 #define CONFIG_TQM834X         1       /* TQM834X board specific */
 
 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */
-#define CFG_IMMRBAR            0xff400000
+#define CFG_IMMR               0xff400000
 
 /* System clock. Primary input clock when in PCI host mode */
 #define CONFIG_83XX_CLKIN      66666000        /* 66,666 MHz */
@@ -210,8 +210,8 @@ extern int tqm834x_num_flash_banks;
 #define CFG_BAUDRATE_TABLE  \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1       (CFG_IMMRBAR + 0x4500)
-#define CFG_NS16550_COM2       (CFG_IMMRBAR + 0x4600)
+#define CFG_NS16550_COM1       (CFG_IMMR + 0x4500)
+#define CFG_NS16550_COM2       (CFG_IMMR + 0x4600)
 
 /*
  * I2C
@@ -248,9 +248,9 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_MII
 
 #define CFG_TSEC1_OFFSET       0x24000
-#define CFG_TSEC1              (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#define CFG_TSEC1              (CFG_IMMR + CFG_TSEC1_OFFSET)
 #define CFG_TSEC2_OFFSET       0x25000
-#define CFG_TSEC2              (CFG_IMMRBAR + CFG_TSEC2_OFFSET)
+#define CFG_TSEC2              (CFG_IMMR + CFG_TSEC2_OFFSET)
 
 #if defined(CONFIG_TSEC_ENET)
 
@@ -473,8 +473,8 @@ extern int tqm834x_num_flash_banks;
 #endif
 
 /* IMMRBAR */
-#define CFG_IBAT6L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT6U     (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L     (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U     (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
 
 /* FLASH */
 #define CFG_IBAT7L     (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)

diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 844bbc900339d046ae45d0ccbad8e5be45de4637..1866dc5cf05af5a5d2f45757ff1577320677aaa9 100644 (file)
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -511,7 +511,7 @@ void board_init_f (ulong bootflag)
        bd->bi_mbar_base = CFG_MBAR;    /* base of internal registers */
 #endif
 #if defined(CONFIG_MPC83XX)
-       bd->bi_immrbar = CFG_IMMRBAR;
+       bd->bi_immrbar = CFG_IMMR;
 #endif
 #if defined(CONFIG_MPC8220)
        bd->bi_mbar_base = CFG_MBAR;    /* base of internal registers */