LIBS += drivers/spi/libspi.o
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/libqe.o
+LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
endif
ifeq ($(CPU),mpc85xx)
COBJS-y += cpu_init.o
COBJS-y += speed.o
COBJS-y += interrupts.o
-COBJS-y += spd_sdram.o
COBJS-y += ecc.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_FSL_SERDES) += serdes.o
COBJS-$(CONFIG_PCIE) += pcie.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+ifdef CONFIG_FSL_DDR2
+COBJS-$(CONFIG_MPC8349) += ddr-gen2.o
+else
+COBJS-y += spd_sdram.o
+endif
+COBJS-$(CONFIG_FSL_DDR2) += law.o
+
COBJS := $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(obj)ddr-gen1.c:
+ @rm -f $(obj)ddr-gen1.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
+
+$(obj)ddr-gen2.c:
+ @rm -f $(obj)ddr-gen2.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
+
+$(obj)ddr-gen3.c:
+ @rm -f $(obj)ddr-gen3.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c
+
#########################################################################
# defines $(obj).depend target
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on the contribution of Marian Balakowicz <m8@semihalf.com>
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
void ecc_print_status(void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ddr83xx_t *ddr = &immap->ddr;
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_FSL_DDR2
+ ccsr_ddr_t *ddr = &immap->ddr;
+#else
+ ddr83xx_t *ddr = &immap->ddr;
+#endif
printf("\nECC mode: %s\n\n",
(ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ddr83xx_t *ddr = &immap->ddr;
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_FSL_DDR2
+ ccsr_ddr_t *ddr = &immap->ddr;
+#else
+ ddr83xx_t *ddr = &immap->ddr;
+#endif
volatile u32 val;
u64 *addr;
u32 count;
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
+{
+ immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
+ u64 start_align, law_sz;
+ int law_sz_enc;
+
+ if (start == 0)
+ start_align = 1ull << (LAW_SIZE_2G + 1);
+ else
+ start_align = 1ull << (ffs64(start) - 1);
+ law_sz = min(start_align, sz);
+ law_sz_enc = __ilog2_u64(law_sz) - 1;
+
+ /*
+ * Set up LAWBAR for all of DDR.
+ */
+ ecm->bar = start & 0xfffff000;
+ ecm->ar = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc));
+ debug("DDR:bar=0x%08x\n", ecm->bar);
+ debug("DDR:ar=0x%08x\n", ecm->ar);
+
+ /* recalculate size based on what was actually covered by the law */
+ law_sz = 1ull << __ilog2_u64(law_sz);
+
+ /* do we still have anything to map */
+ sz = sz - law_sz;
+ if (sz) {
+ start += law_sz;
+
+ start_align = 1ull << (ffs64(start) - 1);
+ law_sz = min(start_align, sz);
+ law_sz_enc = __ilog2_u64(law_sz) - 1;
+ ecm = &immap->sysconf.ddrlaw[1];
+ ecm->bar = start & 0xfffff000;
+ ecm->ar = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc));
+ debug("DDR:bar=0x%08x\n", ecm->bar);
+ debug("DDR:ar=0x%08x\n", ecm->ar);
+ } else {
+ return 0;
+ }
+
+ /* do we still have anything to map */
+ sz = sz - law_sz;
+ if (sz)
+ return 1;
+
+ return 0;
+}
return gd->csb_clk;
}
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq(ulong dummy)
+{
+ return gd->mem_clk;
+}
+
int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
char buf[32];
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
unsigned int ctrl_num)
{
unsigned int i;
- volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#ifdef CONFIG_MPC83xx
+ ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
+#else
+ ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#endif
if (ctrl_num) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
#include "ddr.h"
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC83xx
+ #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
+#elif defined(CONFIG_MPC85xx)
#define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
#elif defined(CONFIG_MPC86xx)
#define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
void board_add_ram_info(int use_default)
{
-#if defined(CONFIG_MPC85xx)
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#if defined(CONFIG_MPC83xx)
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ ccsr_ddr_t *ddr = (void *)&immap->ddr;
+#elif defined(CONFIG_MPC85xx)
+ ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
#elif defined(CONFIG_MPC86xx)
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
+ ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
uint32_t cs0_config = in_be32(&ddr->cs0_config);
#define CONFIG_SYS_BOOT_GET_KBD
#ifndef CONFIG_MAX_MEM_MAPPED
-#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || \
+ defined(CONFIG_E500) || \
+ defined(CONFIG_MPC86xx) || \
+ defined(CONFIG_E300)
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#else
#define CONFIG_MAX_MEM_MAPPED (256 << 20)
/*
- * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004-2011 Freescale Semiconductor, Inc.
*
* MPC83xx Internal Memory Map
*
/*
* DDR Memory Controller Memory Map
*/
+#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
+typedef struct ccsr_ddr {
+ u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
+ u8 res1[4];
+ u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
+ u8 res2[4];
+ u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
+ u8 res3[4];
+ u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
+ u8 res4[100];
+ u32 cs0_config; /* Chip Select Configuration */
+ u32 cs1_config; /* Chip Select Configuration */
+ u32 cs2_config; /* Chip Select Configuration */
+ u32 cs3_config; /* Chip Select Configuration */
+ u8 res4a[48];
+ u32 cs0_config_2; /* Chip Select Configuration 2 */
+ u32 cs1_config_2; /* Chip Select Configuration 2 */
+ u32 cs2_config_2; /* Chip Select Configuration 2 */
+ u32 cs3_config_2; /* Chip Select Configuration 2 */
+ u8 res5[48];
+ u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
+ u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
+ u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
+ u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
+ u32 sdram_cfg; /* SDRAM Control Configuration */
+ u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
+ u32 sdram_mode; /* SDRAM Mode Configuration */
+ u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
+ u32 sdram_md_cntl; /* SDRAM Mode Control */
+ u32 sdram_interval; /* SDRAM Interval Configuration */
+ u32 sdram_data_init; /* SDRAM Data initialization */
+ u8 res6[4];
+ u32 sdram_clk_cntl; /* SDRAM Clock Control */
+ u8 res7[20];
+ u32 init_addr; /* training init addr */
+ u32 init_ext_addr; /* training init extended addr */
+ u8 res8_1[16];
+ u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
+ u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
+ u8 reg8_1a[8];
+ u32 ddr_zq_cntl; /* ZQ calibration control*/
+ u32 ddr_wrlvl_cntl; /* write leveling control*/
+ u8 reg8_1aa[4];
+ u32 ddr_sr_cntr; /* self refresh counter */
+ u32 ddr_sdram_rcw_1; /* Control Words 1 */
+ u32 ddr_sdram_rcw_2; /* Control Words 2 */
+ u8 reg_1ab[8];
+ u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
+ u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
+ u8 res8_1b[104];
+ u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
+ u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
+ u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
+ u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
+ u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
+ u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
+ u8 res8_1ba[0x908];
+ u32 ddr_dsr1; /* Debug Status 1 */
+ u32 ddr_dsr2; /* Debug Status 2 */
+ u32 ddr_cdr1; /* Control Driver 1 */
+ u32 ddr_cdr2; /* Control Driver 2 */
+ u8 res8_1c[200];
+ u32 ip_rev1; /* IP Block Revision 1 */
+ u32 ip_rev2; /* IP Block Revision 2 */
+ u32 eor; /* Enhanced Optimization Register */
+ u8 res8_2[252];
+ u32 mtcr; /* Memory Test Control Register */
+ u8 res8_3[28];
+ u32 mtp1; /* Memory Test Pattern 1 */
+ u32 mtp2; /* Memory Test Pattern 2 */
+ u32 mtp3; /* Memory Test Pattern 3 */
+ u32 mtp4; /* Memory Test Pattern 4 */
+ u32 mtp5; /* Memory Test Pattern 5 */
+ u32 mtp6; /* Memory Test Pattern 6 */
+ u32 mtp7; /* Memory Test Pattern 7 */
+ u32 mtp8; /* Memory Test Pattern 8 */
+ u32 mtp9; /* Memory Test Pattern 9 */
+ u32 mtp10; /* Memory Test Pattern 10 */
+ u8 res8_4[184];
+ u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
+ u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
+ u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
+ u8 res9[20];
+ u32 capture_data_hi; /* Data Path Read Capture High */
+ u32 capture_data_lo; /* Data Path Read Capture Low */
+ u32 capture_ecc; /* Data Path Read Capture ECC */
+ u8 res10[20];
+ u32 err_detect; /* Error Detect */
+ u32 err_disable; /* Error Disable */
+ u32 err_int_en;
+ u32 capture_attributes; /* Error Attrs Capture */
+ u32 capture_address; /* Error Addr Capture */
+ u32 capture_ext_address; /* Error Extended Addr Capture */
+ u32 err_sbe; /* Single-Bit ECC Error Management */
+ u8 res11[164];
+ u32 debug[32]; /* debug_1 to debug_32 */
+ u8 res12[128];
+} ccsr_ddr_t;
+#else
typedef struct ddr_cs_bnds {
u32 csbnds;
u8 res0[4];
u32 debug_reg;
u8 res9[0xFC];
} ddr83xx_t;
+#endif
/*
* DUART
u8 dll_ddr[0x100];
u8 dll_lbc[0x100];
u8 res1[0xE00];
- ddr83xx_t ddr; /* DDR Memory Controller Memory */
+#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
+ ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
+#else
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+#endif
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res2[0x1300];
duart83xx_t duart[2]; /* DUART */
} immap_t;
#endif
+#define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000)
+#define CONFIG_SYS_MPC83xx_DDR_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DDR_OFFSET)
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
-#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC83xx_DMA_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
-#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
# others
-COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+COBJS-$(SPD) += ddr_spd.o
COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
COBJS-y += flash.o
ulong get_bus_freq (ulong);
int get_serial_clock(void);
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
+ulong get_ddr_freq(ulong);
+#endif
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
-ulong get_ddr_freq (ulong);
#endif
#if defined(CONFIG_MPC86xx)
typedef MPC86xx_SYS_INFO sys_info_t;
projects / u-boot / commitdiff