Revert "i.MX28: Enable additional DRAM address bits"

This reverts commit 69d26d09de1cb93e0a09ca71d9f0d41a66f0756a.

Apparently, this commit got mainline only because of out-of-tree
port and causes breakage on board that is mainline. Revert.

Reason:
* The OOT board has 512MB of DRAM, enabling this additional address
  line enabled it to work fine with 512MB of RAM.
* Every mainline port has max. 256MB of DRAM, therefore this revert
  has no impact on any mainline port
* Though this caused a problem with new M28 board with 256MB of DRAM
  where the chips are wired differently. The patch-to-be-reverted
  caused the DRAM to behave like this:

  [128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again]

Therefore to retain the current one-memory-init-rules-them-all situation,
revert this patch until another board emerges and will actually be pushed
mainline that needs different setup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>

diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index 911bbefc060f482d79c29b1b2c21b9bdbc0a6dc5..0f825ed2d210283cabd8cbe8ea0e1df5a2889e50 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -39,7 +39,7 @@ uint32_t dram_vals[] = {
        0x00000000, 0x00000100, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00010101, 0x01010101,
-       0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
+       0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
        0x00000100, 0x00000100, 0x00000000, 0x00000002,
        0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
        0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,