driver/ddr/fsl: Check condition for erratum A-009803

Add condition of checking the enabled of address parity
for erratum A-009803, if parity is not enabled, the
workaround of erratum A-009803 should not be applied.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 5039f5de0a9063b1aa25e252e2e4a33ea37f557e..d37e2474c91d0b8a2a02fb041865f5f52e14f525 100644 (file)
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -206,12 +206,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
        /* part 1 of 2 */
-       if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
-               ddr_out32(&ddr->ddr_sdram_rcw_2,
-                         regs->ddr_sdram_rcw_2 & ~0x0f000000);
+       if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+               if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+                       ddr_out32(&ddr->ddr_sdram_rcw_2,
+                                 regs->ddr_sdram_rcw_2 & ~0x0f000000);
+               }
+               ddr_out32(&ddr->err_disable, regs->err_disable |
+                         DDR_ERR_DISABLE_APED);
        }
-
-       ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
 #else
        ddr_out32(&ddr->err_disable, regs->err_disable);
 #endif
@@ -395,22 +397,24 @@ step2:
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
-               /* if it's RDIMM */
-               if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
-                       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-                               if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
-                                       continue;
-                               set_wait_for_bits_clear(&ddr->sdram_md_cntl,
-                                                       MD_CNTL_MD_EN |
-                                                       MD_CNTL_CS_SEL(i) |
-                                                       0x070000ed,
-                                                       MD_CNTL_MD_EN);
-                               udelay(1);
+               if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+                       /* if it's RDIMM */
+                       if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+                               for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+                                       if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+                                               continue;
+                                       set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+                                                               MD_CNTL_MD_EN |
+                                                               MD_CNTL_CS_SEL(i) |
+                                                               0x070000ed,
+                                                               MD_CNTL_MD_EN);
+                                       udelay(1);
+                               }
                        }
-               }
 
-               ddr_out32(&ddr->err_disable,
-                         regs->err_disable & ~DDR_ERR_DISABLE_APED);
+                       ddr_out32(&ddr->err_disable,
+                                 regs->err_disable & ~DDR_ERR_DISABLE_APED);
+               }
 #endif
        }
 #endif