powerpc/mpc8548cds: Fix network initialization

Add board_eth_init(). PCIe network card is also supported.
Put RGMII init after tsec_eth_init().
Skip initializing eTSEC3 and eTSEC4 with Carrier boards prior to ver 1.3.

Signed-off-by: Ebony Zhu
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index a8d57cdddefead190d69327a00e04b84868b60e2..d33ef7e83cb605dc6fd7148a5740d87ceaac94b4 100644 (file)
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -33,6 +33,9 @@
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <tsec.h>
+#include <fsl_mdio.h>
+#include <netdev.h>
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
@@ -287,7 +290,7 @@ void pci_init_board(void)
        fsl_pcie_init_board(first_free_busno);
 }
 
-int last_stage_init(void)
+void configure_rgmii(void)
 {
        unsigned short temp;
 
@@ -295,29 +298,77 @@ int last_stage_init(void)
        /* This is needed to get the RGMII working for the 1.3+
         * CDS cards */
        if (get_board_version() ==  0x13) {
-               miiphy_write(CONFIG_TSEC1_NAME,
+               miiphy_write(DEFAULT_MII_NAME,
                                TSEC1_PHY_ADDR, 29, 18);
 
-               miiphy_read(CONFIG_TSEC1_NAME,
+               miiphy_read(DEFAULT_MII_NAME,
                                TSEC1_PHY_ADDR, 30, &temp);
 
                temp = (temp & 0xf03f);
                temp |= 2 << 9;         /* 36 ohm */
                temp |= 2 << 6;         /* 39 ohm */
 
-               miiphy_write(CONFIG_TSEC1_NAME,
+               miiphy_write(DEFAULT_MII_NAME,
                                TSEC1_PHY_ADDR, 30, temp);
 
-               miiphy_write(CONFIG_TSEC1_NAME,
+               miiphy_write(DEFAULT_MII_NAME,
                                TSEC1_PHY_ADDR, 29, 3);
 
-               miiphy_write(CONFIG_TSEC1_NAME,
+               miiphy_write(DEFAULT_MII_NAME,
                                TSEC1_PHY_ADDR, 30, 0x8000);
        }
 
-       return 0;
+       return;
 }
 
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+       struct fsl_pq_mdio_info mdio_info;
+       struct tsec_info_struct tsec_info[4];
+       int num = 0;
+
+#ifdef CONFIG_TSEC1
+       SET_STD_TSEC_INFO(tsec_info[num], 1);
+       num++;
+#endif
+#ifdef CONFIG_TSEC2
+       SET_STD_TSEC_INFO(tsec_info[num], 2);
+       num++;
+#endif
+#ifdef CONFIG_TSEC3
+       /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
+       if (get_board_version() >= 0x13) {
+               SET_STD_TSEC_INFO(tsec_info[num], 3);
+               tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+               num++;
+       }
+#endif
+#ifdef CONFIG_TSEC4
+       /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
+       if (get_board_version() >= 0x13) {
+               SET_STD_TSEC_INFO(tsec_info[num], 4);
+               tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+               num++;
+       }
+#endif
+
+       if (!num) {
+               printf("No TSECs initialized\n");
+
+               return 0;
+       }
+
+       mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+       mdio_info.name = DEFAULT_MII_NAME;
+       fsl_pq_mdio_init(bis, &mdio_info);
+
+       tsec_eth_init(bis, tsec_info, num);
+       configure_rgmii();
+
+       return pci_eth_init(bis);
+}
+#endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_pci_setup(void *blob, bd_t *bd)

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index a99f8d592a4fec3d36d45e0b393bb56a6121d0fd..1a6ba692ab64620665f1986902a45272bb280917 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -464,6 +464,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_TSEC4_NAME      "eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
+#define CONFIG_PHY_MARVELL
+
 #define TSEC1_PHY_ADDR         0
 #define TSEC2_PHY_ADDR         1
 #define TSEC3_PHY_ADDR         2