flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
- {4, 32 * 1024}, /* 4 * 32kBytes sectors */
- {255, 128 * 1024}, /* 255 * 128kBytes sectors */
+OrgDef OrgIntel_28F256K3[] = {
+ {256, 128 * 1024}, /* 256 * 128kBytes sectors */
};
/*-----------------------------------------------------------------------
*/
+static void flash_vpp(int on)
+{
+ unsigned int tmp;
+
+ tmp = *(unsigned int *)(VERSATILE_FLASHCTRL);
+
+ if (on)
+ tmp |= VERSATILE_FLASHPROG_FLVPPEN;
+ else
+ tmp &= ~VERSATILE_FLASHPROG_FLVPPEN;
+
+ *(unsigned int *)(VERSATILE_FLASHCTRL) = tmp;
+}
+
unsigned long flash_init (void)
{
int i;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
+ flash_vpp(1);
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+ flash_vpp(0);
break;
default:
panic ("configured too many flash banks!\n");
int i;
OrgDef *pOrgDef;
- pOrgDef = OrgIntel_28F256L18T;
+ pOrgDef = OrgIntel_28F256K3;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
case FLASH_28F256L18T:
printf ("FLASH 28F256L18T\n");
break;
+ case FLASH_28F256K3:
+ printf ("FLASH 28F256K3\n");
+ break;
default:
printf ("Unknown Chip Type\n");
break;
mb ();
value = addr[0];
-
switch (value) {
case (FPW) INTEL_MANUFACT:
info->size = 0x02000000;
break; /* => 32 MB */
+ case (FPW)(INTEL_ID_28F256K3):
+ info->flash_id += FLASH_28F256K3;
+ info->sector_count = 256;
+ info->size = 0x02000000;
+ printf ("\Intel StrataFlash 28F256K3C device initialized\n");
+ break;
+
default:
info->flash_id = FLASH_UNKNOWN;
break;
printf ("\n");
}
+ flash_vpp(1);
start = get_timer (0);
last = start;
printf (" done\n");
}
}
+
+ flash_vpp(0);
+
return rcode;
}
port_width = 4;
#endif
+ flash_vpp(1);
+
/*
* handle unaligned start bytes
*/
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ flash_vpp(0);
return (rc);
}
wp += port_width;
data = (data << 8) | *src++;
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ flash_vpp(0);
return (rc);
}
wp += port_width;
}
if (cnt == 0) {
+ flash_vpp(0);
return (0);
}
data = (data << 8) | (*(uchar *) cp);
}
- return (write_data (info, wp, SWAP (data)));
+ rc = write_data (info, wp, SWAP (data));
+
+ flash_vpp(0);
+
+ return rc;
}
/*-----------------------------------------------------------------------
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
return (2);
}
+
+ flash_vpp(1);
+
flash_unprotect_sectors (addr);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
+ flash_vpp(0);
return (1);
}
}
*addr = (FPW) 0x00FF00FF; /* restore read mode */
+ flash_vpp(0);
return (0);
}
#define CFG_SERIAL0 0x101F1000
#define CFG_SERIAL1 0x101F2000
-#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY)
+#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV)
/*#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-#define CFG_ENV_IS_NOWHERE
+
+#define VERSATILE_SYS_BASE 0x10000000
+#define VERSATILE_SYS_FLASH_OFFSET 0x4C
+#define VERSATILE_FLASHCTRL (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
+#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
+
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
-#define CFG_MAX_FLASH_SECT 128
-#define CFG_ENV_SIZE 32768
+#define CFG_MAX_FLASH_SECT (256)
#define PHYS_FLASH_1 (CFG_FLASH_BASE)
+#define CFG_ENV_IS_IN_FLASH 1 /* env in flash instead of CFG_ENV_IS_NOWHERE */
+#define CFG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET 0x01f00000 /* environment starts here */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+
#endif /* __CONFIG_H */