CPCI405AB (special version of esd CPCI405) board added.

diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk
index 1ad3fc640ae2c9915dc87e342d5a74ca2327a18d..3b8797db6bb58bc0bb4ee640bba09df85b842bd1 100644 (file)
--- a/board/esd/cpci405/config.mk
+++ b/board/esd/cpci405/config.mk
@@ -28,5 +28,9 @@
 ifeq ($(BOARD_REVISION),CPCI4052)
 TEXT_BASE = 0xFFFC0000
 else
+ifeq ($(BOARD_REVISION),CPCI405AB)
+TEXT_BASE = 0xFFFC0000
+else
 TEXT_BASE = 0xFFFD0000
 endif
+endif

diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index b50716f35cdf5b01750f066f0839393d9d89596f..5a6a27c82503c4d4200f6e4488f4d47d8f910dc3 100644 (file)
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -37,7 +37,11 @@
 const unsigned char fpgadata[] =
 {
 #ifdef CONFIG_CPCI405_VER2
-# include "fpgadata_cpci4052.c"
+# ifdef CONFIG_CPCI405AB
+#  include "fpgadata_cpci405ab.c"
+# else
+#  include "fpgadata_cpci4052.c"
+# endif
 #else
 # include "fpgadata_cpci405.c"
 #endif
@@ -74,10 +78,10 @@ int board_pre_init (void)
        /*
         * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
         */
-       out32(IBM405GP_GPIO0_ODR, 0x00000000);        /* no open drain pins      */
-       out32(IBM405GP_GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
-       out32(IBM405GP_GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
-       out32(IBM405GP_GPIO0_OR, 0);                  /* pull prg low            */
+       out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
+       out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
+       out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
+       out32(GPIO0_OR, 0);                  /* pull prg low            */
 
        /*
         * Boot onboard FPGA
@@ -192,10 +196,10 @@ int cpci405_version(void)
         */
        cntrl0Reg = mfdcr(cntrl0);
        mtdcr(cntrl0, cntrl0Reg | 0x03000000);
-       out32(IBM405GP_GPIO0_ODR, in32(IBM405GP_GPIO0_ODR) & ~0x00180000);
-       out32(IBM405GP_GPIO0_TCR, in32(IBM405GP_GPIO0_TCR) & ~0x00180000);
+       out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
+       out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
        udelay(1000);                   /* wait some time before reading input */
-       value = in32(IBM405GP_GPIO0_IR) & 0x00180000;       /* get config bits */
+       value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
 
        /*
         * Restore GPIO settings
@@ -505,4 +509,44 @@ void ide_set_reset(int on)
 #endif /* CONFIG_IDE_RESET */
 #endif /* CONFIG_CPCI405_VER2 */
 
+#if 0 /* test-only */
+/* ------------------------------------------------------------------------- */
+
+u8 *dhcp_vendorex_prep (u8 * e)
+{
+       char *ptr;
+
+/* DHCP vendor-class-identifier = 60 */
+       if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
+               *e++ = 60;
+               *e++ = strlen (ptr);
+               while (*ptr)
+                       *e++ = *ptr++;
+       }
+/* my DHCP_CLIENT_IDENTIFIER = 61 */
+       if ((ptr = getenv ("dhcp_client_id"))) {
+               *e++ = 61;
+               *e++ = strlen (ptr);
+               while (*ptr)
+                       *e++ = *ptr++;
+       }
+
+       return e;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+u8 *dhcp_vendorex_proc (u8 * popt)
+{
+       if (*popt == 61)
+               return (u8 *)-1;
+       if (*popt == 43) {
+               printf("|%s|", popt+4); /* test-only */
+               return (u8 *)-1;
+       }
+       return NULL;
+}
+
 /* ------------------------------------------------------------------------- */
+#endif /* test-only */

diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c
index 85a9edc338fd34bc3095919c8a8a95fe31c8f2fd..02de050b742db02691667ed71f855dd88a7ce92c 100644 (file)
--- a/board/esd/cpci405/flash.c
+++ b/board/esd/cpci405/flash.c
@@ -86,11 +86,11 @@ unsigned long flash_init (void)
        /* Re-do sizing to get full correct info */
 
        if (size_b1) {
-               base_b1 = -size_b1;
                if (size_b1 < (1 << 20)) {
                        /* minimum CS size on PPC405GP is 1MB !!! */
                        size_b1 = 1 << 20;
                }
+               base_b1 = -size_b1;
                mtdcr (ebccfga, pb0cr);
                pbcr = mfdcr (ebccfgd);
                mtdcr (ebccfga, pb0cr);
@@ -103,11 +103,11 @@ unsigned long flash_init (void)
        }
 
        if (size_b0) {
-               base_b0 = base_b1 - size_b0;
                if (size_b0 < (1 << 20)) {
                        /* minimum CS size on PPC405GP is 1MB !!! */
                        size_b0 = 1 << 20;
                }
+               base_b0 = base_b1 - size_b0;
                mtdcr (ebccfga, pb1cr);
                pbcr = mfdcr (ebccfgd);
                mtdcr (ebccfga, pb1cr);

diff --git a/board/esd/cpci405/fpgadata_cpci405ab.c b/board/esd/cpci405/fpgadata_cpci405ab.c
new file mode 100644 (file)
index 0000000..29759a2
--- /dev/null
+++ b/board/esd/cpci405/fpgadata_cpci405ab.c
@@ -0,0 +1,1063 @@
+  0x1f,0x8b,0x08,0x08,0x22,0xe6,0xaf,0x3e,0x00,0x03,0x63,0x70,0x63,0x69,0x34,0x30,
+  0x35,0x61,0x62,0x5f,0x32,0x5f,0x30,0x34,0x2e,0x62,0x69,0x74,0x00,0xed,0xbd,0x0b,
+  0x74,0x5c,0xd5,0x99,0x26,0xfa,0x9f,0x7d,0x4e,0x49,0x47,0xaa,0x92,0xea,0xe8,0x45,
+  0x0a,0x30,0xe6,0xa8,0x24,0x48,0xe1,0x29,0xcb,0x65,0xd9,0x18,0xc7,0xd8,0xd2,0x71,
+  0xc9,0x76,0x2a,0xb1,0xd3,0x2e,0x1e,0x01,0x4f,0x0f,0x2b,0x53,0x26,0xee,0xb4,0x67,
+  0x96,0xc9,0x15,0x24,0xdd,0xed,0x61,0x72,0xd3,0x5b,0x25,0x19,0xcb,0xd8,0xe0,0xe2,
+  0x91,0x8e,0x93,0xd0,0xdc,0xb2,0x71,0x32,0x4e,0x86,0xe9,0x55,0xb6,0x21,0x36,0x90,
+  0xc0,0x91,0x10,0x44,0x7e,0xc4,0x28,0x0e,0x2b,0x6d,0x1e,0x17,0xca,0x44,0x21,0x02,
+  0x14,0xb7,0x70,0x3c,0x20,0x23,0x83,0xee,0xbf,0xf7,0x3e,0xaf,0x7a,0x08,0xe8,0x59,
+  0xbd,0xee,0x63,0x5d,0x2a,0x59,0xf0,0x73,0xb4,0x75,0x6a,0x3f,0xff,0x6f,0x7f,0xff,
+  0xff,0xed,0x2d,0xa8,0x0a,0x4e,0x88,0xff,0x01,0x48,0xeb,0xa1,0xee,0xeb,0xdd,0x5f,
+  0xff,0x4f,0x0b,0x63,0x57,0xff,0xc7,0xf6,0xff,0x18,0x5b,0xd8,0xf6,0xcd,0xaf,0x6f,
+  0x80,0x5b,0xa1,0xba,0xfd,0x5b,0x0b,0x62,0xdf,0xbe,0x7d,0xfe,0xc2,0x85,0xf0,0x75,
+  0xf0,0xb7,0xc7,0x62,0x0b,0xe6,0xc5,0x16,0xce,0x5b,0x10,0x83,0x0d,0x50,0x35,0xff,
+  0x9a,0x25,0xb1,0xab,0xf1,0xff,0xf0,0x57,0x00,0x7b,0xbb,0xa7,0xf1,0xf3,0xb3,0x1f,
+  0x7c,0xf5,0x1b,0x31,0xa0,0x12,0x00,0x54,0xc6,0xa4,0x14,0xfb,0xb7,0x1a,0x93,0x74,
+  0x09,0x68,0xe7,0xdc,0x18,0x98,0xec,0xbf,0xc1,0xfa,0x79,0x55,0x0c,0x74,0xef,0x7f,
+  0x4b,0x31,0x30,0x20,0x09,0xad,0x5f,0x87,0xfa,0x18,0xcc,0xf4,0x91,0x40,0xa1,0xdc,
+  0xf8,0x34,0x65,0xc8,0x8c,0x45,0xd8,0xe7,0xd3,0x97,0xa9,0xff,0xb8,0x22,0xca,0xbf,
+  0x55,0x19,0xfe,0xcf,0xe9,0x7a,0x34,0x24,0x90,0x58,0x4f,0x34,0x82,0xaf,0xc0,0xd0,
+  0x3a,0x87,0xf8,0x7b,0x4c,0xe9,0x0c,0x4c,0x9b,0xcb,0x68,0x80,0xca,0xfa,0x9e,0xe3,
+  0xfa,0x02,0xb5,0xd6,0x94,0xb3,0xfa,0x38,0x7c,0xab,0x39,0x38,0x29,0xe7,0xa0,0x9b,
+  0x57,0x5c,0x3b,0x03,0x4f,0x41,0xdb,0x84,0xba,0x83,0xe8,0xd0,0x4f,0xc3,0x6a,0x75,
+  0x3f,0x09,0x43,0x7f,0xaa,0x5d,0xf7,0x1f,0x26,0x79,0x85,0x77,0x5e,0xbf,0xef,0x38,
+  0x1c,0xd4,0xdb,0x32,0xaa,0x82,0x15,0xeb,0x59,0xae,0x57,0x56,0x4b,0x71,0xaa,0x3c,
+  0xf2,0xa5,0x8d,0xe0,0x8f,0x91,0x3d,0x12,0x7f,0x8f,0xd9,0xf4,0xa8,0x82,0xef,0x39,
+  0x12,0xa1,0x44,0xd7,0x7f,0x46,0xc2,0xc6,0x9c,0x1e,0x68,0xa6,0xfd,0x12,0x51,0xfc,
+  0x39,0x32,0xa1,0xa4,0x78,0xa5,0x9b,0xc6,0x61,0x0a,0x96,0xd2,0xc0,0xd3,0xf2,0x5c,
+  0x18,0xa6,0xed,0x81,0xda,0x47,0x7b,0xf7,0x90,0x31,0xf2,0x64,0xac,0x32,0x27,0x65,
+  0x14,0xfe,0x9e,0xbc,0xf4,0x0b,0x98,0x86,0x4e,0x1a,0x7c,0xcb,0xff,0xaa,0xf1,0x8f,
+  0xfa,0x33,0x74,0xde,0x3e,0xf9,0x1c,0xbc,0x0f,0x9d,0x10,0x9c,0x90,0x27,0x81,0xbf,
+  0xc7,0xd0,0x1e,0xc5,0xf7,0x1c,0x30,0x03,0x9a,0xdc,0x6c,0x0c,0xa8,0x4b,0xb4,0x35,
+  0x8d,0x7e,0x15,0x8e,0xc1,0xa2,0xcc,0xe5,0x39,0x79,0x44,0xd1,0x59,0x99,0x61,0x5f,
+  0x14,0xdb,0x15,0x36,0x23,0xb4,0xa2,0xd9,0xd8,0xae,0xff,0xad,0xa9,0x66,0xc8,0x3c,
+  0xfd,0x15,0xb8,0x88,0xfa,0x73,0x72,0x3b,0x4e,0x20,0xf6,0x5d,0xbe,0x35,0x70,0x10,
+  0xf4,0x6c,0x02,0x88,0x04,0x69,0x3a,0xc7,0x54,0x43,0xe4,0x9e,0x08,0x95,0x22,0x26,
+  0xb6,0x6b,0x52,0xd2,0x58,0x19,0x5d,0x9a,0x0d,0x87,0x68,0xf3,0x78,0xe8,0x12,0x42,
+  0xe0,0xae,0x5c,0x6b,0x4a,0x5d,0x57,0xfd,0x43,0xfa,0x20,0xfd,0x1f,0x63,0xfe,0xcd,
+  0x64,0x9d,0x78,0x4f,0x02,0x3b,0x76,0x2a,0x17,0xdb,0xd3,0x3f,0x87,0xd4,0xd2,0x81,
+  0x4c,0x84,0x06,0x62,0xbd,0xf7,0xd2,0x67,0xf5,0xc5,0xa7,0xfd,0x31,0xf9,0x24,0xe1,
+  0xef,0x31,0x2e,0xc3,0x76,0xf9,0x3a,0x87,0x83,0x13,0x55,0x17,0xe2,0xef,0x41,0xa7,
+  0x51,0x39,0xd1,0xb2,0x4e,0x99,0x90,0xae,0xc9,0x63,0xbb,0x32,0x15,0xbc,0x5d,0xfb,
+  0x7c,0xac,0x7f,0x3a,0x68,0x20,0x27,0x6f,0x22,0x6f,0x43,0xfb,0x40,0x20,0x2b,0xef,
+  0x25,0x63,0x70,0x20,0x55,0x93,0x93,0xdf,0x16,0xe3,0x95,0xa8,0x7b,0x48,0x3b,0x04,
+  0x51,0xaa,0x76,0x93,0x1d,0xda,0x56,0xd0,0x4d,0x55,0x27,0x8d,0xb0,0x15,0x9a,0x0d,
+  0x7c,0x72,0x52,0xf4,0xb3,0x09,0x0f,0x63,0x9d,0xe7,0xe6,0x2f,0x5e,0x4c,0x66,0xc3,
+  0x7e,0xba,0x3b,0xa7,0x6e,0x26,0xf7,0xc2,0x23,0x7d,0x7f,0xfd,0xae,0xba,0x39,0x3e,
+  0x01,0xbc,0x7f,0x12,0x8d,0x38,0xa6,0x10,0xbd,0x55,0x5d,0x48,0xee,0x89,0x3f,0xc0,
+  0xde,0xf3,0x85,0x74,0x00,0x7a,0xb5,0x0d,0x79,0x35,0x86,0xef,0xe1,0xe3,0x3e,0xd6,
+  0xb4,0x0f,0x3e,0x80,0x8e,0xc3,0x73,0x1f,0xdd,0x7e,0xd5,0xaa,0x0f,0x56,0x1c,0xc8,
+  0x06,0xa2,0xf2,0x4f,0xe9,0xdb,0xe6,0xcf,0x69,0x34,0x2b,0x7f,0x20,0xbe,0x2b,0x01,
+  0x79,0x98,0x84,0xa5,0x5a,0x2d,0xed,0xcd,0xa2,0xd9,0x01,0xf3,0xa8,0x9c,0xd7,0x27,
+  0xe1,0x5a,0x29,0x48,0xe5,0x93,0xc0,0xdf,0xa3,0x6a,0xa3,0x70,0x1e,0x3a,0x92,0xaa,
+  0x26,0x57,0x90,0x23,0x89,0x98,0xb1,0x34,0x43,0x14,0x38,0x52,0xdd,0x6e,0xc8,0x19,
+  0x79,0x50,0x7c,0x17,0x55,0x36,0xc0,0x13,0xa4,0x2d,0x81,0xc3,0x74,0xa5,0xba,0x0d,
+  0xf6,0x18,0x35,0x19,0xf9,0xaf,0x2a,0xb6,0x65,0xe6,0x2c,0xf7,0x67,0x48,0x0a,0x78,
+  0x1f,0x86,0x7c,0xad,0xf0,0x04,0xb4,0x19,0x97,0x8c,0xac,0x5a,0x48,0xef,0x81,0x96,
+  0xe5,0xea,0x49,0xf2,0x38,0x6c,0x21,0x2d,0x26,0x96,0x79,0x5e,0x8c,0x85,0xaa,0x28,
+  0xb0,0x1f,0xa2,0x89,0x39,0xd7,0x5f,0xdf,0xb8,0x65,0x8b,0xde,0x9c,0xa8,0xba,0x9e,
+  0xbc,0x98,0xde,0xa2,0x5f,0x65,0xf8,0x35,0x12,0xe7,0x6e,0x04,0x0e,0x07,0xf2,0x70,
+  0x38,0xd9,0x06,0x6d,0xd4,0x7f,0x95,0x71,0x54,0x6a,0x6f,0xec,0xa7,0x0d,0x59,0x75,
+  0xf8,0xba,0x05,0x70,0x39,0x95,0xcf,0xc8,0xbc,0xcc,0xae,0xcb,0xf6,0x62,0x7d,0x3a,
+  0x57,0x7c,0xe5,0x3e,0x79,0x34,0x7e,0x5e,0xeb,0x58,0x19,0xbc,0x4f,0xde,0x80,0xc6,
+  0x52,0x23,0x98,0x91,0xdf,0x94,0xbb,0x45,0x7d,0x46,0x43,0xe7,0xa1,0xf3,0xcb,0x35,
+  0x99,0x07,0xce,0xa9,0xbf,0x96,0xda,0x93,0x81,0x93,0x72,0x63,0xcf,0xaf,0xe7,0x1f,
+  0xe0,0x65,0xc4,0x78,0x2d,0xd6,0xf2,0x90,0x83,0x36,0x4d,0xed,0x23,0xa7,0xfb,0x7e,
+  0x46,0xe6,0x40,0x64,0x4b,0x75,0x73,0x7c,0xb0,0xfb,0xe7,0xe0,0xa7,0xe4,0x84,0x68,
+  0xbb,0xea,0x1b,0x82,0xfd,0x91,0xa8,0xb1,0x4d,0x23,0xbf,0x8a,0xed,0x5e,0x9e,0xc5,
+  0x8e,0x22,0x8a,0xda,0x03,0x29,0x56,0xe7,0x41,0xb1,0xbe,0x42,0x4d,0x7b,0x55,0x6c,
+  0xfb,0x75,0xea,0xfd,0xe4,0x4d,0xf8,0x29,0xcc,0x31,0x12,0xf7,0x55,0xb7,0xd2,0x6d,
+  0xd2,0x95,0x2b,0x58,0xdb,0xc5,0x58,0x64,0x9b,0x78,0x3f,0xa7,0x6a,0x76,0x55,0x8e,
+  0xc2,0x5b,0xd0,0x9e,0x88,0xfe,0x50,0x6e,0x85,0x23,0xc9,0x03,0x29,0xac,0xcf,0x98,
+  0x58,0x17,0x11,0xd8,0xcb,0xca,0xdc,0x11,0xcc,0x7c,0x6e,0x28,0xf2,0x6e,0x04,0x9b,
+  0xa3,0xc9,0xa3,0xda,0x79,0xda,0xc1,0xca,0x1c,0x15,0x73,0x23,0xa2,0x65,0x71,0x4c,
+  0xdb,0xa1,0x96,0x76,0xa5,0xc8,0xb0,0xd1,0x0e,0x81,0xbe,0x06,0x18,0x1c,0x5e,0xd1,
+  0x0e,0x38,0xa6,0x47,0xad,0xf7,0x28,0x11,0x78,0x52,0x6a,0xce,0xaa,0xd9,0x39,0xd7,
+  0x46,0xee,0xa5,0x7b,0x68,0xcd,0x3e,0xb2,0x44,0xf9,0x19,0x7d,0x84,0xfa,0xb3,0xe4,
+  0xa8,0xf0,0x54,0x11,0xb1,0xbe,0x56,0x54,0xc7,0x48,0xad,0x22,0x9b,0xba,0xb9,0x38,
+  0x44,0x6a,0x60,0x7b,0xa6,0x95,0xe2,0xfa,0x3a,0x8a,0xfe,0x8a,0xaf,0xaf,0x59,0x6c,
+  0x7d,0x99,0xea,0xe2,0x0a,0x15,0xb6,0xaa,0xcd,0x66,0x55,0x77,0x7a,0x16,0xfc,0x37,
+  0xb8,0x82,0xfa,0xbb,0xc9,0xb0,0x18,0xd3,0x88,0x8a,0x6b,0x30,0x3b,0x5f,0xaf,0xdd,
+  0xdc,0xf0,0x35,0xf2,0x6c,0xdf,0x82,0xfc,0x9a,0xc5,0xfe,0xd9,0xca,0x73,0xf9,0xc7,
+  0xb3,0xc1,0xcd,0xf2,0x51,0xe1,0x98,0xd5,0xcb,0x1e,0xd5,0xa6,0x16,0xce,0x02,0x7f,
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+  0xbd,0xa1,0xb5,0x6e,0x18,0xf0,0x09,0xfd,0xa2,0x2e,0xb9,0xf5,0x61,0x70,0xac,0x57,
+  0xc0,0x72,0x0b,0x97,0x1d,0x80,0x06,0xf7,0x3d,0x8d,0x88,0xcb,0x55,0x26,0xe2,0xf2,
+  0x83,0x4a,0xab,0xc4,0x26,0xad,0x96,0x81,0x2b,0x18,0x2e,0xa7,0xdc,0xb9,0xda,0x02,
+  0x5f,0x1e,0xa8,0xcf,0xae,0xd8,0x57,0xd7,0x02,0x09,0x5a,0xaf,0xfb,0xb2,0x75,0x61,
+  0x25,0x61,0xd6,0xe7,0x56,0x64,0xad,0x55,0x0a,0xaa,0x19,0x80,0x7a,0x9c,0x2d,0x10,
+  0x43,0x1f,0xc6,0x9d,0x19,0x03,0x31,0x36,0x7f,0xa4,0xc5,0x92,0xd8,0x6a,0x21,0x8e,
+  0x35,0x2a,0x75,0xe0,0x33,0x10,0x97,0x2f,0x52,0x16,0x21,0x5a,0x28,0x1a,0xd6,0xe5,
+  0xaf,0x24,0x25,0x25,0x25,0x25,0xb1,0xad,0xc3,0xf7,0x18,0x44,0x83,0x3e,0x11,0xfc,
+  0xd0,0xf8,0x69,0x45,0x95,0xad,0x9f,0x3e,0x16,0x56,0x71,0xcb,0x00,0x03,0x1c,0x82,
+  0xaf,0x68,0x4c,0xc1,0x2e,0xf8,0x06,0xfa,0x20,0x22,0x20,0x48,0x12,0xc7,0xdf,0x41,
+  0x93,0xb0,0x0c,0xfe,0xa8,0x02,0xaa,0x28,0xdc,0x0a,0x21,0x8a,0x46,0x3f,0x6f,0xfb,
+  0x95,0x70,0x71,0x5a,0xf8,0x1f,0x63,0x65,0xdc,0x86,0x63,0x07,0x97,0x91,0x9a,0xf5,
+  0xec,0x40,0x23,0x64,0xf9,0x5e,0x83,0x7f,0x2b,0x87,0x63,0x0f,0x2e,0xb7,0x5b,0x86,
+  0x68,0xbd,0x01,0x7e,0x88,0x09,0x18,0x3d,0x06,0xb1,0x81,0x40,0x0c,0x61,0xfd,0x59,
+  0xa5,0xdd,0xe4,0x4f,0xac,0xb1,0x30,0x56,0x76,0x29,0xdd,0xe8,0x96,0xd1,0x3f,0xf7,
+  0x2a,0xdd,0x03,0xa1,0x18,0x37,0x52,0x03,0xfc,0x89,0x85,0x29,0x06,0x22,0x27,0x73,
+  0xef,0xc4,0x83,0xcb,0x69,0x7c,0x73,0x88,0x3d,0xb1,0xc6,0x22,0x29,0xc5,0xb9,0x7b,
+  0x5f,0x21,0xfc,0x3c,0xab,0x33,0x1a,0x31,0xe1,0xf9,0xa9,0xfd,0x5d,0xe8,0x94,0xa5,
+  0x46,0x58,0x09,0x75,0x68,0xe0,0x24,0x90,0x84,0x61,0x20,0xfd,0x90,0xe2,0xe2,0xbb,
+  0x12,0x88,0x4d,0xd7,0x51,0x2d,0xa5,0x84,0x24,0x36,0x3d,0x0a,0x0d,0x6b,0x4c,0x13,
+  0x40,0x04,0x1c,0x23,0xb4,0x71,0xa3,0x9e,0x61,0x1c,0xf4,0xf0,0x27,0x60,0x7f,0xd7,
+  0x2a,0xc2,0x70,0xf9,0xea,0x50,0x8d,0x00,0x68,0xaf,0x61,0x58,0x7e,0x5e,0x5a,0xa5,
+  0xdc,0x8e,0x30,0xfa,0xd7,0xa1,0xba,0xe7,0x95,0xdb,0xe9,0x43,0xdc,0xa8,0x60,0x4f,
+  0xbe,0x18,0xaa,0xb3,0xfb,0x47,0x5a,0x05,0xec,0x47,0x9f,0x0f,0x55,0x09,0x5c,0xae,
+  0x44,0x83,0x3f,0xb9,0x26,0x54,0x65,0x95,0x49,0x5a,0xb8,0x8c,0xf8,0x2e,0x70,0xb9,
+  0x8b,0xbd,0x70,0x7e,0xcf,0x8e,0xd4,0x0d,0xa1,0xba,0x41,0x7b,0xbc,0xea,0xa1,0x95,
+  0x7e,0x89,0x55,0xf5,0x7e,0x29,0xc5,0x70,0x39,0xa1,0x0c,0x4a,0xdf,0xc6,0x7d,0xcb,
+  0x45,0x09,0x7b,0x7d,0x19,0x38,0x2b,0x9a,0x69,0x28,0x55,0x11,0xc2,0x65,0xd5,0xdc,
+  0x13,0x4a,0xad,0x42,0x5c,0x56,0xd6,0xf3,0x27,0xce,0x1a,0x5c,0x99,0x52,0x36,0x4b,
+  0xb3,0xa1,0x8b,0x6a,0x79,0x34,0x6a,0xb9,0xe1,0x8b,0xe0,0x93,0x2f,0x52,0xcd,0x9e,
+  0x1b,0xd2,0xf5,0xb0,0x81,0x5e,0xcc,0xb6,0x8d,0xf7,0x8b,0x8d,0x64,0x02,0xc7,0x8b,
+  0x3d,0xa9,0x48,0xd8,0xe3,0x65,0xf0,0xf1,0x52,0xb3,0x0e,0x2e,0xaf,0x8a,0x70,0x43,
+  0xe0,0xb2,0xdd,0x87,0x38,0xee,0x3d,0x5a,0x6c,0x65,0xa0,0x0e,0x0d,0xb3,0x31,0xe6,
+  0xe3,0x06,0xd5,0xf4,0x15,0x81,0x3a,0xc3,0x6e,0x17,0xc1,0x7d,0x56,0x63,0xd6,0x17,
+  0xc0,0x49,0x92,0x64,0x65,0x22,0x52,0x17,0x7b,0xa2,0xe3,0x13,0xc3,0x6e,0x97,0xaa,
+  0xc4,0xc5,0x80,0x73,0x5c,0xe6,0x06,0x43,0x6a,0xca,0xa7,0x80,0xfd,0x5d,0x04,0x10,
+  0x8e,0xf5,0x88,0x4a,0x18,0x2e,0x67,0x75,0x15,0x0d,0xeb,0x09,0xd8,0xed,0x32,0x14,
+  0x7b,0x43,0x87,0x06,0x5b,0x5f,0xcd,0xb4,0xc2,0x7e,0xe2,0x94,0xc1,0xa5,0xf9,0x03,
+  0xb8,0xd2,0xc0,0xf5,0xd5,0x0a,0x97,0x41,0x25,0x1a,0xca,0xb7,0x71,0xb5,0xb0,0x27,
+  0x92,0xc8,0xbf,0xaf,0x4c,0x55,0x44,0xac,0xae,0xab,0x88,0xf8,0x2e,0x81,0x55,0xac,
+  0x33,0x37,0x4a,0x77,0xb3,0x27,0x56,0x1f,0xe2,0x8c,0x04,0xdd,0x08,0xdc,0x28,0x2b,
+  0x30,0x00,0xcd,0x49,0x75,0x1d,0x69,0x64,0x86,0xa1,0x6a,0xf2,0x45,0x60,0x4a,0x56,
+  0xbb,0x14,0x5c,0xfd,0x35,0x86,0x7c,0x23,0x0c,0xc1,0x15,0xcb,0x6b,0x92,0x5d,0x49,
+  0x78,0x8e,0xe1,0x29,0x3e,0x31,0x06,0x35,0xc3,0x5e,0x5f,0xb8,0x9a,0xba,0xaf,0x0f,
+  0x88,0x65,0x15,0x5b,0x35,0xab,0xae,0x17,0xd6,0x0b,0xa3,0xa0,0xce,0xe8,0x4e,0xd8,
+  0x29,0xe8,0x16,0x43,0x35,0x09,0xd8,0x0e,0x06,0x9f,0x68,0xd6,0x78,0x25,0x56,0x20,
+  0x2e,0xaf,0x88,0x5b,0xb8,0x8c,0x00,0x7d,0x5f,0xbf,0x71,0xab,0x14,0xe2,0xb8,0xac,
+  0xd9,0xeb,0xcb,0x48,0xd6,0x35,0x22,0x0a,0xd7,0xa1,0x11,0x6b,0x5c,0xe1,0xf3,0xd5,
+  0x19,0x43,0xc9,0x24,0x3e,0x01,0x77,0xbc,0xd4,0x54,0x1c,0x77,0xd3,0x8d,0x7a,0x4f,
+  0x02,0x87,0xba,0xf1,0x6e,0x9f,0x30,0x34,0x46,0x7a,0x0c,0xb0,0x46,0xcc,0xc6,0x65,
+  0xa5,0xfa,0x0a,0xdb,0x90,0xc8,0x36,0x03,0x71,0x59,0x01,0xbb,0x5d,0x5f,0x91,0x6f,
+  0x30,0x5e,0x1c,0x99,0xbf,0xb0,0x8a,0x19,0x0f,0x8e,0x34,0x2f,0xdc,0xc6,0x9f,0x9c,
+  0xbc,0x7a,0xa1,0x3b,0x5e,0x89,0x15,0x77,0xd4,0xcd,0xea,0xab,0x84,0x26,0xb3,0x95,
+  0x01,0xf4,0x5f,0x23,0x40,0x93,0x3b,0x9a,0x05,0x16,0x58,0xbe,0x17,0x7d,0xb8,0x8d,
+  0xcb,0xa1,0xc4,0xf3,0xf5,0xf3,0xfb,0x76,0xa0,0x61,0x70,0xe3,0xdf,0x1e,0x97,0xe7,
+  0x4e,0xaf,0xfe,0xee,0xb3,0xd3,0xe7,0x0e,0x6e,0x9a,0x3b,0xbd,0xf6,0xd0,0x6f,0xff,
+  0x74,0xce,0xc5,0x65,0xf7,0x3d,0x0b,0xa6,0xd7,0x4c,0x37,0x4c,0x9f,0x43,0x5c,0x9e,
+  0x5e,0xfb,0xc2,0x6f,0xff,0x7c,0xce,0xc5,0x65,0xb7,0xcc,0xb5,0x1c,0x97,0x47,0x05,
+  0x2e,0xd7,0x5f,0xc3,0x71,0xf9,0x2f,0x18,0x2e,0xdf,0x73,0xde,0x29,0x43,0xfa,0x60,
+  0x37,0x44,0x8c,0xea,0x59,0x83,0x68,0x1c,0x47,0x83,0xfd,0xf1,0xc5,0x2c,0x37,0x9c,
+  0x32,0xdc,0x6f,0x59,0x9e,0xcc,0x63,0x80,0x01,0x6e,0x19,0x01,0x31,0x02,0x7d,0x8a,
+  0x0d,0xe7,0xc3,0x16,0x12,0xfe,0xd6,0x2c,0x13,0x8d,0xe3,0x60,0x7b,0xd7,0xc2,0xf7,
+  0x38,0x98,0x55,0x6a,0x38,0x75,0x9e,0xb9,0x94,0x5d,0x63,0xc6,0xe0,0x75,0xe8,0x67,
+  0xa7,0xfe,0x85,0xe1,0x29,0x4a,0xec,0x32,0x33,0x7c,0x0d,0x33,0x9c,0x32,0xd5,0x7d,
+  0x64,0x37,0xec,0x33,0xe6,0x68,0xa5,0x86,0x53,0xa3,0x19,0xfa,0x87,0x19,0x6e,0x7d,
+  0x66,0xee,0x1f,0xfb,0xbb,0x34,0xa8,0x8c,0x61,0xb7,0x7c,0x0b,0xfb,0xc7,0x32,0xac,
+  0x27,0xd8,0x3f,0x44,0xb1,0xdf,0xb3,0x35,0xe6,0xfe,0xfa,0xf1,0x72,0xef,0xc1,0xfe,
+  0x51,0xdc,0xc6,0xf4,0x94,0xed,0x1f,0x3e,0x5e,0xce,0x0f,0x9a,0xcb,0xf7,0xb3,0x46,
+  0xc5,0x1f,0xd6,0x14,0x9f,0xe3,0x50,0xf0,0x11,0x31,0xbd,0x4f,0xf3,0x59,0xba,0xf4,
+  0x63,0x7e,0x18,0x0c,0x7e,0xda,0xd7,0xfc,0x1b,0x7e,0x3a,0xa7,0xa7,0xa7,0xcd,0xf2,
+  0xc6,0xff,0xa7,0xcb,0xd8,0x6b,0x59,0x2b,0x35,0xdc,0x42,0x62,0xc5,0xf1,0x3d,0x88,
+  0x3d,0x57,0x4b,0xd6,0xe0,0xbf,0x62,0x2d,0x6b,0x65,0x0c,0xe7,0xf3,0x89,0x6b,0xf9,
+  0x63,0x56,0xa0,0x67,0x2d,0xab,0x45,0x6b,0xd9,0x63,0xfc,0x2f,0xad,0xe5,0x59,0x47,
+  0xd1,0x38,0xbe,0xef,0x5b,0xc2,0xf0,0xae,0x65,0xf5,0x7f,0x65,0x2d,0xc3,0xa7,0x58,
+  0xcb,0x86,0x30,0x80,0x2d,0x6a,0x77,0x2d,0x7f,0xa2,0x4f,0xf8,0x34,0xbe,0xee,0xd3,
+  0xf4,0x33,0xae,0x65,0x98,0xf9,0xf3,0xd9,0x5a,0xfe,0x7f,0x5f,0x99,0x4f,0xfe,0xc4,
+  0x40,0x97,0x08,0xff,0x77,0xfc,0x4b,0xff,0xca,0x5f,0xfd,0xec,0xf3,0xd9,0xe7,0xb3,
+  0xcf,0x67,0x9f,0xcf,0x3e,0x9f,0x7d,0x3e,0xfb,0x7c,0xf6,0xf9,0xff,0xc5,0x87,0xef,
+  0x97,0x08,0xdf,0x2f,0x19,0xff,0x4f,0xd7,0xe5,0xb3,0xcf,0x67,0x9f,0xcf,0x3e,0x9f,
+  0x7d,0x3e,0xfb,0x7c,0xf6,0xf9,0xec,0xf3,0xd9,0xe7,0xff,0xee,0x4f,0x8c,0x89,0xfb,
+  0x60,0xd1,0xe2,0x18,0x50,0x96,0xbe,0x92,0x63,0x60,0x54,0x7d,0xba,0xdf,0xe3,0xe5,
+  0x7d,0x31,0xc8,0x4a,0xee,0x7b,0x06,0xfe,0xf7,0xe2,0xba,0xfe,0x5f,0xe4,0x2c,0xd3,
+  0xd9,0xbd,0xa4,0x00,0x00,

diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
new file mode 100644 (file)
index 0000000..a265fcd
--- /dev/null
+++ b/include/configs/CPCI405AB.h
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP           1       /* This is a PPC405 CPU         */
+#define CONFIG_4xx             1       /* ...member of PPC4xx family   */
+#define CONFIG_CPCI405         1       /* ...on a CPCI405 board        */
+#define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
+#define CONFIG_CPCI405AB        1       /* ...and special AB version    */
+
+#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE                9600
+#define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
+
+#if 0
+#define CONFIG_PREBOOT                                                          \
+        "crc32 f0207004 ffc 0;"                                                 \
+        "if cmp 0 f0207000 1;"                                                  \
+        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+        "else;echo Old CRC is bad;fi"
+#endif
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_RAMBOOTCOMMAND                                                  \
+       "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "     \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
+       "bootm ffc00000 ffca0000"
+#define CONFIG_NFSBOOTCOMMAND                                                  \
+       "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
+       "bootm ffc00000"
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
+#define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
+
+#define CONFIG_MII             1       /* MII PHY management           */
+#define        CONFIG_PHY_ADDR         0       /* PHY address                  */
+
+#define CONFIG_RTC_M48T35A     1               /* ST Electronics M48 timekeeper */
+
+#if 0 /* test-only */
+#define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT |  \
+                                CONFIG_BOOTP_VENDOREX)
+#else
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT)
+#endif
+
+#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_DHCP    | \
+                               CFG_CMD_PCI     | \
+                               CFG_CMD_IRQ     | \
+                               CFG_CMD_IDE     | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_DATE    | \
+                               CFG_CMD_JFFS2   | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_MII     | \
+                               CFG_CMD_EEPROM  )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_WATCHDOG                        /* watchdog disabled            */
+
+#define        CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                   /* undef to save memory         */
+#define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
+
+#undef CFG_HUSH_PARSER                 /* use "hush" command parser    */
+#ifdef CFG_HUSH_PARSER
+#define        CFG_PROMPT_HUSH_PS2     "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
+#else
+#define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS    16              /* max number of command args   */
+#define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START      0x0400000       /* memtest works on     */
+#define CFG_MEMTEST_END                0x0C00000       /* 4 ... 12 MB in DRAM  */
+
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+         57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR  0x100000        /* default load address */
+#define CFG_EXTBDINFO  1               /* To use extended board_into (bd_t) */
+
+#define        CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE        1       /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_HOST        PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
+                                        /* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET       1       /* reset for ide supported      */
+
+#define        CFG_IDE_MAXBUS          1               /* max. 1 IDE busses    */
+#define        CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define        CFG_ATA_BASE_ADDR       0xF0100000
+#define        CFG_ATA_IDE0_OFFSET     0x0000
+
+#define CFG_ATA_DATA_OFFSET    0x0000  /* Offset for data I/O                  */
+#define        CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
+#define CFG_ATA_ALT_OFFSET     0x0000  /* Offset for alternate registers       */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_FLASH_BASE         0xFFFC0000
+#define CFG_MONITOR_BASE       CFG_FLASH_BASE
+#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN         (128 * 1024)    /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     256     /* max number of sectors on one chip    */
+
+#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
+#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
+
+#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
+#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
+#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
+#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
+#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM    1       /* use NVRAM for environment vars       */
+#define CFG_ENV_SIZE           0x0ff8          /* Size of Environment vars     */
+#define CFG_ENV_ADDR           \
+       (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))   /* Env  */
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars*/
+                                   /* total size of a CAT24WC08 is 1024 bytes */
+#endif
+
+#define CFG_NVRAM_BASE_ADDR    0xf0200000              /* NVRAM base address   */
+#define CFG_NVRAM_SIZE         (32*1024)               /* NVRAM size           */
+#define CFG_NVRAM_VXWORKS_OFFS 0x6900          /* Offset for VxWorks eth-addr  */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CFG_I2C_SPEED          400000  /* I2C speed and slave address */
+#define CFG_I2C_SLAVE          0x7F
+
+#define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT28WC08             */
+#define CFG_I2C_EEPROM_ADDR_LEN        1       /* Bytes of address             */
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW   0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
+                                       /* 16 byte page write mode using*/
+                                       /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE                16384   /* For IBM 405 CPUs, older 405 ppc's    */
+                                        /* have only 8kB, 16kB is save here     */
+#define CFG_CACHELINE_SIZE     32      /* ...                  */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM     0xFF800000      /* FLASH bank #0        */
+#define FLASH_BASE1_PRELIM     0xFFC00000      /* FLASH bank #1        */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization                                  */
+#define CFG_EBC_PB0AP           0x92015480
+#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization                                  */
+#define CFG_EBC_PB1AP           0x92015480
+#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization                                       */
+#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CFG_LED_ADDR            0xF0000380
+
+/* Memory Bank 3 (CompactFlash IDE) initialization                              */
+#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization                                     */
+/*#define CFG_EBC_PB4AP           0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1     */
+#define CFG_EBC_PB4AP           0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1     */
+#define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 5 (optional Quart) initialization                                */
+#define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 6 (FPGA internal) initialization                                 */
+#define CFG_EBC_PB6AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR           0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_FPGA_BASE_ADDR      0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE           0x00
+#define CFG_FPGA_STATUS         0x02
+#define CFG_FPGA_TS             0x04
+#define CFG_FPGA_TS_LOW         0x06
+#define CFG_FPGA_TS_CAP0        0x10
+#define CFG_FPGA_TS_CAP0_LOW    0x12
+#define CFG_FPGA_TS_CAP1        0x14
+#define CFG_FPGA_TS_CAP1_LOW    0x16
+#define CFG_FPGA_TS_CAP2        0x18
+#define CFG_FPGA_TS_CAP2_LOW    0x1a
+#define CFG_FPGA_TS_CAP3        0x1c
+#define CFG_FPGA_TS_CAP3_LOW    0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET      0x0001
+#define CFG_FPGA_MODE_DUART_RESET   0x0002
+#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CFG_FPGA_MODE_TS_CLEAR      0x2000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0    0x0001
+#define CFG_FPGA_STATUS_DIP1    0x0002
+#define CFG_FPGA_STATUS_DIP2    0x0004
+#define CFG_FPGA_STATUS_FLASH   0x0008
+#define CFG_FPGA_STATUS_TS_IRQ  0x1000
+
+#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE       64*1024     /* 64kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
+#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
+
+#endif /* __CONFIG_H */