]> git.sur5r.net Git - u-boot/commitdiff
sunxi: Tune H3 DRAM PLL to improve lock time
authorJens Kuske <jenskuske@gmail.com>
Fri, 19 Aug 2016 11:40:46 +0000 (13:40 +0200)
committerHans de Goede <hdegoede@redhat.com>
Fri, 26 Aug 2016 14:58:37 +0000 (16:58 +0200)
The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
arch/arm/mach-sunxi/clock_sun6i.c

index d4dff1e3463e5a532aa79645ecd08dc8d2651209..be9fcfda0e35591c01c462ed3778d3d72a6bf165 100644 (file)
@@ -116,7 +116,9 @@ struct sunxi_ccm_reg {
        u32 mipi_bias_cfg;      /* 0x240 MIPI Bias config */
        u32 pll9_bias_cfg;      /* 0x244 PLL9 Bias config */
        u32 pll10_bias_cfg;     /* 0x248 PLL10 Bias config */
-       u32 reserved21[13];
+       u32 reserved21[5];
+       u32 pll5_tuning_cfg;    /* 0x260 PLL5 Tuning config */
+       u32 reserved21_5[7];
        u32 pll1_pattern_cfg;   /* 0x280 PLL1 Pattern config */
        u32 pll2_pattern_cfg;   /* 0x284 PLL2 Pattern config */
        u32 pll3_pattern_cfg;   /* 0x288 PLL3 Pattern config */
@@ -223,6 +225,11 @@ struct sunxi_ccm_reg {
 #define CCM_PLL11_CTRL_UPD             (0x1 << 30)
 #define CCM_PLL11_CTRL_EN              (0x1 << 31)
 
+#define CCM_PLL5_TUN_LOCK_TIME(x)      (((x) & 0x7) << 24)
+#define CCM_PLL5_TUN_LOCK_TIME_MASK    CCM_PLL5_TUN_LOCK_TIME(0x7)
+#define CCM_PLL5_TUN_INIT_FREQ(x)      (((x) & 0x7f) << 16)
+#define CCM_PLL5_TUN_INIT_FREQ_MASK    CCM_PLL5_TUN_INIT_FREQ(0x7f)
+
 #if defined(CONFIG_MACH_SUN50I)
 /* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
 #define AHB1_ABP1_DIV_DEFAULT          0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
index 15272c9e7176c753ed5f5c897eda75f63983c114..ed8cd9bbb376eb261abab6e1a28eab4afa8eab80 100644 (file)
@@ -148,6 +148,12 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
        const int max_n = 32;
        int k = 1, m = 2;
 
+#ifdef CONFIG_MACH_SUN8I_H3
+       clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
+                       CCM_PLL5_TUN_INIT_FREQ_MASK,
+                       CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
+#endif
+
        if (sigma_delta_enable)
                writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);