MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
P1010RDB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB
P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT
+P1010RDB_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND
+P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND
P1010RDB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SDCARD
P1010RDB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH
P1010RDB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SDCARD
#ifdef CONFIG_P1010RDB
#define CONFIG_P1010
+#define CONFIG_NAND_FSL_IFC
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#ifdef CONFIG_NAND /* NAND Boot */
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
+#else
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#endif /* CONFIG_NAND_SPL */
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+/* Don't relocate CCSRBAR while in NAND_SPL */
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
/*
* Memory map
*
| CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
+
/* NAND Flash Timing Params */
#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
FTIM0_NAND_TWP(0x0C) | \
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+
+/* NAND boot: 8K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE 0x2000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffb00000
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
* SPI interface will not be available in case of NAND boot SPI CS0 will be
* used for SLIC
*/
+#ifndef CONFIG_NAND_U_BOOT
/* eSPI - Enhanced SPI */
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#endif
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_NAND_U_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#else
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
--- /dev/null
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# Copyright 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+CONFIG_SYS_TEXT_BASE_SPL := 0xff800000
+PAD_TO := 0xff802000
+
+include $(TOPDIR)/config.mk
+
+nandobj := $(OBJTREE)/nand_spl/
+
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
+ $(LDFLAGS_FINAL)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS = start.o resetvec.o ticks.o
+COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+ nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(nandobj)board/$(BOARDDIR)
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+ @rm -f $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+ @rm -f $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+ @rm -f $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+ @rm -f $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+ @rm -f $(obj)law.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_ifc.c:
+ @rm -f $(obj)nand_boot_fsl_ifc.c
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \
+ $(obj)nand_boot_fsl_ifc.c
+
+$(obj)ns16550.c:
+ @rm -f $(obj)ns16550.c
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)resetvec.S:
+ @rm -f $(obj)resetvec.S
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+
+$(obj)fixed_ivor.S:
+ @rm -f $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+ @rm -f $(obj)start.S
+ ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
+
+$(obj)ticks.S:
+ @rm -f $(obj)ticks.S
+ ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
+
+$(obj)tlb.c:
+ @rm -f $(obj)tlb.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+ @rm -f $(obj)tlb_table.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_boot.c:
+ @rm -f $(obj)nand_boot.c
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+
+#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); }
+
+unsigned long ddr_freq_mhz;
+
+void sdram_init(void)
+{
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
+ out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+ out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+ out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
+ out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+
+ if (ddr_freq_mhz < 700) {
+ out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667);
+ out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667);
+ out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667);
+ out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667);
+ out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667);
+ out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667);
+ out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667);
+ out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667);
+ out_be32(&ddr->ddr_wrlvl_cntl,
+ CONFIG_SYS_DDR_WRLVL_CONTROL_667);
+ } else {
+ out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800);
+ out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800);
+ out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800);
+ out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800);
+ out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800);
+ out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800);
+ out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800);
+ out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800);
+ out_be32(&ddr->ddr_wrlvl_cntl,
+ CONFIG_SYS_DDR_WRLVL_CONTROL_800);
+ }
+
+ out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+ out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+ out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
+
+ /* mimic 500us delay, with busy isync() loop */
+ udelay(100);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+ set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, ddr_ratio;
+ unsigned long bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+ ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+ ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* Initialize the DDR3 */
+ sdram_init();
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
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